1111111111111111 IIIIII IIIII 1111111111 11111 11111 1111111111 11111 1111111111 1111111111 11111111
`US 20110099460Al
`
`c19) United States
`c12) Patent Application Publication
`Dusija et al.
`
`c10) Pub. No.: US 2011/0099460 Al
`Apr. 28, 2011
`(43) Pub. Date:
`
`(54) NON-VOLATILE MEMORY AND METHOD
`WITH POST-WRITE READ AND ADAPTIVE
`RE-WRITE TO MANAGE ERRORS
`
`(76)
`
`Inventors:
`
`Gautam Ashok Dusija, Milpitas,
`CA (US); Jian Chen, Menlo Park,
`CA (US); Chris Avila, Sunnyvale,
`CA (US); Jianmin Huang,
`Sunnyvale, CA (US); Lee M.
`Gavens, Milpitas, CA (US)
`
`(21) Appl. No.:
`
`12/642,728
`
`(22) Filed:
`
`Dec.18,2009
`
`Related U.S. Application Data
`
`(63) Continuation-in-part of application No. 12/607,522,
`filed on Oct. 28, 2009.
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`GllC 29152
`(2006.01)
`(2006.01)
`G06F 11110
`(2006.01)
`G06F 12/16
`(2006.01)
`G06F 12/00
`(52) U.S. Cl. .. 714/773; 711/103; 711/173; 711/E12.103;
`711/E12.001; 714/El 1.04
`ABSTRACT
`
`(57)
`
`Data errors in non-volatile memory inevitably increase with
`usage and with higher density of bits stored per cell. The
`memory is configured to have a first portion operating with
`less error but of lower density storage, and a second portion
`operating with a higher density but less robust storage. Input
`data is written and staged in the first portion before being
`copied to the second portion. An error management provides
`checking the quality of the copied data for excessive error
`bits. The copying and checking are repeated on a different
`location in the second portion until either a predetermined
`quality is satisfied or the number or repeats exceeds a prede(cid:173)
`termined limit. The error management is not started when a
`memory is new with little or no errors, but started after the
`memory has aged to a predetermined amount as determined
`by the number of erase/program cycling its has experienced.
`
`HOST 80
`
`FLASH MEMORY DEVICE 90
`
`Controller
`102
`
`Memory Chip 100
`
`On-Chip
`Control
`Circuit
`110
`
`Memory Array
`200
`
`SENSE MODULES
`
`Data Latches
`1/0
`
`440
`
`FIRM(cid:173)
`WARE
`
`ECC
`Processor
`
`60
`
`62
`
`--------►
`
`Micron Ex. 1010, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 1 of 25
`
`US 2011/0099460 Al
`
`HOST 80
`
`,
`
`FLASH MEMORY DEVICE 90
`
`Memory Chip 100
`
`On-Chip
`Control
`Circuit
`110
`
`112
`./
`
`State
`Mach-
`ine
`
`" 480 _,/
`430~
`. ,
`
`440
`
`Controller
`102
`
`.
`....-
`
`,
`
`FIRM-
`WARE
`
`,.._ L-- 60
`
`ECC
`Processor
`
`,.._ L-- 62
`
`◄--------►
`
`Memory Array
`200
`
`SENSE MODULES
`
`Data Latches
`1/0
`
`■
`
`■
`
`■
`
`■
`
`FIG. 1
`
`Micron Ex. 1010, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 2 of 25
`
`US 2011/0099460 Al
`
`Control
`gate
`
`/
`
`20 _130
`"'------
`14 j
`..__ ... c:_ 16
`Source
`Drain
`
`10
`
`FIG. 2
`
`2
`4
`\
`
`3f -
`'T
`11~ 10
`
`-
`l 16 T
`
`....
`
`H
`
`----------
`
`200
`l/
`
`-T
`
`
`~ .,_ 10 Ht
`
`-T
`
`
`-4 ~ f-0
`
`H ~ ----------
`
`' . . .
`
`-T
`
`
`
`....................
`
`-l t-
`
`H~
`
`H ...
`
`-
`T
`
`' ' '
`'
`
`-
`T
`
`(/)
`Q}
`C
`
`0---
`
`I.,._
`
`-
`T
`
`.
`.
`
`-
`T
`
`34-
`
`i----- 36
`
`Bit lines
`
`FIG. 3
`
`Micron Ex. 1010, p. 3
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 3 of 25
`
`US 2011/0099460 Al
`
`BLO BL 1 BL2 BL3 BL4 BL5
`
`Blm-1 Blm
`
`200
`
`44
`SGD
`
`' ' ' ' '
`: : : :
`I
`:
`I
`-~~.;....;...;..~~~~~.;....;...;...;....;...+r+,,.;.-;~~.;...;:..;.,:: :+++::::
`
`Wln
`42
`20
`
`WL3
`
`WL2
`
`WL1
`
`WLO
`
`I
`I
`I
`
`I
`I
`I
`
`I
`I
`I
`
`t
`I
`I
`
`·-:0;:;0:0:
`
`::~:~:~:
`
`I
`I
`I
`
`I
`I
`I
`
`: : L
`:::: )i
`
`70
`
`::-:-:1
`
`~=8
`
`SGS
`44
`
`Source Line
`
`34
`
`FIG. 4
`
`Micron Ex. 1010, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 4 of 25
`
`US 2011/0099460 Al
`
`READ/WRITE CIRCUITS 270A. 270B
`
`480 .----~
`Sense l)
`Sense
`Module
`Module
`1
`2
`
`Sense
`Module
`p
`
`l"--36
`
`Bit line
`
`drain
`10
`'---
`
`Cell
`1
`
`source
`
`i1
`
`Cell
`2
`
`Cell
`p
`
`34
`
`11,
`
`(
`
`Source
`Line
`
`11r CLSRC
`
`ITOT ,,
`
`GND
`
`FIG. 5A
`
`Sense Module~
`
`Sense Amp
`
`490
`
`FIG. 5B
`
`Micron Ex. 1010, p. 5
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 5 of 25
`
`US 2011/0099460 Al
`
`1 200
`
`ERASE BLOCK m
`
`30 0
`,/
`
`■
`
`■
`
`■
`
`ERASE BLOCK 1
`
`ERASE BLOCK 0
`
`36 -
`
`BL1
`
`------,
`
`BLO
`
`FIG. 6
`
`"\
`3 00
`
`v
`
`BLx
`
`-
`
`WLy -
`
`--
`
`■
`
`■
`
`■
`
`-
`
`-
`
`WL31 -
`WL16 -
`4 4~
`WL15
`.T
`42
`-::L
`WLO
`4 47
`
`Micron Ex. 1010, p. 6
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 6 of 25
`
`US 2011/0099460 Al
`
`Erased I
`
`I
`I
`I
`I
`
`(0) G::\1
`Memory J
`
`State
`
`(1)
`
`(2)
`
`1
`
`Binary Bit}
`
`Threshold Window - - - - - -
`
`I
`irV1
`
`: I
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`
`I 8
`
`I
`I
`I
`I
`I
`I
`
`0
`
`Programming into two states represented by a 1-bit code
`
`FIG. 7
`
`Micron Ex. 1010, p. 7
`Micron v. Vervain
`IPR2021-01547
`
`

`

`t :-:
`.... 0 =
`.... 0 = ""O = O" -....
`('D = ..... t "e -....
`
`~ .....
`
`(')
`
`~ .....
`
`(')
`
`~ .....
`""O
`
`> ....
`
`--- 0
`....
`0 ....
`N
`rJJ
`c
`
`0
`O'I
`.i;...
`1,0
`1,0
`0
`
`0 ....
`-....J
`.....
`rJJ =(cid:173)
`....
`0 ....
`
`Ul
`N
`
`('D
`('D
`
`N
`~CIO
`N
`
`FIG. 8
`
`Programming into four states represented by a 3-bit code
`
`4
`
`VrH
`
`I
`I
`I
`I
`!Lower Bit:
`I
`I
`
`Upper Bit JI~
`
`Middle Bit
`
`(2)
`
`(1)
`
`(0)
`
`Threshold Window
`
`Erase
`
`Micron Ex. 1010, p. 8
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 8 of 25
`
`US 2011/0099460 Al
`
`- - - - - - - - Data Page 70' - - - - - - - - - -
`
`User Data
`
`72'7
`
`74'7 76'7
`
`FIG. 9
`
`-Jcr
`
`-2cr
`
`-lcr
`
`20
`
`30
`
`FIG. 10A
`
`Sigma Value
`
`Cumulative value
`
`Cumulative %
`
`Example Error
`Rate at EOL
`
`1 cr
`1.645cr
`1.960cr
`2cr
`2.576cr
`3cr
`3.2906cr
`4cr
`5cr
`6cr
`7cr
`
`1.59E-01
`5.00E-02
`2.50E-02
`2.28E-02
`5.00E-03
`1.35E-03
`5.00E-04
`3.17E-05
`2.87E-07
`9.86E-10
`1.28E-12
`
`15.86500000%
`5.00000000%
`2.50000000%
`2.27500000%
`0.50000000%
`0 .13500000%
`0.05000000%
`0.00316700%
`0.00028670%
`0.00000010%
`0.00000000%
`
`FIG. 10B
`
`...
`1 bits
`...
`2 bits
`...
`4 bits
`...
`8 bits
`30 bits
`42 bits
`
`---
`
`Micron Ex. 1010, p. 9
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 9 of 25
`
`US 2011/0099460 Al
`
`ERROR
`SOURCE
`
`DESCRIPTION
`
`(A)
`
`Epw(Neve)
`
`Bit errors that are present soon after the page is
`written. They increase with Neve, the number of
`program-erase cycling, which is a measure of the
`endurance of a block.
`
`(B)
`
`EoR(T, Neve)
`
`Bit errors due to data retention at EOL ("end of life")
`T = Temperature
`
`(C)
`
`ERo(NR, Neve)
`
`Bit errors due to read disturb which increase with the
`number of reads NR and endurance
`
`FIG. 11
`
`(A)
`
`(B)
`
`(C)
`
`Eror(Neve, NR) = Epw(Neve) + EoR(T, Neve)+ ERo(NR, Neve)
`
`(fresh after 1 year) Epw(Ncvc) + EoR(85°C, 1) + ERo(1M, 1)
`= 3 + 2 + 0 = 5 bits
`Ernr(1, 1M)
`Epw(10K) ~ 10, EoR(85°C, 10K) ~ 10, and ERo(1M,
`1 OK) ~ 1
`= 10+10+1 =21 bits
`
`(memory at EOL)
`Ernr(10K, 1M)
`
`Examples of Total Errors at the beginning and end of life
`FIG. 12
`
`ECCoESIGN
`
`Must be designed to correct for worst case
`Eror(after EOL cycling, Data Retention specification)
`
`FIG. 13
`
`Micron Ex. 1010, p. 10
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 10 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`Second Portion 420
`(less robust but higher density storage)
`
`WRITE
`Input data
`page
`
`...
`
`e-,zz"'''"Z
`
`first copy of data page , ,, 2 , z z, -' .J
`
`First Portion 410
`(more robust but lower density storage)
`
`FIG. 14A
`
`Micron Ex. 1010, p. 11
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 11 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`Second Portion 420
`(less robust but higher density storage)
`
`Input data
`page
`- - -► 12Z?'.!/l~!]:?
`If Post-Write
`Read
`FAILED
`
`First Portion 410
`(more robust but lower density storage)
`
`REWRITE
`
`r <2 « zz second copy of data page r2 u « <1
`
`FIG. 14B
`
`Micron Ex. 1010, p. 12
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 12 of 25
`
`US 2011/0099460 Al
`
`Configuring the memory into first and second portions, the first
`portion having memory cells operating with a margin of error
`larger than that of the second portion
`
`500
`
`u
`
`Write to Second Portion
`
`,.
`
`Programming a first copy of a group of input data in the second
`portion
`
`Post-Write Read
`
`,.
`
`Reading the first copy from the second portion to check for error
`after a predefined time
`
`Does the error exceed a predetermined number of error bits?
`
`H
`
`YES
`Rewrite to Robust First Portion ,.
`
`NO
`
`Programming a second copy of the
`group of input data in the first portion
`
`540
`LJ
`
`'"'
`Identifying the last written copy as valid data for subsequent read
`
`,1,
`
`The group of input data is done storing in the nonvolatile memory
`
`510
`_..,)
`
`520
`
`u
`
`530
`l__..J
`
`550
`L__...i
`560
`L,,
`
`FIG. 15
`
`Micron Ex. 1010, p. 13
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 13 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`Second Portion 420
`(Jess robust but higher density storage)
`
`r,,zz:::-,,,;
`
`first copy of data page , z, 1 ·' z, z ,,
`
`r
`
`WRITE
`
`Input data
`page
`
`\
`
`~
`
`First Portion 410
`(more robust but lower density storage)
`Second Section 412 (for rewrites)
`
`First Section 411 (for caching)
`
`,
`
`cached copy of data page
`
`,...
`
`,...
`
`,;:
`
`r
`
`.,.
`
`FIG. 16A
`
`Micron Ex. 1010, p. 14
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 14 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`
`Second Portion 420
`
`first copy of data page n n a ,oz 7•
`
`First Portion 410
`
`Second Section 412 (for rewrites)
`
`t nun n
`~
`I
`I
`I
`I
`I
`Post-Write I
`I
`Read
`PASSED
`I
`I
`\
`\
`\
`
`First Section 411 (for caching)
`
`\ "
`
`FIG. 16B
`
`Micron Ex. 1010, p. 15
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 15 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`Second Portion 420
`
`~
`I
`I
`I
`I
`I
`Post-Write I
`Read
`I
`FAILED
`I
`I
`I
`\
`\
`\
`ltt..
`
`First Portion 410
`
`Second Section 412 (for rewrites)
`
`First Section 411 (for caching)
`
`RITE
`
`FIG. 16C
`
`Micron Ex. 1010, p. 16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 16 of 25
`
`US 2011/0099460 Al
`
`Configuring the memory into first and second portions, the first
`portion having memory cells operating with a margin of error
`larger than that of the second portion
`
`600
`l--,J
`
`Caching in Robust First Portion,,,
`
`Programming a cached copy of a group of input data in a first
`section of the first portion
`
`602
`__,)
`
`Write to Second Portion
`
`' .
`
`Programming a first copy of the group of input data in the second
`portion
`
`610
`_.,)
`
`Post Write Read
`
`'"
`Reading the first copy from the second portion to check for error
`after a predefined time
`
`620
`~
`
`Does the error exceed a predetermined number of error bits?
`
`630
`
`w
`
`YES
`
`NO
`
`R ewrite to Robust First Portion ,,
`
`632
`Reading the cached copy of the group of
`input data from the first section of the first _../
`portion
`
`Programming the cached copy as a
`642
`second copy of the group of input data in _../
`a second section of the first portion
`
`"'
`Identifying the last written copy as valid data for subsequent read
`
`w
`
`The group of input data is done storing in the nonvolatile memory
`
`650
`__,)
`660
`__,)
`
`FIG. 17
`
`Micron Ex. 1010, p. 17
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 17 of 25
`
`US 2011/0099460 Al
`
`/ 200
`
`I Ncyc (m) -
`
`30 2
`l.,,-'
`
`30 0
`L/
`
`ERASE BLOCK m
`
`■
`
`■
`
`■
`
`-
`
`WLy -
`
`--
`
`■
`
`■
`
`■
`
`WL31 -
`WL16 -
`
`-
`
`-
`
`4 4::i
`WL15
`.::r
`42
`~
`WL0
`4 47
`
`30 2
`Ncyc (1) - v
`
`"'.,
`
`3 00
`l---'
`
`Ncyc (0) -"' 3 02
`
`I
`
`I
`
`ERASE BLOCK 1
`
`ERASE BLOCK 0
`
`i-----, 36 --
`
`BL0
`
`BL1
`
`FIG. 18
`
`BLx
`
`Micron Ex. 1010, p. 18
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 18 of 25
`
`US 2011/0099460 Al
`
`Providing a non-volatile memory organized into
`erase blocks of memory cells, wherein the memory
`cells of each erase block are erased together and
`age with the number of erase/program cycling of
`each block
`
`I'---
`
`700
`
`1'
`
`Providing an error management for correcting errors t'----
`associated with an aging memory device
`
`710
`
`1'
`
`Tracking the age of each block by maintaining a hot I'---
`count that records the number of erase/program
`cycling each block has undergone
`
`720
`
`1'
`
`Is the Hot Count of a memory block >
`a predetermined hot count threshold?
`
`730
`
`y
`
`11r
`
`~740
`
`N
`1 Ir
`
`~750
`
`Enable the error
`management for the
`rest of the life of the
`memory
`
`Do not enable the
`error management
`yet
`
`FIG. 19
`
`Micron Ex. 1010, p. 19
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 19 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`Second Portion 420 (D3)
`
`(4) 1st Post(cid:173)
`Write Read on
`D3 Block m
`PASSED
`
`f
`I
`I
`I
`(3) 1st D3
`I
`Page n
`I
`Write (Folding)
`\
`\
`\
`,/
`!
`\
`
`(2) D1
`Page n
`STAGING
`
`I
`
`D3 Block m
`1st copy of D3 page n zz::zzzzz=1
`
`First Portion 410 (D1)
`
`Second Section 412 (D1 for staging)
`
`First Section 411
`(D1 for caching small fragments)
`(1 )From HOST 1.!::::=============:!.1
`
`Example of successful D1 to D3 Folding
`
`FIG. 20A
`
`Micron Ex. 1010, p. 20
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 20 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`Second Portion 420 (D3)
`
`(6) 2nd Post(cid:173)
`Write Read on
`03 Block m
`P SSE0
`
`(4') 1st Post(cid:173)
`Write Read on
`03 Block m
`
`_A_IL_E_0_,-,1(7:Y,I,,~i:
`
`Block m'
`2nd copy of D3 data page
`
`I
`I
`I
`I
`(3) 1st 03 I
`Page n
`I
`Write (Folding}
`\
`
`(2) 01 \
`Page n
`STAGING
`
`:
`'.\
`\
`
`First Portion 410
`
`Second Section 412 (D1 for staging)
`
`(5) 2nd 03
`Block m
`Write
`
`First Section 411
`(01 for caching small fragments)
`
`Example of Read Error after 1st D1 to D3 Folding
`
`FIG. 20B
`
`Micron Ex. 1010, p. 21
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 21 of 25
`
`US 2011/0099460 Al
`
`MEMORY ARRAY 200
`Second Portion 420 (D3)
`
`~A~l=.:LE=.:□~.,,--1l,,2_2~_-< __ ·\,_:··_.,:_"·_'r_i1_· "_Y·_· :_):_:i _d_;s,_::;,_· ,_-· ,, __ ,-~_,,~_' _~1 __
`
`(6') 2nd Post(cid:173)
`Write Read on
`D3
`
`(4') 1st Post(cid:173)
`Write Read on
`D3 Block m
`
`I
`I
`I
`I
`I
`1
`
`(3) 1st 03
`Page n
`Write (Folding~
`I
`/
`(2) 01 \
`Page n \ {
`STAGING'-\.
`
`(5) 2nd D3
`Block/'
`Write
`
`·t_z"?_.z__1J
`
`First Portion 410
`
`Second Section 412 (D1 for staging)
`
`m.3
`m.2
`D1 Virtual Block m.1
`Staged D1 copy of
`data a es n.1, n.2, n.3
`
`First Section 411
`(D1 for caching small fragments)
`
`Example of Read Error after 2nd D1 to D3 Folding
`
`FIG. 20C
`
`Micron Ex. 1010, p. 22
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 22 of 25
`
`US 2011/0099460 Al
`
`File System Configuration File
`
`PARAMETER
`
`DESCRIPTION
`
`E_pw_check
`
`a variable set in File System Configuration File to specify at
`what# of ECC bits level, a D3 block is consider high risk
`and restart of D1 to D3 folding to a new D3 block is
`required
`
`a variable is needed in File System Configuration File for
`ECC threshold
`- maintaining SLC threshold to compare against in order to
`SLC
`make a decision to continue with EPWR or not
`
`EPWR_enable_ controlled in File System Configuration File.
`0 = not set (Default);
`flag
`1 = set when EPWR is enabled
`
`Hot_count_
`enable_flag
`
`0 = not enabled;
`1 = enabled
`
`a variable set in File System Configuration File to specify at
`Hot_count_
`what hot count level, EPWR is needed. If hot count of all
`threshold_EPWR D3 blocks is< hot count threshold, even EPWR enable flag
`is on, EPWR process is not triggered
`
`EPWR_verify_
`page_budget
`
`a variable set in File System Configuration File to specify
`how many pages can be read during 1 phase of EPWR
`
`EPWR retries
`
`a variable in File System Configuration File to limit number
`of retry attempts
`
`D3_Block_max a variable in File System Configuration File to limit the total
`- retries
`number of retry attempts on a D3 block over lifetime
`
`FIG. 21
`
`Micron Ex. 1010, p. 23
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 23 of 25
`
`US 2011/0099460 Al
`
`(
`
`Start
`
`800
`
`,.
`-...
`..... D1 to D3 Folding ___, 810
`
`-
`N
`
`Is a D3 block
`completed?
`y
`
`,,
`
`EPWR enabled?
`
`___, 812
`
`,,,--- 820
`N
`
`r 830
`
`,,
`
`,,,,-- 850
`
`Retain D3 block;
`Retire D1 copies of
`D3 block
`
`Process more blocks?
`
`(870
`
`- y
`N
`
`Retire D3 block;
`Retain D1 copies of
`D3 block
`
`Put Card in Read
`Only Mode
`
`1.--- 872
`
`'-----
`
`-
`
`.,...
`
`-
`
`.,...
`
`y
`1 .
`Process EPWR
`~ ("Enhanced Post Write Read")
`,,,--- 840
`N
`
`Error Rate>
`Threshold?
`ly
`I
`
`+
`
`(860
`
`Redo D3 block on N
`a new block?
`
`y
`
`,,
`
`(869
`
`Redo D1 to D3
`folding on a new
`block
`
`1 '
`
`(
`
`DONE
`
`1,
`
`90
`8
`
`FIG. 22A
`
`Micron Ex. 1010, p. 24
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Apr. 28, 2011 Sheet 24 of 25
`
`US 2011/0099460 Al
`
`Do EPWR? 820
`
`EPWR_enable_flag = enabled?
`y
`
`'-- 822
`
`N
`
`" - -
`
`1 r
`
`N -
`
`Hot_count_enable_flag = enabled?
`y
`
`'-- 824
`
`, r
`
`D3 Block's Hot Count >
`Hot_count_threshold_EPWR?
`y
`
`'-- 826
`
`-...
`
`y
`
`1r
`
`,r
`
`N
`
`N . ...
`No EPWR
`Pfi
`ocessing
`D 3 Block
`med good
`assu
`G OTO 850
`
`Process EPWR
`GOTO 830
`
`FIG. 22B
`
`Micron Ex. 1010, p. 25
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Apr. 28, 2011 Sheet 25 of 25
`
`US 2011/0099460 Al
`
`Process EPWR 830
`
`FROM 820
`
`--,,
`
`Process time
`available?
`y
`
`N - Remember the
`-
`last EPWR
`step
`
`'------- 832
`
`- Start/Continue on
`-
`a D3 block
`'------- 834
`
`~ 838
`
`Transfer page with
`ECC to Controller ~
`for EDC checking
`
`Select next
`page
`
`,,
`
`'------- 836
`
`a
`
`'--- 844
`
`N
`
`...
`# ECC errors > N -
`E_pw_check?
`
`'--- 840
`
`y
`
`H
`
`Reach end of
`the D3 block?
`Y'--- 842
`
`(
`
`862
`
`-
`
`I
`
`Redo D3 block? 860
`______ ""'I--/ 868
`I
`I
`(Optional)
`1
`-I
`Is this retry > EPWR_retries? .
`I Correct D1 data
`·
`1
`N_l
`y
`I with ECC and
`I
`~ restaged~n_9~I
`_ __ 1
`_ _ _
`1
`A
`:
`(Optional)
`i 866 -..__,
`:......... y
`I
`D3 block
`I
`NI
`total retries>
`Check D1 data;
`f-.__~ 864
`Is ECC errors> ~ Block max retries? I
`-
`I
`' ECC_threshold
`Retire D3 block L v865
`SLC?
`'
`-
`L - - - - , - - - - . . .1
`'
`N
`,
`:
`: ............• i. ................................ :
`
`,,
`
`Redo 03 Block
`GOTO 869
`
`,,
`No redo••
`MEMORY OLD 03 BLOCK GOOD
`GOTO 870
`GOTO 850
`
`FIG. 22C
`
`Micron Ex. 1010, p. 26
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2011/0099460 Al
`
`Apr. 28, 2011
`
`1
`
`NON-VOLATILE MEMORY AND METHOD
`WITH POST-WRITE READ AND ADAPTIVE
`RE-WRITE TO MANAGE ERRORS
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application is a continuation-in-part of U.S.
`application Ser. No. 12/607,522 filed on Oct. 28, 2009.
`
`BACKGROUND OF THE INVENTION
`
`[0002] This application relates to the operation of re-pro(cid:173)
`grammable non-volatile memory systems such as semicon(cid:173)
`ductor flash memory, and, more specifically, to handling and
`efficient managing of errors in memory operations.
`[0003] Solid-state memory capable of nonvolatile storage
`of charge, particularly in the form of EEPROM and flash
`EEPROM packaged as a small form factor card, has recently
`become the storage of choice in a variety of mobile and
`handheld devices, notably information appliances and con(cid:173)
`sumer electronics products. Unlike RAM (random access
`memory) that is also solid-state memory, flash memory is
`non-volatile, and retaining its stored data even after power is
`turned off. Also, unlike ROM (read only memory), flash
`memory is rewritable similar to a disk storage device. In spite
`of the higher cost, flash memory is increasingly being used in
`mass storage applications. Conventional mass storage, based
`on rotating magnetic medium such as hard drives and floppy
`disks, is unsuitable for the mobile and handheld environment.
`This is because disk drives tend to be bulky, are prone to
`mechanical failure and have high latency and high power
`requirements. These undesirable attributes make disk-based
`storage impractical in most mobile and portable applications.
`On the other hand, flash memory, both embedded and in the
`form of a removable card are ideally suited in the mobile and
`handheld environment because of its small size, low power
`consumption, high speed and high reliability features.
`[0004] Flash EEPROM is similar to EEPROM ( electrically
`erasable and programmable read-only memory) in that it is a
`non-volatile memory that can be erased and have new data
`written or "programmed" into their memory cells. Both uti(cid:173)
`lize a floating (unconnected) conductive gate, in a field effect
`transistor structure, positioned over a channel region in a
`semiconductor substrate, between source and drain regions.
`A control gate is then provided over the floating gate. The
`threshold voltage characteristic of the transistor is controlled
`by the amount of charge that is retained on the floating gate.
`That is, for a given level of charge on the floating gate, there
`is a corresponding voltage (threshold) that must be applied to
`the control gate before the transistor is turned "on" to permit
`conduction between its source and drain regions. In particu(cid:173)
`lar, flash memory such as Flash EEPROM allows entire
`blocks of memory cells to be erased at the same time.
`[0005] The floating gate can hold a range of charges and
`therefore can be programmed to any threshold voltage level
`within a threshold voltage window. The size of the threshold
`voltage window is delimited by the minimum and maximum
`threshold levels of the device, which in tum correspond to the
`range of the charges that can be programmed onto the floating
`gate. The threshold window generally depends on the
`memory device's characteristics, operating conditions and
`history. Each distinct, resolvable threshold voltage level
`range within the window may, in principle, be used to desig(cid:173)
`nate a definite memory state of the cell.
`
`It is common in current commercial products for
`[0006]
`each storage element of a flash EEPROM array to store a
`single bit of data by operating in a binary mode, where two
`ranges of threshold levels of the storage element transistors
`are defined as storage levels. The threshold levels of transis(cid:173)
`tors correspond to ranges of charge levels stored on their
`storage elements. In addition to shrinking the size of the
`memory arrays, the trend is to further increase the density of
`data storage of such memory arrays by storing more than one
`bit of data in each storage element transistor. This is accom(cid:173)
`plished by defining more than two threshold levels as storage
`states for each storage element transistor, four such states (2
`bits of data per storage element) now being included in com(cid:173)
`mercial products. More storage states, such as 16 states per
`storage element, are also being implemented. Each storage
`element memory transistor has a certain total range (window)
`of threshold voltages in which it may practically be operated,
`and that range is divided into the number of states defined for
`it plus margins between the states to allow for them to be
`clearly differentiated from one another. Obviously, the more
`bits a memory cell is configured to store, the smaller is the
`margin of error it has to operate in.
`[0007] The transistor serving as a memory cell is typically
`programmed to a "programmed" state by one of two mecha(cid:173)
`nisms. In "hot electron injection," a high voltage applied to
`the drain accelerates electrons across the substrate channel
`region. At the same time a high voltage applied to the control
`gate pulls the hot electrons through a thin gate dielectric onto
`the floating gate. In "tunneling injection," a high voltage is
`applied to the control gate relative to the substrate. In this way,
`electrons are pulled from the substrate to the intervening
`floating gate. While the term "program" has been used his(cid:173)
`torically to describe writing to a memory by injecting elec(cid:173)
`trons to an initially erased charge storage unit of the memory
`cell so as to alter the memory state, it has now been used
`interchangeable with more common terms such as "write" or
`"record."
`[0008] The memory device may be erased by a number of
`mechanisms. For EEPROM, a memory cell is electrically
`erasable, by applying a high voltage to the substrate relative to
`the control gate so as to induce electrons in the floating gate to
`tunnel through a thin oxide to the substrate channel region
`(i.e., Fowler-Nordheim tunneling.) Typically, the EEPROM
`is erasable byte by byte. For flash EEPROM, the memory is
`electrically erasable either all at once or one or more mini(cid:173)
`mum erasable blocks at a time, where a minimum erasable
`block may consist of one or more sectors and each sector may
`store 512 bytes or more of data.
`[0009] The memory device typically comprises one or
`more memory chips that may be mounted on a card. Each
`memory chip comprises an array of memory cells supported
`by peripheral circuits such as decoders and erase, write and
`read circuits. The more sophisticated memory devices also
`come with a controller that performs intelligent and higher
`level memory operations and interfacing.
`[0010] There are many commercially successful non-vola(cid:173)
`tile solid-state memory devices being used today. These
`memory devices may be flash EEPROM or may employ other
`types of nonvolatile memory cells. Examples of flash memory
`and systems and methods of manufacturing them are given in
`U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063,
`and 5,661,053, 5,313,421 and 6,222,762. In particular, flash
`memory devices with NAND string structures are described
`in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935. Also non-
`
`Micron Ex. 1010, p. 27
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2011/0099460 Al
`
`Apr. 28, 2011
`
`2
`
`volatile memory devices are also manufactured from memory
`cells with a dielectric layer for storing charge. Instead of the
`conductive floating gate elements described earlier, a dielec(cid:173)
`tric layer is used. Such memory devices utilizing dielectric
`storage element have been described by Eitan et al., "NROM:
`A Novel Localized Trapping, 2-Bit Nonvolatile Memory
`Cell," IEEE Electron Device Letters, vol. 21, no. 11, Novem(cid:173)
`ber 2000, pp. 543-545. An ONO dielectric layer extends
`across the channel between source and drain diffusions. The
`charge for one data bit is localized in the dielectric layer
`adjacent to the drain, and the charge for the other data bit is
`localized in the dielectric layer adjacent to the source. For
`example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a
`nonvolatile memory cell having a trapping dielectric sand(cid:173)
`wiched between two silicon dioxide layers. Multi-state data
`storage is implemented by separately reading the binary
`states of the spatially separated charge storage regions within
`the dielectric.
`[0011]
`In order to improve read and program performance,
`multiple charge storage elements or memory transistors in an
`array are read or programmed in parallel. Thus, a "page" of
`memory elements are read or programmed together. In exist(cid:173)
`ing memory architectures, a row typically contains several
`interleaved pages or it may constitute one page. All memory
`elements of a page will be read or progrannned together.
`
`Errors in Written Data
`
`[0012]
`In the types of memory systems described herein, as
`well as in others, including magnetic disc storage systems, the
`integrity of the data being stored is maintained by use of an
`error correction technique. Most commonly, an error correc(cid:173)
`tion code (ECC) is calculated for each sector or other unit of
`data that is being stored at one time, and that ECC is stored
`along with the data. The ECC is most commonly stored
`together with a unit group of user data from which the ECC
`has been calculated. The unit group of user data may be a
`sector or a multi-sector page. When this data is read from the
`memory, the ECC is used to determine the integrity of the user
`data being read. Erroneous bits of data within the unit group
`of data can often be corrected by use of the ECC.
`[0013] The trend is to reduce the size of the memory sys(cid:173)
`tems in order to be able to put more memory cells in the
`system and to make the system as small as possible to fit in
`smaller host devices. Memory capacity is increased by a
`combination of higher integration of circuits and configuring
`each memory cell to store more bits of data. Both techniques
`require the memory to operate with increasing tighter margin
`of error. This in tum places more demand on the ECC to
`correct errors.
`[0014] The ECC can be designed to correct a predeter(cid:173)
`mined number of error bits. The more bits it has to correct, the
`more complex and computationally intensive will the ECC
`be. For quality assurance, conventional ECC is designed
`based on the expected worst-case cell error rate at the end of
`life of the memory device. Thus, they have to correct a maxi(cid:173)
`mum number of error bits up to the far tail end of a statistical
`population of error rate.
`[0015] As the flash memory ages, its error rate increases
`rapidly near the end of life of the device. Thus a powerful
`ECC designed for the worst-case will only be called to apply
`its full capacity at the end oflife of the memory device.
`[0016] Using ECC to correct a worst-case number of error
`bits will consume a great amount processing time. The more
`bits it has to correct, the more computational time is required.
`
`The memory performance will be degraded. Additional dedi(cid:173)
`cated hardware may be implemented to perform the ECC in a
`reasonable amount of time. Such dedicated hardware can take
`up a considerable amount of space on the controller ASIC
`chip. Moreover, for most of the life time of the device, the
`ECC is only marginally utilized, resulting in its large over(cid:173)
`heads being wasted and realizing no real benefits.
`[0017] Thus, there is a need to provide a nonvolatile
`memory of high storage capacity without the need for a
`resource-intensive ECC over designed for the worse-case.
`
`SUMMARY OF THE INVENTION
`
`Adaptively Rewrite Data from a Higher Density
`Memory Portion to a Lower Error Rate Memory Por(cid:173)
`tion to Control Error Rate
`
`[0018] According to a general aspect of the invention, a
`post-write-read error management is provided in that a flash
`memory having an array of memory cells is configured with a
`first portion and a second portion. The second portion stores
`data at higher density but operates with a smaller margin of
`errors compared to the first portion. Data is written to the
`second portion for efficient storage. Afterwards, the data is
`read back in a post-write read operation to check for excessive
`error bits. If the error bits exceeded a predetermined amount,
`the data is rewritten or kept at the less error-prone first portion.
`This places a limit on the maximum number of error bits
`arising from writing data to the memory. In a statistical dis(cid:173)
`tribution of error rates, the limit represents a limit on the
`number standard derivations of the distribution so that the far
`tail-end of the distribution (with higher error rates) can be
`ignored. This allows a smaller and more efficient error cor(cid:173)
`rection code ("ECC") to be designed for correcting a smaller
`number of errors bits, thereby improving the performance and
`reducing the cost of the memory.
`[0019]
`In one preferred embodiment, the first portion has
`each memory cell storing one bit of data and the second
`portion has each memory cell storing more than one bit of
`data.
`[0020]
`In an alternative embodiment, the first portion
`serves as a cache for incoming data, so a cache copy of the
`input data is progrannned into the cache. Then a first copy of
`data is programmed into the second portion. If the post-write
`read has not detected an excessive amount of error in the first
`copy, the first copy will be deemed valid and subsequent
`access will be directed to access the first copy. On the other
`hand, if the post-write read has detected an excessive amount
`of error in the first copy, the cached copy in the first portion
`will replace the first copy in the se