Reply Declaration of Dr. David Liu
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`Case No.: IPR2021-01547
`U.S. Patent No. 8,891,298
`Original Issue Date: November 18, 2014
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`REPLY DECLARATION OF DR. DAVID LIU
`
`1
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`Reply Declaration of Dr. David Liu
`
` TABLE OF CONTENTS
`
`I.
`II.
`
`B.
`
`C.
`
`Page
`INTRODUCTION .......................................................................................... 3
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS ............................................................... 3
`III. ASSIGNMENT AND MATERIALS CONSIDERED .................................. 4
`IV. UNDERSTANDING OF THE LAW ............................................................. 5
`V.
`LEVEL OF SKILL IN THE ART .................................................................. 5
`VI.
`THE 298 PATENT’S EFFECTIVE FILING DATE ..................................... 5
`VII. PATENT OWNER’S CONSTRUCTION OF “BLOCKS” AS BEING
`ONLY “PHYSICAL BLOCKS” IS INCONSISTENT WITH HOW A
`POSA WOULD HAVE UNDERSTOOD THE CLAIM TERM ................... 6
`VIII. MOSHAYEDI DISCLOSES AND RENDERS OBVIOUS THE
`“TRANSFERRING” LIMITATION .............................................................. 9
`A.
`Patent Owner Mischaracterizes Moshayedi, But Even Under
`This Incorrect Understanding, Moshayedi Discloses The
`Transferring Limitation ........................................................................ 9
`A POSA Would Not Have Understood The Transferring
`Limitation To Require The Transfer Of Contents In The
`Physical MLC Block Before Allocation Occurs ................................ 10
`Even Under Patent Owner’s Incorrect Interpretation Of The
`Transferring Limitation, Moshayedi Discloses The Transferring
`Limitation ........................................................................................... 12
`Even Under Patent Owner’s Incorrect Interpretation Of The
`Transferring Limitation, Moshayedi Renders Obvious The
`Transferring Limitation ...................................................................... 18
`SUTARDJA’S “SECOND SHOWING” RENDERS OBVIOUS
`“COUNTING” [1.F] AND “TRANSFERRING” [1.G] ............................... 21
`SUTARDJA’S “FIRST WAY” RENDERS OBVIOUS
`“COUNTING” [1.F] AND “TRANSFERRING” [1.G] ............................... 25
`XI. DECLARATION .......................................................................................... 32
`
`D.
`
`IX.
`
`X.
`
`2
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`Reply Declaration of Dr. David Liu
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`I, David Liu, declare as follows:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by Micron Technology, Inc. (“Micron”) as an
`
`independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”). I am not an employee of Micron or any affiliate
`
`or subsidiary of Micron.
`
`2.
`
`3.
`
`My opinions and the bases for my opinions are set forth below.
`
`I am being compensated at $550 per hour for my work, plus
`
`reimbursement for any reasonable expenses. My compensation is based solely on
`
`the amount of time that I devote to activity related to this case and is in no way
`
`contingent on the nature of my findings, the presentation of my findings in
`
`testimony, or the outcome of this or any other proceeding. I have no other
`
`financial interest in this proceeding.
`
`II.
`
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS
`
`4.
`
`My education, background, and professional qualifications are set
`
`forth in Paragraphs 5-14 of the previous declaration that was submitted in
`
`connection with this proceeding (which I understand has been designated as
`
`Exhibit 1009). My CV is included as Exhibit 1058.
`
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`III. ASSIGNMENT AND MATERIALS CONSIDERED
`
`Reply Declaration of Dr. David Liu
`
`5.
`
`I have been asked to provide some additional opinions and elaboration
`
`regarding the state of the art and what one of ordinary skill in the art would have
`
`known as of the effective filing date of the 298 patent.
`
`6.
`
`I reserve the right to amend and supplement this declaration in light of
`
`additional evidence, arguments, or testimony presented during this IPR or related
`
`proceedings on the 298 patent.
`
`7.
`
`In forming the opinions set forth in this declaration, I have considered
`
`and relied upon my education, knowledge of the relevant field, knowledge of
`
`scientific and engineering principles, and my experience. To the extent applicable
`
`to the opinions I render here, I have also reviewed and considered Patent Owner’s
`
`Response in this proceeding, the materials listed in my prior declaration (Exhibit
`
`1009), along with the following additional materials:
`
`Exhibit
`
`Description
`
`1059
`
`1061
`
`1062
`
`1064
`
`Deposition Transcript of Sunil Khatri (September 1, 2022)
`[IPR2021-01547, -01548 and -01549]
`
`U.S. Patent No. 8,130,554 (“Linnell”)
`
`U.S. Patent No. 7,917,709 (“Gorobets III”)
`
`Byung-Woo Nam, Gap-Joo Na, and Sang-Won Lee, “A Hybrid
`Flash Memory SSD Scheme for Enterprise Database
`Applications”
`
`4
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`
`Exhibit
`
`Description
`
`Reply Declaration of Dr. David Liu
`
`1065
`
`1066
`
`2014
`
`Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, “Improving
`Flash Wear-Leveling by Proactively Moving Static Data”
`
`Muthukumar Murugan, “Rejuvinator: A Static Wear Leveling
`Algorithm for NAND Flash Memory with Minimized Overhead”
`
`Declaration of Sunil Khatri in Support of Patent Owner’s
`Response in IPR 2021-01547
`
`
`IV. UNDERSTANDING OF THE LAW
`
`8.
`
`Paragraphs 19-34 of my prior declaration (Ex. 1009) included a
`
`section discussing my understanding of the law. I am not an attorney, but I have
`
`been instructed in and applied the law as described in my prior declaration.
`
`V. LEVEL OF SKILL IN THE ART
`
`9.
`
`Paragraphs 35-38 of my prior declaration (Ex. 1009) include my
`
`understanding of the level of skill in the art. I understand that Patent Owner
`
`adopted Petitioner’s definition of the level of skill in the art. I have applied the
`
`same definition of an ordinarily skilled artisan here.
`
`VI. THE 298 PATENT’S EFFECTIVE FILING DATE
`
`10. As in my prior declaration, my opinions in this declaration are formed
`
`from the perspective of a person of ordinary skill in the art as of July 19, 2011,
`
`including both the knowledge of a person or ordinary skill in the art at that time as
`
`well as how a person of ordinary skill in the art would understand the prior art.
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`Reply Declaration of Dr. David Liu
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`VII. PATENT OWNER’S CONSTRUCTION OF “BLOCKS” AS BEING
`ONLY “PHYSICAL BLOCKS” IS INCONSISTENT WITH HOW A
`POSA WOULD HAVE UNDERSTOOD THE CLAIM TERM
`
`11.
`
`I understand that Patent Owner has taken the position that the claim
`
`term “blocks” means only physical blocks and does not include logical blocks
`
`within its scope. POR, 23-24.
`
`12. As an initial matter, I disagree that, in the context of the 298 patent, a
`
`POSA would have understood the claim term “blocks” to refer only to physical
`
`blocks. Instead, the term would have been understood to include both logical and
`
`physical blocks.
`
`13.
`
`I begin by noting that the surrounding claim language confirms that
`
`the claim term “blocks” includes logical blocks within its scope. At a high level, a
`
`“block” in flash memory can exist in two forms: the physical form, which was
`
`known as a “physical block,” and the logical form, which was known as a “logical
`
`block.” Ex. 1009, ¶¶ 61-74. As I noted in my original declaration, an address
`
`map, namely, a logical-to-physical mapping, maps the logical blocks to physical
`
`blocks. Ex. 1009, ¶¶ 61-74.
`
`14. Claim 1 starts with “one MLC non-volatile memory module
`
`comprising a plurality of individually erasable blocks.” Claim 1 contains a similar
`
`limitation for SLC. Importantly, the claim then recites “maintain[ing] an address
`
`map of the MLC … non-volatile memory module[].” That map comprises: (1) “a
`
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`list of logical address ranges accessible by a computer system, the list of logical
`
`Reply Declaration of Dr. David Liu
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`address ranges having a minimum quanta of addresses,” and (2) “each entry in the
`
`list of logical address ranges maps to a similar range of physical addresses
`
`within … the at least one MLC non-volatile memory module.” Thus, a POSA
`
`would have understood this logical to physical mapping to disclose the mapping of
`
`logical blocks to physical blocks. Indeed, claim 2 specifies that “the minimum
`
`quanta of [logical] addresses is equal to one block,” which expressly incorporates
`
`this understanding. Thus, a POSA would have understood the claim term “block”
`
`to include both the physical and logical form, i.e., physical and logical blocks.
`
`15. Also, the claim language would be nonsensical if “block” only meant
`
`“physical block.” Claim 1 recites a process in which one must “allocate those
`
`blocks … to the at least one SLC non-volatile memory module.” If “block” was
`
`restricted to physical blocks, this limitation would make no sense because one
`
`cannot “allocate” physical blocks from one memory module to another. In the
`
`context of the 298 patent, which has an MLC module and a separate SLC module,
`
`allocating a physical block to a different module conjures up the notion of
`
`physically moving the MLC block to the different SLC module. Even if one could
`
`somehow do this (it is not possible), it would not remedy the problem that the 298
`
`patent is directed at solving (i.e., ensuring that hot blocks are not rendered
`
`unusable much faster than other blocks). Ex. 1001, 2:59-64. Even if one were able
`
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`to move a physical block in MLC to SLC, it would still be an MLC block with the
`
`Reply Declaration of Dr. David Liu
`
`same logical address and the same write count and thus would wear out in the same
`
`amount of time. Instead, allocating a block to SLC refers to allocating the logical
`
`block to SLC by reassigning the logical block address to a physical SLC block.
`
`16.
`
`I understand that Patent Owner has also contended that only physical
`
`blocks can be erased and, thus, the claim’s requirement that the MLC and SLC
`
`modules comprise “individually erasable blocks” must only be referring to
`
`physical blocks. This is incorrect. Logical blocks are individually erasable by the
`
`host. Moshayedi’s claims make this clear. Claim 1 includes a limitation which
`
`requires “creating a list of one or more metrics associated with the erasing [of] data
`
`blocks” and “rewriting the one or more logical blocks to a physical address of the
`
`non-volatile memory based on the one or more metrics.” Ex. 1012 (“Moshayedi”),
`
`claim 1. Claim 2 depends from claim 1 and requires that “the one or more metrics
`
`associated with erasing data blocks comprise an erase count of a logical block
`
`address (LBA).” This plainly discloses the erasure of logical blocks.
`
`17.
`
`I understand that Patent Owner’s expert, Dr. Khatri, has admitted that
`
`logical blocks can be erased. Ex. 1059, 168:19-169:8. I agree. It was well-known
`
`that logical blocks could be erased. Ex. 1061 (“Linnell”), 3:54-4:2 (“delet[ing]” a
`
`“logical block”), 6:63-7:8 (describing a “secure erase technique” that “supports
`
`erasure of logical data blocks in at least NAND flash based memory”). As Linnell
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`explains, when a host would erase a logical block, one technique was to mark the
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`Reply Declaration of Dr. David Liu
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`corresponding physical block invalid. Id., 7:9-19. As Linnell demonstrates, secure
`
`erasure techniques were known such that erasing a logical block would cause
`
`erasure of the physical block as well. Id., 7:48-67. Put another way, it was well
`
`known for the host to issue erase commands for the logical units, such as logical
`
`blocks, and then a corresponding operation to erase the physical unit occurs (either
`
`immediately, see above, or at some point “later”). Ex. 1062, 2:10-34 (“The host
`
`can issue a sector erase command to erase the logical sector in the memory in order
`
`to delete all the sector data.”). Thus, Patent Owner’s contention that it wasn’t
`
`possible to erase logical blocks is wholly false.
`
`VIII. MOSHAYEDI DISCLOSES AND RENDERS OBVIOUS THE
`“TRANSFERRING” LIMITATION
`
`A.
`
`Patent Owner Mischaracterizes Moshayedi, But Even Under This
`Incorrect Understanding, Moshayedi Discloses The Transferring
`Limitation
`
`18.
`
`I understand that Patent Owner has characterized Moshayedi’s “swap”
`
`as only writing a single block of data received with the write operation to SLC.
`
`POR, 57. As I explain below, this is incorrect because as part of the “swap,”
`
`Moshayedi also copies any valid data from the original MLC physical block and
`
`transfers it to the new physical SLC block. But even assuming Patent Owner were
`
`correct that Moshayedi’s “swap” only transfers the data from the write command
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`into SLC, in my opinion, this still satisfies the transferring claim limitation.
`
`Reply Declaration of Dr. David Liu
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`Moshayedi discloses that the flash drive “determines whether to store newly
`
`received data associated with a particular LBA in SLC flash or MLC flash,
`
`depending on the number of writes that have occurred for that particular LBA.”
`
`Moshayedi, [0024]; see also id., [0032]. When the host issues a write command,
`
`the host provides both the data (to be written) and a logical address (from the
`
`host’s perspective, the logical address to which the data is written). Moshayedi
`
`describes the “newly received data” as being “associated with a particular LBA”
`
`because after receiving the write command, from the host’s perspective, the newly
`
`received data is now addressable at that logical block address (LBA). In other
`
`words, from the host’s perspective, that data is now in that specific logical block.
`
`Accordingly, upon receiving a write operation with “new data,” that “data” is
`
`associated with the LBA and, therefore, is “the respective contents of those
`
`blocks.” By writing that data into SLC, the flash device “transfer[s] the respective
`
`contents of those blocks to the at least one SLC non-volatile memory module.”
`
`B. A POSA Would Not Have Understood The Transferring
`Limitation To Require The Transfer Of Contents In The Physical
`MLC Block Before Allocation Occurs
`
`19.
`
`I understand that Patent Owner has taken the position that limitation
`
`[1.G] (i.e., “allocate those blocks that receive the most frequent writes by
`
`transferring the respective contents of those blocks to the at least one SLC non-
`
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`volatile memory module”) should be understood to require that the transferred data
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`Reply Declaration of Dr. David Liu
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`be in the physical MLC block before the allocation occurs. POR, 59. I disagree
`
`that a POSA would have understood the transferring limitation in this way.
`
`20. First, PO’s interpretation assumes that “contents of those blocks”
`
`refers to physical blocks and not logical blocks. I explain why this is incorrect in
`
`Section VII above. Second, the only embodiment in the specification that
`
`discusses this transfer process refers to performing the transfer on “every 1000
`
`writes, or every 10,000 writes.” Ex. 1001, 6:24-35. While the specification does
`
`not expressly detail this process, the specification does say the “transfer” occurs in
`
`connection with a write operation and, therefore, a POSA would have understood
`
`that the “transfer” may be a transfer of the newly written data, i.e., the flash device
`
`may transfer incoming data associated with a write command (and does not have to
`
`be a transfer of the data existing in the physical block before allocation).
`
`Ex. 1001, 6:24-35. In fact, transferring incoming data to a new location in
`
`connection with write operations was known in the art (see my opening
`
`declaration, Ex. 1009, ¶ 71), further supporting that a POSA would have
`
`understood the specification’s reference to the transfer occurring “every 1000
`
`writes, or every 10,000 writes” to indicate that the transfer may of the new data in
`
`connection with a write command.
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`Reply Declaration of Dr. David Liu
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`C.
`
`Even Under Patent Owner’s Incorrect Interpretation Of The
`Transferring Limitation, Moshayedi Discloses The Transferring
`Limitation
`
`21. As an initial matter, Moshayedi discloses counting accesses to both
`
`physical and logical blocks. For example, Moshayedi discloses tracking the write
`
`count of a logical block, noting that the flash drive “keeps track of the number of
`
`times that data for each logical block address (LBA) [i.e., logical block] has been
`
`written to the flash memory.” Moshayedi, [0024]. Moshayedi further discloses
`
`tracking the “erase count” of “a block in MLC flash.” Moshayedi, [0032]. In
`
`independent claim 1, Moshayedi refers to using this erase count (“metrics
`
`associated with the erasing data blocks”). In dependent claim 2, Moshayedi
`
`specifies the erase count is of a logical block, meaning that the erase count of
`
`independent claim 1 could be physical or logical (since claim 2 narrows claim 1).
`
`A POSA would have understood both logical and physical blocks to be erasable.
`
`See Section VII.
`
`22. As I discuss in my opening declaration, Moshayedi describes
`
`performing a “swap” when the write or erase count is above a threshold.
`
`Ex. 1009, ¶¶ 220-224.
`
`23.
`
`I understand that Patent Owner has taken the position that
`
`Moshayedi’s “swap” only discloses redirecting an incoming write (i.e., new data)
`
`to SLC. POR, 57-58. I disagree that a POSA would have understood Moshayedi
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`Reply Declaration of Dr. David Liu
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`to only be disclosing the redirection of a write without any transfer of data from the
`
`physical MLC block to the physical SLC block. Moshayedi discloses both the
`
`redirection of an incoming write operation (i.e., “new data”) to MLC and the
`
`transfer of data that is already in MLC (i.e., “existing data”) to SLC as part of its
`
`“swap” process. In addition to the redirection, Moshayedi also “move[s]” (i.e.,
`
`“transfer[s]”) other segments of data in the physical MLC block to the physical
`
`SLC block. Moshayedi, [0024], [0032].
`
`24. As I noted in my previous declaration, flash memory is organized into
`
`different units, such as “blocks,” “pages,” and/or “sectors.” Ex. 1009, ¶ 52. A
`
`block is the smallest erasable unit and, thus, an erase operation must occur on the
`
`entire block. Id. A page is the smallest writable unit and a block is made up of
`
`multiple pages. Id.; Ex. 1019, 3. When writing to a single page, the valid data in
`
`the other pages in the block (or lack of any data in those pages) is not altered.
`
`Thus, when writing to a page, existing data in the other pages does not change.
`
`25.
`
`I likewise described in my previous declaration the well-known
`
`process of wear-leveling and the benefits associated therewith. Ex. 1009, ¶¶ 71-74.
`
`“Dynamic wear leveling” is a process wherein the flash device “remaps” (i.e.,
`
`updates the logical to physical mapping for) incoming data to a block with lower
`
`wear. Ex. 1009, ¶ 71. Thus, rather than writing to a physical block with a high
`
`wear level, the incoming write may be remapped to an already-erased block with a
`
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`Reply Declaration of Dr. David Liu
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`lower wear level. Id. Through this method, a flash device can select blocks with
`
`relatively low wear for incoming writes. Id., ¶ 72. It was known that these
`
`“redirections” could occur between MLC and SLC.
`
`26. Wear leveling techniques rely on the availability of free sectors that
`
`can be filled up with new data. Ex. 1019, 41. Since data may be written in pages,
`
`but can only be erased in blocks, it was important to ensure that all data in an old
`
`block was moved to another location prior to erasure to prevent the erasure of valid
`
`data. Id.; Ex. 1064, 1 (“However, when updating a page in the block, all valid
`
`pages of the corresponding block must be copied to the free block.”), 4 (describing
`
`a “block merge” process wherein “valid pages in [an] original data block” may be
`
`transferred to a new block so that the original data block may be erased); Ex. 1065,
`
`5 (“before a block is erased, data of any valid pages in the block must be copied to
`
`other free pages”); Ex. 1066, 2-3 (describing “cop[ying]” “valid pages” to a new
`
`block before reclaiming a block); Ex. 1046, 7:54-66 (describing the remapping and
`
`moving of data to a new block so that the old block can be “reclaimed”). To
`
`invalidate a memory block, the controller selects a free memory block, moves the
`
`data to that free memory block, and marks the original block as invalid. Ex. 1064,
`
`1 (“However, when updating a page in the block, all valid pages of the
`
`corresponding block must be copied to a free block.”), 4 (describing a “block
`
`merge” process wherein “valid pages in [an] original data block” may be
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`transferred to a new block so that the original data block may be erased); Ex. 1065,
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`Reply Declaration of Dr. David Liu
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`5 (“before a block is erased, data of any valid pages in the block must be copied to
`
`other free pages”); Ex. 1066, 2-3 (describing “cop[ying]” “valid pages” to a new
`
`block before reclaiming a block); Ex. 1046, 7:54-66 (describing the remapping and
`
`moving of data to a new block so that the old block can be “reclaimed”). In a
`
`similar process known as “garbage collection,” blocks containing invalid sectors
`
`would be selected and the portions of those blocks that contain valid sectors would
`
`be copied into free sectors of other blocks. Ex. 1019, 42; Ex. 1046, 7:65-8:8.
`
`After this, the whole block would be erased. Ex. 1019, 42. Garbage collection is
`
`typically performed as a background operation but can be performed during write
`
`operations. Id. Either process requires valid data to be moved prior to erasure.
`
`27. Moshayedi incorporates each of these well-known techniques (i.e.,
`
`wear leveling and garbage collection) as part of the “swap.” Moshayedi’s “swap”
`
`involves two separate subprocesses: (1) the redirection of an incoming write from
`
`MLC to SLC if the block is above a write or erase threshold, and (2) the
`
`transferring or copying of existing valid data in MLC to SLC. Moshayedi, [0024],
`
`[0032].
`
`28. Moshayedi’s “swap” method begins with an incoming write operation
`
`for a page of data and an associated logical block address (“LBA”) that is directed
`
`to a free page in a block of MLC. Moshayedi, [0047]. Moshayedi refers to this
`
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`MLC block as the “selected block.” Id. at [0047]-[0048]. The flash device receives
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`Reply Declaration of Dr. David Liu
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`the write command and interprets the physical location of the data based on its
`
`V2P table (i.e., an address map). Id. at [0047]; Ex. 1009, ¶¶ 61-74. Then, the
`
`device checks the “redundancy” area (i.e., spare area) of the block to discern its
`
`erase count. Id. If the erase count is over a threshold, the “swap” process is
`
`initiated wherein the data will be “swapped” from MLC to SLC. Id.
`
`29. Upon initiating the “swap” process, a “free block” is selected in SLC
`
`based on the V2P table. Moshayedi, [0048]. After selecting the free block in SLC,
`
`the buffered data from the incoming write may be copied into a free page of that
`
`“free block.” Id. Then, the data in the other pages of the “selected block” (i.e., the
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`physical block for which the write was originally intended) in MLC is transferred
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`over to the other free pages in the “free block” in SLC. Id. One way in which this
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`could be done is by appending the existing valid pages in the MLC block with the
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`new pages of data in the buffer and subsequently writing or transferring the content
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`of the buffer into the free block. Finally, the “selected block” in MLC may be
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`marked invalid and erased through a garbage collection process. Id. Then, the
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`“selected block” may be “reclaimed” as a free block and added to a free block list
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`in the V2P RAM. Id.; see ¶ 26, supra; Ex. 1064, 1, 4; Ex. 1065, 5; Ex. 1066, 3;
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`Ex. 1046, 7:54-66.
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`Reply Declaration of Dr. David Liu
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`30. Thus, Patent Owner misunderstands Moshayedi when it asserts that
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`the “swap” is only the redirection of an incoming write to SLC. This detailed
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`swapping process is further described in other portions of Moshayedi, such as
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`paragraph [0049] where Moshayedi says: “[w]hen the erase count of the block at
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`MLC area is 500, next written data ca[n] require the data to move to SLC area
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`which erase count is less than 500.” Moshayedi, [0049]. Based on my discussion
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`above, a POSA would have understood this “move” process to describe the transfer
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`(i.e., “moving”) of existing data from MLC to SLC. See ¶ 29, supra. In fact, after
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`the data is copied to SLC, the MLC block can then be erased and “reclaimed” as a
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`free block to which data can subsequently be written. Moshayedi, [0049]. A
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`POSA would have understood that it was necessary to copy all of the valid data
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`from MLC to SLC in order to allow for the MLC block to be erased and
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`subsequently reclaimed as a free block. See ¶ 26, supra; Ex. 1064, 1, 4; Ex. 1065,
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`5; Ex. 1066, 2-3; Ex. 1046, 7:54-66.
`
`31. Moshayedi confirms the understanding that both new data and
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`existing data are moved to SLC by noting that, upon selecting a new block for the
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`“swap,” “[t]he original data plus changed data is copied to the new target block.”
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`Moshayedi, [0059]. This “original data” is the data existing in MLC and the “new
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`data” is the data associated with the incoming write. Id. Detailing this process,
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`Moshayedi states that both “the data from the buffer” and “the rest of the data of
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`the selected block [i.e., MLC]” are copied to the “free block” in SLC. Id., [0048].
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`Reply Declaration of Dr. David Liu
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`Upon transferring all the data, the “selected block” in MLC may be marked invalid
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`and erased. Ex. 1066, 2-3; Ex. 1046, 7:54-66; Ex. 1065, 5.
`
`32. Moshayedi further confirms this understanding by noting that “[i]t is
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`not possible to operate the SLC at one logical block size and the MLC at a
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`different logical block size. The reason for this is that it would make it extremely
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`difficult to copy data between the two and keep track of the data if the block sizes
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`were different. Moshayedi, [0068]. Moshayedi is referring to the need to keep the
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`pages of the block together and, when necessary, copy all the block pages from
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`MLC to SLC to move the entire block to SLC.
`
`D. Even Under Patent Owner’s Incorrect Interpretation Of The
`Transferring Limitation, Moshayedi Renders Obvious The
`Transferring Limitation
`
`33.
`
`I also opined that Moshayedi renders the transferring limitation
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`obvious because it would have been obvious to perform the “swap” as a
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`background operation (during idle time) with no connection to a host operation.
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`Ex. 1009, ¶ 225. For example, executing the process as a background operation in
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`connection with garbage collection (which also brings performance benefits when
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`executed as a background operation) would allow the firmware to move data to
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`SLC and free up blocks in MLC for future write commands, which leads to a more
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`efficient write process. Ex. 1044, [0163]; Ex. 1019, 42 (“In order to minimize the
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`impact on performance, garbage collection can be performed in [the]
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`Reply Declaration of Dr. David Liu
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`background.”). I understand that Patent Owner’s expert, Dr. Khatri, has stated that
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`such background operations save time and resources. Ex. 1059, 195:16-196:18. I
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`agree with Dr. Khatri.
`
`34. By way of another example, performing the “swap” during idle time
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`would improve system performance because it would obviate the need to perform
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`the “swap” in connection with a write operation. Ex. 1009, ¶ 227. By performing
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`this as a background operation, those logical or physical blocks with high
`
`frequencies of writes would have their logical addresses “remapped” to SLC and,
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`subsequently, all data in those MLC blocks would be transferred to SLC. Thus,
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`there would be no need to perform the write redirection, because the logical
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`address associated with the frequently written MLC block would have already been
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`remapped to SLC in the background. The incoming write would not need to be
`
`redirected because, if the write was going to a high frequency block, it would
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`already be mapped to SLC. This would obviate, for example, the step of checking
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`the erase or write count of the target block of the write command to determine
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`whether remapping to SLC was necessary, thereby improving the write operation
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`speed.
`
`35.
`
`I understand that Patent Owner has also argued that Moshayedi
`
`teaches away from MLC-to-SLC background operations because Moshayedi
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`discloses that they are unnecessary. POR, 62. I disagree. Moshayedi is only
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`Reply Declaration of Dr. David Liu
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`saying that background operations for MLC to SLC are not necessary if his system
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`is employing write redirection. Specifically, Moshayedi notes: “[1] As the level of
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`user blocks within the SLC goes above the configured limit, the logical blocks with
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`the lowest write count are moved from SLC to MLC, therefore freeing up space in
`
`the SLC. [2] No converse operation is necessary (copy from MLC to SLC) as
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`logical blocks are directed towards SLC when they are written by the host if the
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`write count is at a sufficient level to warrant this.” Moshayedi, [0073]. Here,
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`Moshayedi is disclosing in ([1]) that if too many blocks are mapped to SLC, it may
`
`be necessary to remap some of these SLC blocks to MLC (and transfer the block
`
`content to MLC). Moshayedi is disclosing in ([2]) that the opposite should not
`
`happen, i.e., too many blocks are mapped to MLC, because the write redirection
`
`should be sufficient to steer and copy enough MLC blocks to SLC. Thus, a POSA
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`would have understood that Moshayedi is disclosing that one option to ensure that
`
`there are not too many blocks in MLC is to use write redirection. Id. However,
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`this also tells a POSA that another alternative is to use the “swap” as a background
`
`operation (like he does for SLC to MLC) and not perform any write redirection.
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`Id. By transferring frequently written data as a background operation, one would
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`no longer need to perform write redirections because the frequently written logical
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`blocks would already be in SLC.
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`Reply Declaration of Dr. David Liu
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`IX.
`
`SUTARDJA’S “SECOND SHOWING” RENDERS OBVIOUS
`“COUNTING” [1.F] AND “TRANSFERRING” [1.G]
`
`36.
`
`I understand that Patent Owner argues that Sutardja does not disclose
`
`counting accesses to blocks. POR, 32-36. I disagree. In my original declaration, I
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`noted that Sutardja discloses receiving the “actual write frequencies for logical
`
`addresses where data is to be written from the host.” Ex. 1009, ¶ 151 (citing Ex.
`
`1011, “Sutardja,” [0147]); Sutardja, [0146]-[0147]. A POSA would have
`
`understood that counting writes to logical addresses is the counting accesses to
`
`blocks. As I described above, a POSA would have understood the claim term
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`“block” to include logical blocks within its scope. See Section VII, supra. As I
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`noted in my original declaration, logical addresses are those that are used by the
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`higher-level system to write data to physical addresses in memory. Ex. 1009, ¶ 62.
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`An LBA (“logical block address”), which a host uses to write data, is a “block” of
`
`logical addresses that