Advanced
`Semiconductor
`AY(CNNWC
`
` ASHOK K. SHARMA
`
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`

`ADVANCED
`SEMICONDUCTOR
`MEMORIES
`
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`IEEE Press
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`BOOKS OF RELATED INTEREST FROM IEEE PRESS
`
`SEMICONDUCTOR MEMORIES: Technology, Testing, and Reliability
`Ashok K. Sharma
`1997 Hardcover 480 pp
`
`ISBN 0-7803-1000-4
`
`NONVOLATILE SEMICONDUCTOR MEMORY TECHNOLOGY
`William Brown and Joe E. Brewer
`1998 Hardcover 616pp
`ISBN 0-7803-1173-6
`
`ADVANCED THEORY OF SEMICONDUCTOR DEVICES
`Karl Hess
`2000 Hardcover 352pp
`
`ISBN 0-7803-3479-5
`
`Micron Ex. 1047, p. 3
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`

`

`u
`
`I
`Architectures, Designs,
`and Applications
`
`ASHOK K. SHARMA
`
`IEEE
`PRESS
`
`ffiWILEY(cid:173)
`\VINTERSCIENCE
`A JOHN WILEY & SONS, INC., PUBLICATION
`
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`

`

`This book is printed on acid-free paper. 6)
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`Copyright © 2003 The Institute of Electrical and Electronics Engineers. All rights reserved.
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`
`Sharma, Ashok K.,
`Advanced semiconductor memories: Architectures, designs, and applications/
`Ashok K Sharma
`p. cm.
`Includes bibliographical references and index.
`ISBN 0-470-528-370 (cloth: alk. paper)
`
`Reprinted in 2009. For sale in Taiwan only.
`
`10 9 8 7 6 5 4 3 2
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`

`

`CONTENTS
`
`PREFACE
`
`1
`
`INTRODUCTION TO ADVANCED SEMICONDUCTOR
`MEMORIES
`
`1.1. Semiconductor Memories Overview / 1
`1.2. Advanced Semiconductor Memory Developments / 8
`1.3. Future Memory Directions / 16
`References / 18
`
`xix
`
`1
`
`2
`
`STATIC RANDOM ACCESS MEMORY TECHNOLOGIES
`
`19
`
`2.1. Basic SRAM Architecture and Cell Structures / 19
`
`2.1.1. SRAM Performance and Timing Specifications / 21
`2.1.2. SRAM Read/Write Operations / 23
`2.2. SRAM Selection Considerations / 26
`2.3. High Performance SRAMs / 33
`2.3.l. Synchronous SRAMs Flow-Through / 41
`2.3.2. Zero Bus Turnaround SRAMs / 43
`2.3.3. Quad Data Rate SRAM / 44
`2.3.4. Double Data Rate SRAM / 50
`2.3.5. No-Turnaround Random Access Memory / 51
`2.4. Advanced SRAM Architectures / 55
`2.5. Low-Voltage SRAMs / 61
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`CONTENTS
`
`2.6. BiCMOS Technology SRAMs / 75
`2.7. SOI SRAMs / 79
`2.8. Specialty SRAMs / 91
`2.8.l. Multiport RAMs / 92
`2.8.1.1. Dual-Port RAMs I 92
`2.8.1.2. QuadportTM RAMs / 101
`2.8.2. First-In-First-Out (FIFO) Memories / 103
`2.8.3. Content Addressable Memories (CAMs) / 111
`2.8.3.1. Advanced Content Addressable Memories
`(Examples) / 116
`
`References / 122
`
`3 HIGH-PERFORMANCE DYNAMIC RANDOM ACCESS
`MEMORIES
`
`129
`
`3.1. DRAM Technology Evolution and Trends / 129
`3.2. DRAM Timing Specifications and Operations / 133
`3.2.1. General Timing Specifications / 133
`3.2.2. Memory Read Operation / 135
`3.2.3. Memory Write Operation / 138
`3.2.4. Read-Modify-Write Operation / 140
`3.2.5. DRAM Refresh Operation / 141
`3.3. Extended-Data-Out DRAMS / 145
`3.3.1. EDO DRAM (Example) / 145
`3.4. Enhanced DRAM (EDRAM) / 146
`3.5. Synchronous DRAM/GRAM Architectures / 150
`3.5.1. SOR SDRAM/SGRAM / 150
`3.5.2. DOR SDRAM/SGRAM Features / 151
`3.5.3. Synchronous DRAM 256 Mb (Example) / 154
`3.5.3.1.
`Initialization / 154
`3.5.3.2. Register Definition / 155
`3.5.3.3. Commands / 157
`3.5.3.4. SDRAM Operations / 159
`3.6. Enhanced Synchronous DRAM (ESDRAM) / 163
`3.7. Cache DRAM (CDRAM) / 166
`3.8. Virtual Channel Memory (VCM) DRAMs / 172
`3.9. Advaned DRAM Technology Perspectives / 175
`3.9.1. Memory Capacitor Cell Improvements / 179
`3.9.2. 64-Mb DRAMs / 188
`3.9.3. 256-Mb DRAMs / 195
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`CONTENTS
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`Vii
`
`3.10. Gigabit DRAM Scaling Issues and Architectures / 200
`3.11. Multilevel Storage DRAMs / 217
`3.12. SOT DRAMs / 221
`References / 231
`
`4 APPLICATION-SPECIFIC DRAM ARCHITECTURES
`AND DESIGNS
`
`237
`
`4.1. Video RAMs (VRAMs) / 241
`4.2. Synchronous Graphic RAMs (SGRAMs) / 244
`4.2.1. 64-Mb DDR SGRAM / 246
`4.2.2. 256-Mb DDR Fast Cycle RAM / 253
`4.3. Rambus Technology Overview / 257
`4.3.1. Direct RDRAM Technologies and Architectures / 264
`4.3.2. Direct Rambus Memory System-Based Designs / 272
`4.4. Synchronous Link DRAMs (SLDRAMs) / 275
`4.4.1. SLDRAM Standard / 277
`4.4.2. SLDRAM Architectural and Functional Overview / 283
`4.4.3. SLDRAM (Example) / 285
`4.5. 3-0 RAM / 296
`4.5.1. Pixel ALU Operations / 305
`4.6. Memory System Design Considerations / 309
`References / 316
`
`5 ADVANCED NONVOLATILE MEMORY DESIGNS
`AND TECHNOLOGIES
`
`319
`
`5.1. Nonvolatile Memory Advances / 319
`5.1.1.
`Introduction / 319
`5.1.2. Serial EEPROMs / 323
`5.1.3. Flash Memory Developments / 327
`5.2. Floating Gate Cell Theory and Operations / 334
`5.2.1. Floating Gate Cell Theory / 334
`5.2.2. Charge Transport Mechanisms / 339
`5.2.2.1. Fowler-Nordheim Tunneling / 340
`5.2.2.2. Po1yoxide Conduction / 342
`5.2.2.3. Channel Hot-Electron Injection (CHET) / 343
`5.2.2.4. Direct Band-to-Band Tunneling / 347
`5.3. Nonvolatile Memory Cell and Array Designs / 350
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`viii
`
`CONTENTS
`
`5.3.l. UV-EPROM (or EPROM) Cells / 350
`5.3.1.1. T-Cell EPROM / 351
`5.3.1.2. X-Cell EPROM / 351
`5.3.1.3. Staggered Virtual Ground (SVG) Cell Array
`EPROM / 352
`5.3.1.4. Alternate Metal Virtual Ground (AMG)
`Cell Array EPROM / 353
`5.3.2. EEPROM Cells / 354
`5.3.3. Flash Memory Cells / 354
`5.3.3.1. T-Cell Flash I 355
`5.3.3.2. Alternate Metal Ground (AMG)
`Flash Cell / 357
`5.3.3.3. Source-Coupled Split-Gate (SCSG) Flash
`Cell / 358
`5.3.3.4. Field-Enhancing Tunneling Injector Flash
`Cell / 359
`5.3.3.5. Triple-Polysilicon Virtual Ground (TPVG)
`Flash Cell / 362
`5.3.3.6. Divided Bit-Line NOR (DINOR) Flash
`Cell / 363
`5.3.3.7. AND Flash Cell / 365
`5.3.3.8. High Capacitive Coupling Ratio (HiCr) Flash
`Cell I 366
`5.3.3.9. NANO Flash Cell / 366
`5.3.4. Flash Memory Cell Basic Operation and Processes / 368
`5.3.5. Flash EEPROM Technology Developments / 372
`5.4. Flash Memory Architectures / 377
`5.4.1. NOR Flash Memories / 378
`5.4.1.1. AMD NOR Architecture Flash Memories / 381
`5.4.1.2.
`Intel Flash Memories / 387
`5.4.2. NANO Flash Memories / 392
`5.4.2.1. AMO NAND Architecture Flash Memories / 393
`5.4.2.2. Samsung 32M x 8-bit NANO Architecture
`Flash Memory I 397
`5.4.2.3. Virtual DRAM I 401
`5.4.3. DINOR Architecture Flash Memories / 403
`5.4.3.1. A 16-Mb DINOR Flash Memory / 405
`5.4.3.2. P-Chanriel DJNOR Flash Memory / 406
`5.4.3.3. BiNOR Cell Flash Memory / 408
`5.4.4. AND Architecture Flash Memories / 410
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`CONTENTS
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`ix
`
`5.4.5. Specialty Flash Memories / 411
`5.5. Multilevel Nonvolatile Memories / 412
`5.5.1. Multilevel NOR Flash Memories / 418
`5.5.2. Multilevel NAND Flash Memories / 426
`5.5.2.1. A 512-Mb NAND Flash Memory I 429
`5.5.3. Multilevel AND Flash Memories / 429
`5.6. Flash Memory Reliability Issues / 430
`5.6.1. General Failure Mechanisms for
`EPROMs/EEPROMs / 430
`5.6.1.l. Stuck Bit / 434
`5.6.1.2. Data Retention Degradation / 434
`5.6.1.3. Read Time Degradation / 434
`5.6.1.4. Erase Time Degradation I 434
`5.6.1.5. Program Time Degradation j 434
`5.6.1.6. Disturbs / 434
`5.6.2. Flash Memory Reliability / 435
`5.6.2.1. Flash Overerase / 436
`5.6.2.2. Flash Program Disturbs / 436
`5.6.2.3. Flash Read Disturbs / 437
`5.6.2.4. Flash Program/Erase Endurance I 437
`5.6.2.5. Flash Data Retention Failures / 439
`5.6.2.6. Flash Hot Carrier Reliability Effects / 441
`5.6.2.7. Multilevel Flash Reliability / 442
`5.7. Ferroelectric Memories / 443
`5.7.1. Technology Overview / 443
`5.7.2. Ferroelectric Materials and Memory Design / 451
`5.7.3. Megabit FRAMs / 454
`5.7.4. Chain FRAM (CFRAM) / 463
`5.7.5. Metal Ferroelectric Semiconductor FET / 465
`5.7.6. FRAM Reliability Issues / 467
`References / 469
`
`6 EMBEDDED MEMORIES DESIGNS AND APPLICATIONS
`
`479
`
`6.1. Embedded Memory Developments / 479
`6.2. Cache Memory Designs / 487
`6.2.1. Cache Architecture Implementation for a DSP
`(Example) / 495
`6.3. Embedded SRAM/DRAM Designs / 499
`6.3.1. Embedded SRAM Macros / 503
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`X
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`CONTENTS
`
`6.3.1.1. A lT SRAM Macro / 504
`6.3.1.2. A 4T SRAM Macro I 506
`6.3.2. Embedded DRAM Macros / 508
`6.3.2.1. dRAMASICs / 508
`6.3.2.2. A Compiled 100-MHz DRAM Macro / 509
`6.3.2.3. A Dual-Port Interleaved DRAM Architecture
`Macro / 511
`6.3.2.4. A 1-GHz Synchronous DRAM Macro / 513
`6.4. Merged Processor DRAM Architectures / 516
`6.5. DRAM Processes with Embedded Logic Architectures / 522
`6.5.1. A Modular Embedded DRAM Core / 523
`6.5.2. Multimedia Accelerator with Embedded DRAM / 524
`Intelligent RAM (IRAM) / 527
`6.5.3.
`6.5.4. Computational RAM / 530
`6.6. Embedded EEPROM and Flash Memories / 533
`6.7. Memory Cards and MultiMedia Applications / 536
`6. 7.1. Memory Cards / 536
`6. 7.2. Single-Chip Flash Disk / 544
`References / 547
`
`7
`
`FUTURE MEMORY DIRECTIONS: MEGABYTES TO
`TERA BYTES
`
`549
`
`7.1. Future Memory Developments / 549
`7.2. Magnetoresistive Random Access Memories (MRAMs) / 551
`7.2.1. MRAM Technology Developments and Tradeoffs / 551
`7.2.2. MRAM Cells and Architectures / 556
`7.2.3. 256K/1-Mb GM RAMs / 566
`7.2.4. Multilevel MRAMs / 571
`7.3. Resonant Tunneling Diode-Based Memories / 572
`7.3.1. Resonant Tuneling Diode Theory / 572
`7.3.2. Tunneling SRAM (TSRAM) Cell Designs / 574
`7.3.3. RTD-Based Memory System (Example) / 579
`7.4. Single-Electron Memories / 582
`7.4.1. Single-Electron Device Theory / 582
`7.4.2. Single-Electron Memory Characteristics and
`Configurations / 590
`7.4.3. Single-Electron Devices Fabrication Techniques / 595
`7.4.4. Nanocrystal Memory Devices / 596
`7.5. Phase-Change Nonvolatile Memories / 602
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`CONTENTS
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`Xi
`
`7.6. Protonic Nonvolatile Memories / 607
`7.7. Miscellaneous Memory Technology Development
`(Examples) / 612
`7.7.1. Thyristor-Based SRAM Cell (T-RAM) / 613
`7.7.2. Content Addressable Read-Only Memory (CAROM) / 614
`7.7.3. Nanotech Memories / 618
`7.7.4. Solid-State Holographic Memories / 618
`References / 623
`
`INDEX
`
`631
`
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`CHAPTER 6
`
`EMBEDDED MEMORIES DESIGNS
`AND APPLICATIONS
`
`6.1. EMBEDDED MEMORY DEVELOPMENTS
`
`The memory technology for embedded memories has a wide variation, ranging
`from small blocks of RO Ms, hundred of kilobytes of cache RAMs, high density
`(several megabits) of DRAMs, and small to medium density nonvolatile
`memory blocks of EEPROMs and flash memories. For memories embedded in
`the logic process, the most important figure of merit is the compatibility to
`logic process. In general, embedded ROM used for microcode storage has the
`highest compatibility to the logic process; however, its application is rather
`limited. Programmable logic array (PLA) or ROM-based logic is well used, but
`it is considered a special case of embedded ROM [1].
`Embedded SRAMs is one of the most frequently used memory embedded in
`logic chips, and typical applications include on-chip buffers, caches, register
`files, and so on. The standard six-transistor (6T) SRAM cell is also fairly
`compatible to a logic process, unless there are special structures involved. The
`bit density is not very high. Polysilicon resistor load ( 4T) cells provide higher
`bit density, but at the cost of process complexity associated with additional
`polysilicon-layer resistors. Embedded DRAM (eDRAM) that provides high
`density features is also becoming quite popular in combination with RISC
`processor and other peripheral circuitry in system-on-chip (SOC) types of
`applications for graphic accelerators and multimedia chips. Embedded EP(cid:173)
`ROM, EEPROM, and flash memory technologies require two to three or more
`additional masking steps to the standard logic process. These are finding
`applications in microcontrollers, field programmable gate arrays (FPGAs), and
`complex programmable logic devices (CPLDs).
`
`479
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`480
`
`EMBEDDED MEMORIES DESIGNS AND APPLICATIONS
`
`In a typical logic VLSI design, the on-chip memory integrated with other
`circuitry may include anything from simple registers to caches of several
`megabit sizes. In special applications such as the microprocessors, memory can
`occupy more than 50% of the chip area. A processor in search of data or
`instructions looks first in the first-level (Ll) cache memory, which is closest to
`the processor, and if the information is not found there, the request is passed
`on to the second-level cache (L2). The integration of on-chip Ll improves both
`the processor performance and bandwidth. The SRAM cells used in the Ll
`cache are usually larger than the ones for commodity SRAMs and for highest
`performance, fabricated with the same process as for the processor logic. Thus,
`an Ll cache tends to be faster than the L2 and L3 (the off-chip caches) and
`often utilizes special SRAM processes that minimize cell area.
`The major goal of cache memory design is to minimize the miss rate- that
`is, the possibility that immediately needed bits of information are not available
`in the nearest level of cache memory and have to be fetched from the higher
`levels of caches or even the main memory. As the processor performance has
`increased, the wait time in idle memory cycles has also increased, which has
`led to the so-called memory-processor performance gap, as illustrated in Figure
`6.1. Therefore, the ability to integrate large memory close to the processor
`(possibly, on-chip) helps remove some of the constraints of a slow memory
`access, allowing increase of more conventional pin-limited bus widths of
`16--256 bits, or even as high as 1024 bits [2].
`Another trend that drives the integration of DRAMs into logic chips is the
`memory granularity, which refers to the smallest increment by which a memory
`size may be increased. For applications that require less than 2 Mb of memory,
`an embedded SRAM would probably be more cost effective and should be
`considered first. In the 0.18-µm process generation, it is expected that the
`embedded DRAM solution would become cost effective at above approximate-
`
`g 1,000 .
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`performance gap \
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`
`1980
`
`1985
`
`1990
`
`1995
`
`2000
`
`Illustration of performance levels of processor versus DRAM, over several
`Figure 6.1
`generations [2].
`
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`EMBEDDED MEMORY DEVELOPMENTS
`
`481
`
`ly 2-Mb density. The embedding of DRAM not only reduces power by
`eliminating the need for off-chip drivers, but also allows for more active power
`management systems.
`In a DRAM manufacturing process, tight lithography and structural inno(cid:173)
`vations are combined to fabricate very dense cell arrays, and focus is on the
`minimization of cell area. Cell structure innovations include buried trench
`capacitor or stacked capacitor structure. Furthermore, in DRAM technologies,
`low leakage current levels are crucial, because the goal is to minimize the loss
`of stored charge (increase its retention time), including the transistor off(cid:173)
`current as well as the junction leakage. Typically, the low off-current levels are
`attained by using relatively high threshold voltages and longer channel lengths.
`In fact, unlike in logic process, channel lengths are significantly longer than the
`minimum dimension (e.g., in a 0.25-pm process, the designed gate lengths may
`be as long as 0.35-0.40 pm). Therefore, when the longer channels are combined
`with the rather high threshold voltages, the device on-currents are low as
`compared to those for the devices fabricated on a same generation standard
`logic process.
`In comparison to DRAM process, logic technologies use gate-level mini(cid:173)
`mum dimensions to drive short channel lengths to optimize the circuit timing
`and minimize the timing skew from channel length variations. The DRAM
`processes prefer a single work-function gate material (usually 11-type) for
`submicron technologies, so that the p-channel FET operates as a buried(cid:173)
`channel device. The gate of a buried pFET device is more loosely coupled to
`the channel it controls, and the performance is poorer as compared to the
`surface-channel device. The logic technology process runs dual-function gates:
`n-poly gates for the 11FETs and p-poly gates for the pFETs to get highest
`performance at the cost of complexity.
`In a given DRAM technology, the devices have thicker gate dielectric than
`would be consistent with a constant field scaling. For example, a 0.25-µm
`DRAM process would typically have about 8-nm gate oxide, whereas 0.25-µm
`logic process typically uses a 5-nm gate oxide to ensure maximum performance
`at 2.5 V. In a DRAM process, to minimize cost, all devices (and not just the
`transfer gates that are stressed with the boosted gate voltage) are fabricated
`with the thicker gate oxide, even though it provides suboptimal performance.
`The logic circuits often have self-aligned silicides (called salicides, in contrast
`to the polycide process) in which the gate and diffusion area are silicided
`simultaneously. However, in DRAM technology, the silicided diffusions are
`avoided because they can increase the junction leakage, even though the gate
`conductor usually has a silicide that is put on before the gate is defined.
`The density of a DRAM chip is mostly dependent on the cell size or array
`density, and it supports circuits that rarely push density limits and are less
`strictly controlled. Thus, the performance compromises made by commodity
`DRAM processes to reduce cost and increase yield result in a significant gap
`in performance between the logic and DRAM technologies. A simple logic
`circuit fabricated in a logic technology can be twice as fast as a comparable
`
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`482
`
`EMBEDDED MEMORIES DESIGNS AND APPLICATIONS
`
`circuit fabricated in a high-yield, commodity DRAM technology. As a result
`of the tradeoffs, while the DRAM technologies are capable of dense features,
`the devices have lower drive capability. Thus, to drive the next stages, the
`devices have to be made larger (i.e., wider), and the indirect consequence is that
`despite the high circuit density of a DRAM process, it lags about one(cid:173)
`to one-half generation behind the logic technology process. The logic technol(cid:173)
`ogy may have up to seven or eight levels of high-performance wiring (intercon(cid:173)
`nect) as compared with two or three for the DRAMs, and it requires an
`extremely planar surface at every level.
`These relative tradeoffs between the two technologies have spawned argu(cid:173)
`ments regarding which technology should be preferred for the embedded
`D RA Ms-- fabricating memory in a logic-based technology versus fabricating
`logic circuits in a DRAM-based technology.
`An ASIC with embedded DRAM costs about 40% more than the same size
`die with pure logic, and combining the two produces logic that is 10-30%
`slower than the pure logic in the same process geometry. Also, embedded
`DRAM requires internal built-in-self test (BIST) structures and additional
`testing, which can increase the time to market. Due to these disadvantages, the
`embedded DRAM approach may not be appropriate for every design. The first
`to use embedded DRAM technology were the graphics, networking, and data
`storage applications. Graphic controllers use embedded DRAM to boost the
`throughput, network controllers are replacing embedded SRAM with large
`DRAM buffers, and disk drive controllers are embedding DRAM because
`discrete devices take up too much board area. A number of traditional memory
`manufacturers such as Mitsubishi, Toshiba, and Samsung, and so on, offer
`embedded DRAM technology for the ASICs. Also, many logic process vendors
`supply ASICs with embedded memory macros and intellectual property (IP)
`cores.
`A major advantage of embedding DRAM is the much lower power
`consumption, because it eliminates tl;ie need for power-consuming driver
`circuits and allows the circuits to operate at chip's internal voltage, which is
`typically below 2 V. Embedding DRAM improves system performance, be(cid:173)
`cause the signals between CPU and memory no longer suffer the delays from
`the drivers and additional peripheral chips (or PCB) routing. However, the
`major performance boost comes when the system is adapted to take full
`advantage of the embedded DRAM capabilities. For example, by widening the
`interface between the CPU and the DRAM array from the typical 64 bits to
`256 bits, a 100-MHz DRAM array can provide a memory bandwidth of 3
`Gbytes/s. Such wide interfaces are not practical with discrete designs because
`the package size on the ASIC would be prohibitively expensive. The embedded
`array has no such limitation.
`Although DRAM is more complicated to work with compared to any other
`available memory, it is popular as discrete implementation because it is the
`most compact memory technology available, and therefore the cheapest. The
`size difference between a DRAM and a SRAM can be nearly tenfold. In a
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`0.25-pm process, a DRAM memory cell occupies 0.6-1.0pm 2
`, whereas the
`SRAM cell occupies 5-9 pm 2
`. Therefore, an embedded DRAM can allow an
`ASIC to contain as much as 128 Mb in a 0.25-pm process.
`Another advantage is noise reduction. The interconnect between the proces(cid:173)
`sor and the memory carries some of the highest-frequency signals that generate
`electrical noise, which is increasingly difficult to control as the system clock
`speeds increase. The fact that a memory bus contains many high-speed signals
`routed together makes the problem worse. Therefore, bringing the signals
`inside the ASIC by using embedded DRAM approach reduces the difficulty of
`controlling electrical noise on the board. Figure 6.2 shows (a) an on-chip
`DRAM that eliminates both the PCB traces and two sets of I/O drivers
`required and (b) an ASIC plus a discrete DRAM design approach [3]. The
`embedding of DRAM can also improve the granularity of the ASIC itself,
`because it allows the system designers to select an optimum size for their
`system memory without any waste.
`The embedded DRAM can reduce the system engineering effort and
`therefore, possibly, the time to market. While the discrete DRAM has many
`access modes, embedded DRAM has only one basic mode, which eliminates
`the need for extensive architectural analysis to determine which type of DRAM
`provides the best system performance. Despite these savings, there are some
`drawbacks also, such as the process costs, technical risks, and additional test
`the embedded memory approach. Although embedded
`requirements for
`DRAM lowers some of the system costs, the cost of the ASIC is much greater
`
`(a)
`
`PCB
`connection
`
`(b)
`
`Figure 6.2 A comparison of (a) ASIC with embedded DRAM and (b) ASIC with PCB
`connection to a discrete DRAM [3].
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`EMBEDDED MEMORIES DESIGNS AND APPLICATIONS
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`and may override the system savings. An embedded DRAM process costs
`nearly 40% more to run than a logic process, because it requires extra
`production steps (i.e., more masks). As a result, an ASIC with on-chip DRAM
`is almost always more expensive than a pure logic ASIC combined with a
`discrete DRAM approach.
`Memory testing has several components that are different from the logic
`testing, and need specialized tests such as the functional test patterns to detect
`for the memory array pattern sensitivity faults and data retention measure(cid:173)
`ments, under worst-case refresh timings and operating temperature extremes.
`While these tests are routinely performed by the commodity DRAM manufac(cid:173)
`turers, the ASIC manufacturers may not be equipped to perform this complex
`testing on the embedded DRAMs. Therefore, the embedded DRAMs in a logic
`process may require a different approach such as the design for testability
`(DFT) and built-in self-test (BIST) techniques. These DFT and BIST tech(cid:173)
`niques for embedded memories were discussed in Semiconductor Memories,
`Chapter 5. The addition of testability requirements to embedded memories
`may increase the time to market, as well as the system cost.
`A key advantage of the embedded memory approach is the higher packag(cid:173)
`ing density and board space saving, which is a very desirable feature for the
`notebook computers, mobile computing, and portable communication devices.
`In the conventional multichip memory approach, interconnections require
`large 1/0 buffers to overcome package and board level trace impedances. The
`resultant increased power means limited battery life and often reduced reliabil(cid:173)
`ity. It is estimated that a graphic controller with embedded DRAM consumes
`roughly 500-750 mW, which is roughly 25% the power of its multichip
`alternative, consuming approximately 2.5 W.
`The transistor gate oxide thicknesses differ for the logic and memory cell
`processes. The standard logic transistors have thin oxides with low turn-on
`threshold voltages to minimize switching time and maximize performance. In
`contrast, many memory processes require thicker gate oxide transistors that
`have high turn-on threshold voltages to minimize off-transistor leakage cur(cid:173)
`rent, which is a prime determinant of the required DRAM refresh frequency.
`Also, thicker oxides improve data retention characteristics for the EPROM,
`EEPROM, and flash memory, because they can help memory cells withstand
`the effects of high voltages and corresponding electrical field stresses during
`repeated programming and erase cycles.
`Mitsubishi for its larger than 0.25-µm design processes, uses normal thin
`gate oxide logic transistors for fabricating the DRAM memory cells also,
`depending on the lower operating voltages to reduce leakage current. However,
`at 0.25-µm and below processes, Mitsubishi's HyperDRAM process uses
`dual-oxide thicknesses and adds three processing steps. Standard logic and
`HyperDRAM share the same metal pitch and therefore the same logic-layout
`libraries but have different logic timing. Mitsubishi's triple-well approach
`isolates the DRAM substrate from the bias and injected noise originating in
`the logic and standard SRAM circuits and also contains any required DRAM
`substrate bias (see Figure 6.3) [4]. Embedded memory density depends on the
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`485
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`Figure 6.3 Mitsubishi embedded DRAM triple-well process cross section [4].
`
`internal bus-width, including optional parity support, array aspect ratio, the
`number of memory macros, and logic gate count.
`In addition to providing embedded DRAM for ASIC applications, Mit(cid:173)
`subishi leverages its eDRAM processes to build the 3-D RAM graphic chip
`that combines 1.25 Mbytes of DRAM with a high-performance ALU and also
`combines the M32R/D 32-bit RISC CPU with 2 Mbytes of DRAM. Mitsubishi
`has ported its 32-bit M32R CPU not only to the embedded DRAM with
`M32R/D, but also to the flash memory with the M32R/E family.
`Another example is Samsung Semiconductor, which supplies merged
`DRAM and logic on MDL90, a 3.3-V, 0.35-/Im process, with three-layer or
`four-layer metal process. This process is the same that the company uses for
`its 500-MHz Alpha 21164 CPU. It supports as much as 24 Mbits of extended
`dataout (EDO) DRAM or SDRAM. A four-well approach ensures isolation
`between the logic and DRAM subsections. There are other vendors offering
`embedded flash memory fabricated on an EEPROM process, such as Atmel,
`Hyundai, Lucent Technologies, Motorola, and Texas Instruments. EEPROM
`variants, although they have more complex cell structures than the NOR
`alternatives, offer efficient programming and erasing that minimizes the re(cid:173)
`quired size of on-chip charge pumps for scaling down to low-voltage operation,
`and, unlike the NAND flash memory, are appropriate for both code and data
`storage. Some companies are also planning to introduce FRAM as part of their
`embedded memory portfolio. However, FRAM has a more complex manufac(cid:173)
`turing process because of its specialized capacitor-dielectric material structure.
`The selection of embedded memory approach as compared to the discrete
`DRAM-based memory systems has advantages as well as disadvantages in
`three areas of consideration, as follows:
`
`1. On-Chip Memory Inte1face
`
`· The replacement of the off-chip drivers with smaller on-chip drivers can
`reduce power consumption significantly, because large board wire capac(cid:173)
`itive loads are avoided. For example, a system that needs a 4-Gbyte/s
`bandwidth and a bus width of 256 bits, built with discrete SDRAMs
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`486
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`EMBEDDED MEMORIES DESIGNS AND APPLICATIONS
`
`(16-bit interface at 100 MHz), would require about 10 times the power of
`an eDRAM with an internal 256-bit interface. However, even though the
`use of eDRAM may reduce overall power consumption of the system, the
`power consumption per chip may increase, and therefore the junction
`temperature may increase, which can affect the DRAM retention time.
`• Embedded DRAMs can achieve much higher clock frequencies than the
`discrete SDRAMs, because the chip interface can be 512 bits wide (or even
`higher) as compared to the discrete SDRAMs that are limited to 16-64
`bits. It is possible to make a 4-Mb eDRAM with a 256-bit interface,
`whereas it would require 16 discrete 4-Mb chips (organized as 256K x 16)
`to achieve the same width, and the granularity of such a discrete system
`is 64 Mb (overcapacity for an application that needs, say, 4 Mb of
`memory).
`• In eDRAMs, interconnect wire lengths can be optimized for a given
`application, which can result in lower propagation delays and higher