(12) United States Patent
`Weathers et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,656,256 B2
`Feb. 18, 2014
`
`USOO8656256B2
`
`APPARATUS AND METHOD FOR
`MULT-MODE OPERATION OF A FLASH
`MEMORY DEVICE
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(54)
`
`(75)
`
`Inventors: Anthony D. Weathers, San Diego, CA
`(US); Richard D. Barndt, San Diego,
`CA (US); Ashot Melik-Martirosian,
`San Diego, CA (US)
`
`(73)
`
`Assignee: STEC, Inc., Santa Ana, CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 119 days.
`
`(21)
`
`Appl. No.: 13/177,482
`
`(22)
`
`Filed:
`
`Jul. 6, 2011
`
`(65)
`
`Prior Publication Data
`US 2012/O24OO12 A1
`Sep. 20, 2012
`
`(60)
`
`(51)
`
`(52)
`
`(58)
`
`Related U.S. Application Data
`Provisional applicationNo. 61/362,263, filed on Jul. 7,
`2010.
`
`Int. C.
`GI IC 29/00
`G06F I3/00
`G06F 3/28
`GIC II/34
`GIC I6/06
`GITC 700
`U.S. C.
`USPC ...... 714/773: 714/763; 711/102: 365/185.09;
`365/200
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`Field of Classification Search
`None
`See application file for complete search history.
`
`7,444.543 B2 *
`10/2008 Babudri et al. .............. T14?6.32
`3/2006 Babudri et al. .......... 365,185.09
`2006.0062046 A1*
`3/2008 Brown et al. ................. T14f763
`2008.00721 18 A1*
`2009/0327591 A1* 12/2009 Moshayedi ...
`... 711,103
`2010.012201.6 A1* 5, 2010 Marotta et al. .
`... 711,103
`2010, O257430 A1* 10, 2010 Chen ..............
`714,773
`2010/0332922 A1* 12/2010 Chang et al. .................. T14,704
`2013,0003457 A1* 1 2013 Wood et al. .............. 365,185.03
`OTHER PUBLICATIONS
`
`
`
`Jagmohan, et al., “Write Amplification Reduction in NAND Flash
`through Multi-Write Coding”, Storage Conference, 2010, MSST.
`Birrell, et al., “A Design for High-Performance Flash Disks'. ACM
`Operating Systems Review, Apr. 2007, pp. 88-93, 41(2).
`Hu, et al., “Write amplification analysis in flash-based solid state
`drives', in SYSTOR, May 4-6, 2009, Haifa, Israel.
`Rosenblum, et al., “The design and implementation of a log-struc
`tured file system”, ACM TOCS, Feb. 1992, pp. 26-52, vol. 10, No. 1.
`* cited by examiner
`Primary Examiner — Guerrier Merant
`(74) Attorney, Agent, or Firm — McDermott Will & Emery
`LLP
`
`ABSTRACT
`(57)
`Disclosed is an apparatus and method for operating a multi
`level cell (MLC) flash memory circuit. Data is read from a
`memory block of a plurality of memory blocks in the MLC
`flash memory circuit, wherein each of the plurality of
`memory blocks can operate in one of at least three modes of
`operation comprising an MLC mode, a single-level cell
`(SLC) mode and a defective mode, and wherein the memory
`block is initially operating in the MLC mode. Error correction
`is performed on the read data to correct read errors in the read
`data. A determination is made if a number of bits corrected by
`the error correction exceeds a predetermined threshold value.
`If the number of bits corrected by the error correction exceeds
`the predetermined threshold value, the operating mode of the
`memory block is switched from the MLC mode to the SLC
`mode.
`
`20 Claims, 4 Drawing Sheets
`
`100
`
`Controller 104
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`Storage
`Meir 18
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`Flash Memory 112
`Registes
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`Corder
`16
`
`NAND
`Array
`18
`-----
`
`Flash Memory
`12
`
`Flash Memory
`112
`
`Micron Ex. 1046, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`U.S. Patent
`
`Feb. 18, 2014
`
`Sheet 1 of 4
`
`US 8,656.256 B2
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`Micron Ex. 1046, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`

`

`U.S. Patent
`
`Feb. 18, 2014
`
`Sheet 2 of 4
`
`US 8,656.256 B2
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`Micron Ex. 1046, p. 3
`Micron v. Vervain
`IPR2021-01547
`
`

`

`U.S. Patent
`U.S. Patent
`
`Feb. 18, 2014
`
`Sheet 3 of 4
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`US 8,656.256 B2
`US 8,656,256 B2
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`Micron Ex. 1046, p. 4
`Micron v. Vervain
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`Micron Ex. 1046, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`

`

`U.S. Patent
`
`Feb. 18, 2014
`
`Sheet 4 of 4
`
`US 8,656.256 B2
`
`
`
`
`
`
`
`
`
`502
`
`504
`
`506
`
`Read data from a
`memory block
`
`Perform error Correction
`On the read data
`
`Does the
`number of bits
`corrected by the error
`Correction exceed a
`threshold?
`
`
`
`50
`
`Switch the memory
`block from MLC mode
`to SLC mode
`
`FIG. 4
`
`Micron Ex. 1046, p. 5
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,656,256 B2
`
`1.
`APPARATUS AND METHOD FOR
`MULT-MODE OPERATION OF A FLASH
`MEMORY DEVICE
`
`This application claims priority from U.S. Provisional
`Application No. 61/362.263, filed Jul. 7, 2010, which is incor
`porated herein by reference in its entirety.
`
`TECHNICAL FIELD
`
`The Subject technology relates generally to memory
`devices and in particular to multi-level cell flash memory
`devices.
`
`BACKGROUND
`
`10
`
`15
`
`2
`corrected by the error correction exceeds the predetermined
`threshold value, Switching the operating mode of the memory
`block from the MLC mode to the SLC mode.
`The disclosed subject matter also relates to a system for
`adjusting a memory parameter associated with a MLC flash
`memory circuit. The system comprises a host interface con
`figured to be operably coupled to a host device, to receive data
`from the host device, and to send data to the host device, a
`memory interface operably coupled to the MLC flash
`memory circuit, a storage medium interface operably coupled
`to a Volatile memory, and a controller operably coupled to the
`host interface. The controller is operable to read data from a
`memory block of a plurality of memory blocks in the MLC
`flash memory circuit, wherein each of the plurality of
`memory blocks can operate in one of at least three modes of
`operation comprising an MLC mode, a SLC mode and a
`defective mode, and wherein the memory block is initially
`operating in the MLC mode. The controller is further oper
`able to perform error correction on the read data to correct
`read errors in the read data, determine if a number of bits
`corrected by the error correction exceeds a predetermined
`threshold value, and if the number of bits corrected by the
`error correction exceeds the predetermined threshold value,
`switch the operating mode of the memory block from the
`MLC mode to the SLC mode.
`The disclosed subject matter also relates to a machine
`readable medium including machine-executable instructions
`for performing a method for operating a MLC flash memory
`circuit. The method comprises the steps of reading data from
`a memory block of a plurality of memory blocks in the MLC
`flash memory circuit, wherein each of the plurality of
`memory blocks can operate in one of at least three modes of
`operation comprising an MLC mode, a SLC mode and a
`defective mode, and wherein the memory block is initially
`operating in the MLC mode, and performing error correction
`on the read data to correct read errors in the read data. The
`method further comprises the steps of determining if a num
`ber of bits corrected by the error correction exceeds a prede
`termined threshold value, and if the number of bits corrected
`by the error correction exceeds the predetermined threshold
`value, Switching the operating mode of the memory block
`from the MLC mode to the SLC mode.
`It is understood that other configurations of the subject
`technology will become readily apparent to those skilled in
`the art from the following detailed description, wherein vari
`ous configurations of the Subject technology are shown and
`described by way of illustration. As will be realized, the
`Subject technology is capable of other and different configu
`rations and its several details are capable of modification in
`various other respects, all without departing from the Scope of
`the Subject technology. Accordingly, the drawings and
`detailed description are to be regarded as illustrative in nature
`and not as restrictive.
`
`25
`
`30
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`35
`
`Flash memory is an improved form of Electrically-Eras
`able Programmable Read-Only Memory (EEPROM). Tradi
`tional EEPROM devices are only capable of erasing or writ
`ing one memory location at a time. In contrast, flash memory
`allows multiple memory locations to be erased or written in
`one programming operation. Flash memory can thus operate
`at higher effective speeds than traditional EEPROM.
`Flash memory enjoys a number of advantages over other
`storage devices. It generally offers faster read access times
`and better shock resistance than a hard disk drive (HDD).
`Unlike dynamic random access memory (DRAM), flash
`memory is non-volatile, meaning that data stored in a flash
`storage device is not lost when power to the device is
`removed. For this reason, a flash memory device is frequently
`referred to as a flash storage device, to differentiate it from
`volatile forms of memory. These advantages, and others, may
`explain the increasing popularity of flash memory for storage
`applications in devices Such as memory cards, USB flash
`drives, mobile phones, digital cameras, mass storage devices,
`MP3 players and the like.
`Flash memory may use single-level cell (SLC) flash
`memory, which is configured to store one bit per memory cell,
`or multi-level cell (MLC) flash memory, which is configured
`to store multiple bits (e.g., two) of data per memory cell.
`While MLC flash memory may provide a higher storage
`density due to its ability to store more than one bit per cell, the
`maximum number of programferase cycles that can be per
`formed on MLC flash memory is significantly lower than the
`maximum number of programferase cycles that can be per
`formed on SLC flash memory. However, MLC flash memory
`is significantly less expensive than SLC flash memory and
`therefore may be the only commercially viable option for
`many storage applications. Accordingly, there is a need for
`improved techniques for more efficiently utilizing and man
`50
`aging MLC flash memory for data storage.
`
`40
`
`45
`
`SUMMARY
`
`The disclosed subject matter relates to a method for oper
`ating a multi-level cell (MLC) flash memory circuit. The
`method comprises the steps of reading data from a memory
`block of a plurality of memory blocks in the MLC flash
`memory circuit, wherein each of the plurality of memory
`blocks can operate in one of at least three modes of operation
`comprising an MLC mode, a single-level cell (SLC) mode
`and a defective mode, and wherein the memory block is
`initially operating in the MLC mode, and performing error
`correction on the read data to correct read errors in the read
`data. The method further comprises the steps of determining
`if a number of bits corrected by the error correction exceeds a
`predetermined threshold value, and if the number of bits
`
`55
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A detailed description will be made with reference to the
`accompanying drawings:
`FIG. 1 is a block diagram illustrating components of a data
`storage system according to example aspects of the Subject
`technology.
`FIG. 2 is a graph illustrating example threshold Voltage V,
`distributions for an MLC flash memory before being
`switched from an MLC mode to an SLC mode.
`FIG.3 is a graph illustrating example threshold voltage V,
`distributions for an MLC flash memory after being switched
`from an MLC mode to an SLC mode.
`
`60
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`65
`
`Micron Ex. 1046, p. 6
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,656,256 B2
`
`3
`FIG. 4 illustrates a process by which an MLC flash memory
`circuit is operated.
`
`DETAILED DESCRIPTION
`
`4
`Host interface 106 is configured to be coupled to host
`device 102, to receive data from host device 102 and to send
`data to host device 102. Host interface 106 may include both
`electrical and physical connections for operably coupling
`host device 102 to controller 104, for example, via the I/O
`interface of controller 104. Hostinterface 106 is configured to
`communicate data, addresses, and control signals between
`host device 102 and controller 104. Alternatively, the I/O
`interface of controller 104 may include and/or be combined
`with host interface 106. Host interface 106 may be configured
`to implement a standard interface. Such as Serial-Attached
`SCSI (SAS), Fiber Channel interface, PCI Express (PCIe),
`SATA, USB, and the like. Host interface 106 may be config
`ured to implement only one interface. Alternatively, host
`interface 106 (and/or the I/O interface of controller 104) may
`be configured to implement multiple interfaces, which are
`individually selectable using a configuration parameter
`selected by a user or programmed at the time of assembly.
`Host interface 106 may include one or more buffers for buff
`ering transmissions between host device 102 and controller
`104.
`Flash memory 112 represents a non-volatile memory
`device for storing data. According to one aspect of the Subject
`technology, flash memory 112 includes, for example, a two
`bit MLC flash memory. Flash memory 112 may include a
`single flash memory device or chip, or, as depicted by FIG. 1,
`or may include multiple flash memory devices or chips
`arranged in multiple channels. Flash memory 112 is not lim
`ited to any particular capacity or configuration. For example,
`the number of physical blocks, the number of physical pages
`per physical block, the number of sectors per physical page,
`and the size of the sectors may vary within the scope of the
`Subject technology.
`Flash memory 112 may have a standard interface specifi
`cation. This standard ensures that chips from multiple manu
`facturers can be used interchangeably (at least to a large
`degree). The interface hides the inner working of the flash
`memory and returns only internally detected bit values for
`data. The interface of flash memory 112 may be used to access
`one or more internal registers 114 and an internal flash con
`troller 116 for communication by external devices. In some
`aspects, registers 114 may include address, command, and/or
`data registers, which internally retrieve and output the neces
`sary data to and from a NAND memory cell array 118. For
`example, a data register may include data to be stored in
`memory array 118, or data after a fetch from memory array
`118, and may also be used for temporary data storage and/or
`act like a buffer. An address register may store the memory
`address from which data will be fetched to host 102 or the
`address to which data will be sent and stored. A command
`register may be included to control parity, interrupt control,
`and the like. Internal flash controller 116 may be accessible
`via a control register to control the general behavior of flash
`memory 112. Internal flash controller 116 and/or the control
`register may control the number of stop bits, word length,
`receiver clock source, and may also control Switching the
`addressing mode, paging control, coprocessor control, and
`the like.
`Controller 104 is configured to store data received from
`host device 102 into in a memory block of flash memory 112
`in response to a write command from host device 102. Con
`troller 104 is further configured to read data stored in the
`memory block and to transfer the read data to host device 102
`in response to a read command from host device 102. Con
`troller 104 may use one or more error correction algorithms
`when reading and writing data to detect and correct bit errors
`in the data being written and read. When the bit errors in a
`
`15
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`
`FIG. 1 is a block diagram illustrating components of a data
`storage system according to aspects of the Subject technology.
`As depicted in FIG. 1, data storage system 100 (e.g., a solid
`state drive) includes data storage controller 104, host inter
`face 106, storage medium 108, and flash memory 112. Con
`10
`troller 104 may include a processor is configured to execute
`code or instructions to perform the operations and function
`ality described herein, manage request flow and address map
`pings, and to perform calculations and generate commands.
`The processor may be a general-purpose microprocessor, a
`microcontroller, a digital signal processor (DSP), an applica
`tion specific integrated circuit (ASIC), a field programmable
`gate array (FPGA), a programmable logic device (PLD), a
`controller, a state machine, gated logic, discrete hardware
`components, or a combination of the foregoing.
`Controller 104 also may include several internal compo
`nents (not shown) Such as a read-only memory, a flash com
`ponent interface (e.g., a multiplexer to manage instruction
`and data transport along a serial connection to flash memory
`112), an I/O interface, error correction circuitry, and the like.
`In some aspects, all of these elements of controller 104 may
`be integrated into a single chip. In other aspects, these ele
`ments may be separated into one or more discrete compo
`nentS.
`One or more sequences of instructions may be stored as
`firmware on ROM within controller 104 and/or its processor.
`One or more sequences of instructions may be software stored
`and read from storage medium 108, flash memory 112, or
`received from host device 102 (e.g., via host interface 106).
`ROM, storage medium 108 and flash memory 112 represent
`examples of machine or computer readable media on which
`instructions/code executable by controller 104 and/or its pro
`cessor may be stored. Machine or computer readable media
`may generally refer to any medium or media used to provide
`instructions to controller 104 and/or its processor, including
`both volatile media, Such as dynamic memory used for Stor
`age media 108 or for buffers within controller 104, and non
`Volatile media, Such as electronic media, optical media, and
`magnetic media.
`Storage medium 108 represents volatile memory used to
`temporarily store data and information used to manage data
`storage system 100. The data may include logical to physical
`address mapping tables, wear-leveling data structures, etc.
`Storage medium 108 may be static and/or dynamic random
`access memory (RAM) such as double data rate (DDR)
`RAM. Other types of RAM also may be used to implement
`storage medium 108. Memory 108 may be implemented
`using a single RAM module or multiple RAM modules.
`While storage medium 108 is depicted as being distinct from
`controller 104, it should be noted that storage medium 108
`may be incorporated into controller 104 without departing
`from the scope of the Subject technology. Alternatively, Stor
`age medium 108 may be a non-volatile memory Such as a
`magnetic disk, flash memory, peripheral SSD, or the like.
`Host device 102 represents any device configured to be
`coupled to data storage system 100 and to store data in data
`storage system 100. Host device 102 may be a computing
`system Such as a personal computer, a server, a workstation, a
`laptop computer, PDA, Smart phone, and the like. Alterna
`tively, host device 102 may be an electronic device such as a
`digital camera, a digital audio player, a digital video recorder,
`and the like.
`
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`Micron Ex. 1046, p. 7
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,656,256 B2
`
`5
`particular memory block exceed the correction capabilities of
`the algorithm, that memory block fails and is preferably
`removed from use in data storage system 100. As will be
`described in more detail below, the subject technology pro
`poses changes an operating mode of a memory block operat
`ing as MLC flash memory to an SLC operating mode for that
`memory block rather than removing the memory block from
`SC.
`As noted above, flash memory has limited endurance and
`block erases (e.g., MLC flash memory typically has 10K
`write-erase cycles). As the limit on the program-erase cycles
`is approached, and memory blocks begin to fail, the memory
`blocks taken out of circulation, thus reducing the overall raw
`capacity of data storage system 100. However, taking defec
`tive blocks out of circulation places a greater burden on the
`remaining blocks and causes them to wear even more rapidly.
`This results in an acceleration of the deterioration near the end
`of life.
`Log-structured file systems (LFSS) may be used to mitigate
`the effect of limited endurance and block erases. In an LFS, a
`translation layer maintains a mapping between logical and
`physical block addresses. During a write operation, logical
`block addresses (LBAS) are given and the corresponding
`logical pages are written (e.g., sequentially) to physical pages
`in the flash memory. When a logical page is updated, the new
`data is written to the next available physical page, and the
`previous physical page holding the original data is marked
`invalid. The logical to physical page mapping in the transla
`tion layer is then updated, so that the logical address will point
`to the new physical page. This procedure typically helps with
`wear leveling, where writes are spread across the entire
`capacity of the data storage system and no individual blocks
`tend to experience significantly more programming cycles
`than the rest. However, the free space will eventually be
`diminished and invalid pages will have to be reclaimed in
`order to provide new erased blocks for upcoming writes. As
`noted above, this reclamation corresponds to garbage collec
`tion, which involves erasing blocks that contain invalid data
`and relocating valid data that may be contained in those
`blocks.
`A measure of the number of extra physical writes that take
`place for each logical write operation is write amplification.
`As more and more memory blocks fail and are removed from
`use, the number of physical writes for each logical write
`increases, which speeds up the wear on the remaining
`memory blocks and reduces the system endurance. If C is
`defined as the user capacity and R is defined as the total raw
`capacity, then an over provisioning ratio can be defined as
`C=R/C. The write amplification, A(C.), is a function of the
`over provisioning ratio. Ife is the rated endurance of a flash
`chip, then system endurance can be given by:
`
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`6
`Voltage V of the cell, and V can be manipulated by the
`amount of charge put on a floating gate of the cell. Placing
`charge on the floating gate will increase the threshold Voltage
`of the cell. In the example of FIG. 2, a two-bit MLC is
`illustrated, where the memory cell is capable of storing four
`states (or amounts of charge) percell. These four states equate
`to different bit values (e.g., 11,01, 00, 10). However, it should
`be noted that MLC is not limited to two bits. For example, for
`a memory cell to hold three bits, it would be necessary to use
`eight states (e.g., 000, 001, 010, 011, 100, 101, 110, 111).
`As can be seen in FIG. 2, four distribution states 302 to 308
`are shown, together with corresponding read levels 312 to
`316. By altering the amount of charge put on the floating gate
`of the cell, it is possible to manipulate the threshold voltage
`V value of the cell. The initial or erased state of a cell
`corresponds to distribution state 302. Placing charge on the
`floating gate will increase the threshold voltage of the cell,
`and these charge amounts can be incremented to store charge
`amounts (e.g., corresponding to distribution states 304 to
`308). Thus, it is possible for the two-bit MLC flash memory of
`FIG. 2 to store two-bit values (e.g., 11, 01, 00, 10). As flash
`memory ages and the number of programming cycles per
`formed on the memory cells increases, the distributions
`between to widen and shift. As the distributions begin to
`overlap on the edges, the likelihood of bit errors increases.
`When an MLC flash memory block begins to exhibit bit
`errors that approach or reach the capabilities of the error
`correction algorithm being used in the system, the Subject
`technology proposes operating the memory block in an SLC
`mode rather than marking the memory block as bad and
`removing it from circulation. As illustrated in FIG. 3, which
`illustrates example threshold voltage V distributions for an
`SLC flash memory, the number of distributions is reduced
`from four to two thereby allowing the distributions to be
`spaced farther apart from each other. While the reduction in
`the number of distribution states available for the memory
`cells reduces the number of bits that can be stored in each
`memory cell from two to one, using the memory block as an
`SLC memory block allows the memory block to continue to
`be used at half capacity for data storage and prolong the life of
`the data storage system.
`In Summary, the Subject technology provides for assigning
`three modes to memory blocks, including an MLC mode, an
`SLC mode, and a defective mode. Initially, all memory blocks
`for a MLC flash memory circuit operate in the MLC mode.
`When a given memory block fails, that block can be switched
`from the MLC mode to the SLC mode. During future pro
`gramming operations, it is possible that the memory block
`(having been Switched to SLC mode) can fail again. At that
`stage, the block can be switched from SLC mode to a defec
`tive mode, so that the block is taken out of circulation. This
`allows for raw capacity for an MLC flash memory circuit to
`deteriorate at a slower rate, thereby extending the life of the
`circuit.
`FIG. 4 illustrates a process by which an MLC flash memory
`circuit is operated according to the Subject technology. Fol
`lowing start block 502, data is read from a memory block of
`a plurality of memory blocks in a MLC flash memory circuit
`at step 504. Initially, all of the memory blocks may be oper
`ated in the MLC mode.
`As noted above with reference to FIG. 1, controller 104 is
`configured to store data received from a host device 102 into
`a memory block of flash memory 112 in response to a write
`command from host device 102. Controller 104 is further
`configured to read data stored in the memory block, and to
`transfer the read data to host device 102 in response to a read
`command from host device 102.
`
`40
`
`45
`
`50
`
`E = e--
`A (a)
`
`(1)
`
`55
`
`From Formula 1, it can be understood that as the number of
`cycles increases and as defective blocks are taken out of
`circulation, C. decreases and A(O) increases. Thus, both of the
`terms C. and A(O) contribute to the reduction of system endur
`ance. The Subject disclosure provides for reducing the rate at
`which the system deteriorates.
`FIG. 2 is a graph illustrating threshold voltage V distribu
`tions for an MLC flash memory. As noted above, MLC flash
`is a type of flash memory which stores two (or more) bit
`values percell. The bit values are determined by the threshold
`
`60
`
`65
`
`Micron Ex. 1046, p. 8
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,656,256 B2
`
`5
`
`10
`
`15
`
`25
`
`7
`At step at step 506, error correction is performed on the
`read data to correct read errors in the read data. In this regard,
`controller 104 is configured to generate an error correction
`code (ECC) for data in data storage system 100 in conjunction
`with performing a write operation for writing the data to a
`memory block in flash memory 112. Controller 104 can write
`the error correction code associated with the data to the
`memory block in flash memory 112. During a read operation,
`controller 104 can use the error correction codes to determine
`whether a data error occurs when controller 104 reads data
`from the memory block.
`A data error occurs if one or more data bits of the data read
`from the memory block by controller 104 are corrupt. If a data
`error occurs when controller 104 reads data from the memory
`block, controller 104 can perform error correction on the data
`by using the ECC previously generated for the data.
`Thus, at decision step 508, an inquiry is made as to whether
`a number of bits corrected by the error correction exceeds a
`predetermined threshold value. If the answer to this inquiry is
`yes, the operating mode of the memory block is Switched
`from the MLC mode to the SLC mode at step 510, and the
`process ends at end block 512. The threshold value may be set
`at the maximum number of bits that can be corrected using the
`ECC. Alternatively, the threshold value may be set below the
`maximum number of bits.
`As noted above with reference to FIG. 3, each of the plu
`rality of memory blocks can operate in one of at least three
`modes of operation, including an MLC mode, an SLC mode
`and a defective mode. To switch operation from the two-bit
`MLC mode to the SLC mode, controller 104 is configured to
`mark the particular memory cell as operating in SLC mode
`and switch from using the memory cells in the memory block
`for storing two bit values to storing one bit value. According
`to one aspect, controller 104 may operate an MLC flash
`memory block in an SLC operating mode by only writing data
`to the least significant bit (LSB) pages in the memory block
`and stop using the most significant bit (MSB) pages in the
`memory block. When Switching to operating the memory
`block in SLC operating mode, the maximum threshold volt
`age may be lower, which typically results in less damage
`during the programming process.
`Thus, when carrying out the operations of the LFS as
`described above, the MSB page physical addresses are no
`longer used when the memory block is operating in SLC
`mode. Otherwise, the operations by controller 104 for the
`45
`memory block may remain essentially the same relative to the
`memory block operating in MLC mode. Accordingly, it is
`possible that only minor changes in processing the memory
`block are made (e.g., in the LFS) in order to switch from the
`MLC mode to the SLC mode.
`In switching the memory block from the MLC mode to the
`SLC mode, it may be necessary to invalidate the memory
`block, so that it can be reclaimed in a future garbage collec
`tion. To invalidate the memory block, controller 104 can be
`configured to select an available memory block from the
`plurality of memory blocks, move the data from the memory
`block to the available memory block, and mark the memory
`block as invalid. Controller 104 can then assign the operating
`mode of the memory block to the SLC mode. The data can be
`associated with an address mapped to the memory block
`before the data is moved to the available memory block.
`Moving the data from the memory block to the available
`memory block can include mapping the address associated
`with the data to the available memory block.
`After the memory block has been marked invalid, garbage
`collection can be used to reclaim the memory block. For
`example, garbage collection may be invoked when the num
`
`8
`ber of available pages falls below a threshold, or anytime data
`storage system 100 of FIG. 1 is not busy. Garbage collection
`involves erasing blocks that contain invalid data and relocat
`ing valid data that may be contained in those blocks. Further,
`garbage collection involves rewriting valid blocks that were
`already written in location to another location, and typically
`occurs in the background so as to be independent of user
`operations.
`After the memory block (having been switched to SLC
`mode) has been reclaimed, it is possible that the memory
`block can fail again in Subsequent programming. For
`example, duringa Subsequent read operation, it is possible for
`a data error to occur when controller 104 reads data from the
`memory block. Controller 104 can again perform error cor
`rection on the data by using an ECC previously generated for
`the data for reading the data from the memory block. Further,
`controller 104 can determine if a number of bits corrected by
`the error correction exceeds a predetermined threshold value,
`and if so, can Switch the operating mode. This time, since the
`memory block is already in SLC mode, controller 104 can
`Switch the operating mode to the defective mode, so as to
`remove the memory block out of circulation for program
`ming.
`To manage switching of the memory block from the MLC
`mode to the SLC mode, and from the SLC mode to the
`defective mode, controller 104 may be coupled to one or more
`data structures (not shown) for managing logical block
`addresses. For example, a table can be used to contain rows
`with a logical blockaddress, along with the physical address
`for the corresponding one or two blocks associated with that
`logical blockaddress. Other tables may allow controller 104
`to keep track of the number of blocks that are available (e.g.,
`in MLC or SLC mode). For example, an MLC table can be
`used to keep track of the number of blocks that are in MLC
`mode and the physical location of these blocks, and an SLC
`table can be used to keep track of the number of blocks that are
`in SLC mode and the physical l