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`
`(12) United States Patent
`Lee et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,078,794 B2
`Dec. 13, 2011
`
`(54) HYBRID SSD USING A COMBINATION OF
`SLC AND MLC FLASH MEMORY ARRAYS
`
`(75)
`
`Inventors: Charles C. Lee, Cupertino, CA (US);
`David Q. Chow, San Jose, CA (US);
`Abraham Chih-Kang Ma, Fremont, CA
`(US); I-Kang Yu, Palo Alto, CA (US);
`Ming-Shiang Shen, Taipei Hsien (TW)
`
`(73)
`
`Assignee: Super Talent Electronics, Inc., San
`Jose, CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 623 days.
`
`(21)
`
`Appl. No.: 11/926,743
`
`(22)
`
`Filed:
`
`Oct. 29, 2007
`
`(65)
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`Prior Publication Data
`
`US 2008/0215800 Al
`
`Sep. 4, 2008
`
`Int. Cl.
`(2006.01)
`G06F 13/00
`U.S. Cl.
`................................ 711/103; 711/E12.083
`Field of Classification Search ........................ None
`See application file for complete search history.
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,623,552 A
`5,907,856 A
`5,959,541 A
`6,000,006 A
`6,012,636 A
`6,069,920 A
`6,081,858 A
`6,125,192 A
`6,193,152 B1
`6,202,138 B1
`
`4/1997 Lane
`5/1999 Estakhri et al.
`9/1999 DiMaria et al.
`12/1999 Bruce et al.
`1/2000 Smith
`5/2000
`Schulz et al.
`6/2000 Abudayyeh et al.
`9/2000 Bjornetal.
`2/2001 Fernando et al.
`3/2001
`Estakhri et al.
`
`6,230,233 B1
`6,275,894 B1
`6,321,478 B1
`6,324,620 B1 *
`6,418,009 B1 *
`6,547,130 B1
`6,636,929 B1
`6,718,407 B2
`6,880,024 B2
`7,103,765 B2
`7,228,299 B1 *
`7,257,714 B1
`2001/0043174 Al
`2002/0166023 Al
`2003/0046510 Al
`2003/0163656 Al
`2004/0148482 Al
`2004/0255054 Al
`2005/0102444 Al
`
`Lofgren et al.
`5/2001
`8/2001 Kuo et al.
`11/2001
`Klebes
`......... 711/112
`11/2001
`Christenson et al.
`7/2002
`Brunette .................... 361/306.3
`4/2003
`Shen
`10/2003
`Frantz et al.
`4/2004 Martwick
`4/2005 Chen et al.
`9/2006 Chen
`6/2007 Harmer et al .
`8/2007 Shen
`11/2001
`Jacobsen et al.
`11/2002 Nolan et al.
`3/2003 North
`8/2003 Ganton
`7/2004 Grundy et al.
`12/2004 Pua et al.
`5/2005
`Cruz
`
`.................... 707/3
`
`(Continued)
`
`Primary Examiner
`
`Pierre-Michel Bataille
`
`Sean D Rossiter
`Assistant Examiner
`(74) Attorney, Agent, or Firm
`Roger H. Chu
`
`(57)
`
`ABSTRACT
`
`Hybrid solid state drives (SSD) using a combination of
`single-level cell (SLC) and multi-level cell (MLC) flash
`memory arrays are described. According to one aspect of the
`present invention, a hybrid SSD is built using a combination
`SLC and MLC flash memory arrays. The SSD also includes a
`micro-controller to control and coordinate data transfer from
`a host computing device to either the SLC flash memory array
`of the MLC flash memory array. A memory selection indica-
`tor is determined by triaging data file based on one or more
`criteria, which include, but is not limited to, storing system
`files and user directories in the SLC flash memory array and
`storing user files in the MLC flash memory array; or storing
`more frequent access files in the SLC flash memory array,
`while less frequent accessed files in the MLC flash memory
`array.
`
`20 Claims, 14 Drawing Sheets
`
`560
`
`562 -^ I
``il
`
`Examine particular
`information from
`register files
`
`563
`
`System File?
`
`no
`
`564
`
`Store in
`SLC
`
`565
`
`Yes
`
`User
`Directory
`
`no
`
`566
`
`Does the file
`prefix
`have a filename
`prefix
`designated
`SLC ?
`
`567
`
`no
`
`Store in
`MLC
`
`Micron Ex. 1023, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,078,794 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`6/2005 Chen et al.
`2005/0120146 Al
`7/2005 Chen
`2005/0160213 Al
`9/2005 Lee et al.
`2005/0193161 Al
`11/2005 Adams et al.
`2005/0246243 Al
`Sinclair et al.
`200 5/02 5 16 17 Al* 11/2005
`2005/0268082 Al
`12/2005 Poisner
`2006/0065743 Al
`3/2006 Fruhauf
`2 00 6/00 7 5 1 74 Al
`4/2006 Vuong
`2006/0106962 Al
`5/2006 Woodbridge et al.
`2006/0161725 Al
`7/2006 Lee et al.
`
`.....
`
`711/103
`
`.......... ........ 711/108
`
`9/2006 Fausak
`2006/0206702 Al
`10/2006 Fausak
`2006/0242395 Al
`20 0 6/02 7 1 73 1 Al* 11/2006 Kilian et al .
`20 0 7/0 1 13 2 67 Al
`5/2007
`Iwanski et al.
`.......... ........ 711/103
`2008/0104309 Al*
`5/2008 Cheon et al .
`20 0 8/0 1 12 23 8 Al*
`5/2008 Kim et al .
`............. ........ 365/200
`2008/0126680 Al*
`5/2008 Lee et al .
`.............. ........ 711/103
`2009/0100244 Al*
`4/2009 Chang et al .
`.......... ........ 711/172
`2009/0248965 Al* 10/2009 Lee et al .
`.............. ........ 711/103
`4/2010 Chen et al .
`20 1 0/00 82 8 83 Al*
`............ ........ 711/103
`* cited by examiner
`
`Micron Ex. 1023, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`

`

`U.S. Patent
`
`Dec. 13, 2011
`
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`Micron v. Vervain
`IPR2021-01547
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`

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`U.S. Patent
`
`Dec. 13, 2011
`
`Sheet 2 of 14
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`Micron Ex. 1023, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`

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`U.S. Patent
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`Dec. 13, 2011
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`Micron v. Vervain
`IPR2021-01547
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`Micron v. Vervain
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`Micron v. Vervain
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`Dec. 13, 2011
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`Micron v. Vervain
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`Micron v. Vervain
`IPR2021-01547
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`Micron v. Vervain
`IPR2021-01547
`
`

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`U.S. Patent
`
`Dec. 13, 2011
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`Micron Ex. 1023, p. 15
`Micron v. Vervain
`IPR2021-01547
`
`

`

`U.S. Patent
`
`Dec. 13, 2011
`
`Sheet 14 of 14
`
`US 8,078,794 B2
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`Micron Ex. 1023, p. 16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,078,794 B2
`
`1
`HYBRID SSD USING A COMBINATION OF
`SLC AND MLC FLASH MEMORY ARRAYS
`
`FIELD OF THE INVENTION
`
`The present invention relates to secondary storage devices
`such as solid state drive (SSD), and more particularly to a
`hybrid SSD devices using a combination of single-level cell
`(SLC) and multi-level cell (MLC) flash memory array.
`
`BACKGROUND OF THE INVENTION
`
`Portable electronic storage device such as USB flash drive
`has become popular in the past few years replacing other
`forms of storage media such as floppy disk, removable stor-
`age, CD-ROM and DVD commonly used in a computing
`device. Latest trend is to use flash memory as non-volatile
`memory (e.g., NAND flash) to build a secondary storage
`device such as solid state drive (SSD). SSDs do not require
`batteries and do not have any moving parts hence eliminating
`seek time, latency and other electro-mechanical delays inher-
`ent in conventional disk drives.
`There are two types of flash memories today, single-level
`cell (SLC) flash memory and multi-bit cell (MBC) or multi-
`level cell (MLC) flash memory. SLC flash memory stores
`one-bit of data per cell, while MBC or MLC flash memory
`stores more than one bits (e.g., 2, 4 or other higher power of
`2 bits) of data per cell. MLC flash memory has cheaper
`manufacturing costs than SLC does for same amount of stor-
`age or on a per MB (Mega Byte) basis.
`Currently, SSDs are built using the higher cost SLC flash
`memory instead of MLC mainly due to one reason
`relative
`higher data endurance (i.e., number of write/erase cycles).
`The problem associated with this approach is that the cost is
`too high for many practical applications or usages. One solu-
`tion is to use MLC flash memory in a SSD. However, the data
`endurance rate of MLC based SSD could drop as much as a
`factor of ten (10) comparing to the SLC based SSD. This is
`not valid solution. Therefore it would be desirable to have an
`improved SSD device that overcomes the problems described
`herein.
`
`BRIEF SUMMARY OF THE INVENTION
`
`This section is for the purpose of summarizing some
`aspects of the present invention and to briefly introduce some
`preferred embodiments. Simplifications or omissions in this
`section as well as in the abstract and the title herein may be
`made to avoid obscuring the purpose of the section. Such
`simplifications or omissions are not intended to limit the
`scope of the present invention.
`Hybrid solid state drives (SSD) using a combination of
`single-level cell (SLC) and multi-level cell (MLC) flash
`memory arrays are disclosed. According to one aspect of the
`present invention, a hybrid SSD is built using a combination
`SLC and MLC flash memory arrays. The SSD also includes a
`micro-controller to control and coordinate data transfer from
`a host computing device to either the SLC flash memory array
`or the MLC flash memory array. A memory selection indica-
`tor is determined by triaging data file based on one or more
`criteria, which include, but is not limited to, storing system
`files and user directories in the SLC flash memory array and
`storing user files in the MLC flash memory array; or storing
`more frequent access files in the SLC flash memory array,
`while less frequent accessed files in the MLC flash memory
`array.
`
`5
`
`10
`
`2
`According to an exemplary embodiment of the present
`invention, a hybrid solid state drive includes at least the fol-
`lowing: an interface configured for receiving data transfer
`commands from a host computing device, each of the
`received data transfer commands includes either a data read
`or a data write request; a single-level cell (SLC) flash memory
`array; a multi-level cell (MLC) flash memory array; a micro-
`controller configured for controlling the interface, the SLC
`flash memory array and MLC flash memory array, the micro-
`processorextractsparticularcharacteristicsofadatafileasso-
`ciated with said each of the received data transfer commands,
`and then, based on the particular characteristics for the data
`write request, a memory selection indicator is determined by
`triaging the data file to be stored in either the SLC flash
`memory array or the MLC flash memory array based on one
`15 or more criteria; and an address mapping memory, coupling
`to the micro-controller, configured to correlate logical block
`address (LBA) of the data file to a physical block address
`(PBA) associated with one of the SLC flash memory array
`and the MLC flash memory array according to the memory
`20 selection indicator.
`The hybrid solid state drive further includes a read cache
`configured to be a first buffer holding data blocks to be trans-
`ferred to the host computing device, a write cache configured
`to be a second buffer holding data blocks to be written to
`25 either the SLC or MLC flash memory array, one or more
`register files configured to hold the particular characteristics
`for the micro-controller, and a memory switch configured to
`switch between the SLC flash memory array and the MLC
`flash memory array based on the memory selection indicator.
`According to another exemplary embodiment of the
`present invention, a method of writing data in a hybrid solid
`state drive (SSD) includes at least the following steps: receiv-
`ing data transfer commands; determining whether each of the
`received data transfer commands is a data read or a data write
`35 request; when the data write request is determined, extracting
`particular characteristics of a data file associated with said
`each of the received data transfer commands; constructing a
`memory selection indicator by triaging the data file to be
`stored in either a SLC flash memory array or a MLC flash
`40 memory array using the particular characteristics based on
`one or more criteria; correlating logical block address (LBA)
`of the data file to a physical block address (PBA) associated
`with one of the SLC flash memory array and the MLC flash
`memory array according to the memory selection indicator;
`45 and writing data blocks to the physical block address accord-
`ingly.
`The method further includes pre-storing the data blocks
`associated with LBA to a write cache when the data write
`request is determined and storing the particular characteris-
`50 tics of the data file into one or more register files of the
`micro-controller.
`One of the objects, features, and advantages in the present
`invention is to use a smart data file triage method to ensure the
`lower manufacturing cost can be achieved by using a combi-
`55 nation of SLC and MLC flash memory to build a SSD that has
`an acceptable level of data endurance. Other objects, features,
`and advantages of the present invention will become apparent
`upon examining the following detailed description of an
`embodiment thereof, taken in conjunction with the attached
`60 drawings.
`
`30
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`These and other features, aspects, and advantages of the
`65 present invention will be better understood with regard to the
`following description, appended claims, and accompanying
`drawings as follows:
`
`Micron Ex. 1023, p. 17
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,078,794 B2
`
`3
`FIG. 1 is a simplified block diagram showing some com-
`ponents of a computing device in accordance with one
`embodiment of the present invention;
`FIG. 2 is a block diagram showing salient components of
`an exemplary hybrid SSD may be used as a secondary storage
`of the computing system of FIG. 1 in accordance with one
`embodiment of the present invention;
`FIG. 3 is a diagram illustrating an exemplary scheme for
`mapping logical block address (LBA) of files in the hybrid
`SSD of FIG. 2 in accordance with one embodiment of the
`present invention;
`FIG. 4 is a flowchart illustrating an exemplary process of
`writing data in the hybrid SSD of FIG. 2, according to an
`embodiment of the present invention; and
`FIGS. 5A-5E are flowcharts showing several alternative
`methods to tri age files into SLC or MLC in theprocess of FIG.
`4;
`
`FIG. 6 is a diagram illustrating an operating system of the
`computing device of FIG. 1; and
`FIGS. 7A-7D are diagrams and examples showing data
`structures in an operating system which may be used by a
`micro-controller in the exemplary hybrid SSD of FIG. 2,
`according an embodiment of the present invention.
`
`DETAILED DESCRIPTION
`
`In the following description, numerous specific details are
`set forth in order to provide a thorough understanding of the
`present invention. However, it will become obvious to those
`skilled in the art that the present invention may be practiced
`without these specific details. The descriptions and represen-
`tations herein are the common means used by those experi-
`enced or skilled in the art to most effectively convey the
`substance of their work to others skilled in the art. In other
`instances, well-known methods, procedures, components,
`and circuitry have not been described in detail to avoid unnec-
`essarily obscuring aspects of the present invention.
`Reference herein to "one embodiment" or "an embodi-
`ment" means that a particular feature, structure, or character-
`istic described in connection with the embodiment can be
`included in at least one embodiment of the invention. The
`appearances of the phrase "in one embodiment" in various
`places in the specification are not necessarily all referring to
`the same embodiment, nor are separate or alternative embodi-
`ments mutually exclusive of other embodiments. Used
`herein,
`the terms
`"upper",
`"lower",
`"top",
`"bottom",
`"middle", "upwards", and "downwards" are intended to pro-
`vide relative positions for the purposes of description, and are
`not intended to designate an absolute frame of reference.
`Further, the order of blocks in process flowcharts or diagrams
`representing one or more embodiments of the invention do
`not inherently indicate any particular order nor imply any
`limitations in the invention.
`Embodiments of the present invention are discussed herein
`with reference to FIGS. 1-7D. However, those skilled in the
`art will readily appreciate that the detailed description given
`herein with respect to these figures is for explanatory pur-
`poses as the invention extends beyond these limited embodi-
`ments.
`Referring now to the drawings, FIG. 1 is a simplified block
`diagram depicting a computing device 100 (e.g., a desktop, a
`laptop, etc.). The computing device 100 includes an internal
`data bus 120. Coupling to the data bus 120 are one or more
`processor 122, a main memory 124, preferably random
`access memory (RAM), one or more secondary storage
`devices 126 (e.g., hard disk drive, removable storage drive,
`etc.), one or more input interfaces 127 (e.g., keyboard, point-
`
`5
`
`4
`ing device, etc.), one or more output interfaces 128 (e.g.,
`display, printer, etc.) and an optional network interface 130.
`The processor 122 executes instructions from one or more
`modules 1251oaded in the main memory 124. The secondary
`storage device 126 is configured to store data and source of
`the module 125 (e.g., executable binary code) in a non-vola-
`tile medium, which can retain the stored information even
`when not powered. The network interface 130 is configured to
`facilitate data communication to another computing device
`io over a data network (e.g., Internet) wired or wireless.
`FIG. 2 is a block diagram showing salient components of
`an exemplary hybrid solid state drive (SSD) 200 using a
`combination of SLC and MLC flash memory array in accor-
`dance with one embodiment of the present invention. The
`15 hybrid SSD 200 may be configured as a secondary storage for
`the computing device 100 of FIG. 1. The hybrid SSD 200
`comprises a SSD interface 202, a micro-controller or control-
`ler 210, a data read cache 203, a data write cache 204, a set of
`register files 206, a logical-to-physical address mapping
`20 memory 220, a memory switch 222 that facilitates a switch-
`ing function between a SLC flash memory array 226 and a
`MLC flash memory array 228.
`The SSD interface 202 is configured for transferring data
`between the hybrid SSD 200 and a data host (e.g., the com-
`25 puting device 100 of FIG. 1) in one ofthe standards including,
`but not limited to, Advanced Technology Attachment (ATA),
`serial ATA (SATA), and Small Computer System Interface
`(SCSI). The micro-controller 210 (also MCU) is a computer-
`on-a-chip, which is a compact form of the computing device
`30 100. The micro-controller 210 is configured for performing
`controlling the hybrid SSD 200 via various function units
`such as command extractor 212 and logical block address
`(LBA) range decoder 214. The command extractor 212 is
`configured to extract data transfer commands received
`35 through the SSD interface 202 from the host. One of the
`functions is to determine whether the command is a data read
`or write request. The LBA range decoder 214 is configured to
`determine the range of the received LBA based on metadata
`or characteristics of a data file or directory (i.e. file folder)
`4o associated with the data transfer command. The metadata or
`characteristics may include, but not necessarily be limited to,
`file name, file size, file creation date and time, file type, file
`location (e.g., starting cluster number).
`The data read cache 203 and the data write cache 204
`45 comprise volatile memory modules configured as data trans-
`fer buffer between the host and the hybrid SSD 200. The data
`read cache 203 is configured to keep recently requested data
`blocks or clusters. The data write cache 204 is configured to
`hold data in write requests to be stored. The register files 206
`5o are configured to hold particular metadata of a data file rel-
`evant for various function units (e.g., LBA range decoder
`214) to perform tasks. For example, particular data (e.g.,
`starting cluster number and total number of clusters to be read
`or written) of the metadata may be loaded into the register
`files 206 by the micro-controller 210.
`The logical-to-physical address mapping memory 220
`(generally made of static RAM (SRAM)) is configured to
`map logical block address (LBA) to a physical block address,
`which includes a memory selection indicator for the memory
`60 switch 222 to direct data transfer to either the SLC flash
`memory array 226 or the MLC memory array 228. The hybrid
`SSD 200 may be configured to have various capacities (e.g.,
`32 GB, 64 GB, etc.) with different ratios between the SLC
`flash memory array 226 and the MLC flash memory array
`65 228. The ratios may have a range between 10% and 90%. In
`other words, the amount of the SLC flash memory array
`versus the amount of the MLC flash memory array in the
`
`55
`
`Micron Ex. 1023, p. 18
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,078,794 B2
`
`5
`hybrid SSD 200 may be from 10% to 90% depending upon
`applications or usages. The present invention sets no limit as
`to what ratio to be used in the hybrid SSD. One ratio may
`work better in one particular embodiment while different
`ratios may perform better in others. For example, a hybrid
`SSD configured as a secondary storage for archival purpose,
`a very low ratio may be more suitable because the archival
`data is only written once. Therefore, MLC flash memory
`could provide enough data endurance and reliability.
`It is noted that the SLC flash memory array 226 may
`include at least one flash memory chip. Likewise, the MLC
`flash memory array 228 may include at least one MLC flash
`memory chip.
`Referring now to FIG. 3, which is a diagram of an exem-
`plary scheme showing how LBA is mapped to physical
`address of either the SLC or MLC flash memory array in the
`hybrid SSD of FIG. 2, according to an embodiment of the
`present invention. In the scheme, eight LBAs 304 received
`from a host (e.g., received through the SSD interface 202) are
`listed as "system file 1" 304a, "system file 2" 304b, "user file
`1" 304c, "user file 2" 304d, "user file 3" 304e, "user directory
`A" 304f, "user file 4" 304g and "user directory B" 304h. Each
`of the received LBAs 304a-h is mapped to a physical block
`address (PBA) as shown in the first column entry 321 in the
`address mapping memory 320. Corresponding entry in the
`second column 322 represents a memory selection indicator
`marking which type of flash memory array (i.e., SLC or
`MLC) to be stored. For example, "system file 1" 304a is
`mapped to physical block zero (0) of the SLC physical block
`address 326 of the SLC flash memory array 226; "system file
`2" 304b mapped to physical block one (1) of the SLC; "user
`file 2" 304d mapped to physical block five (5) of the MCL
`physical block address 328; and so forth. Dotted lines repre-
`sents a mapping to the SLC physical block address 326, while
`solid lines represents a mapping to the MLC physical block
`address 328. For clarity, content of the second column 322 is
`denoted using "S" for SLC and "M" for MLC in FIG. 3.
`Implementing this feature in the address mapping memory
`220 may be accomplished with an indicative bit (e.g., 0 for
`SLC and 1 or MLC, or vice versa).
`According to one aspect of the present invention, the map-
`ping schemes between LBAs and PBAs are dependent upon
`definitions of cluster and sector with characteristics of the
`flash memory (i.e., blocks and pages). Since flash memory
`need to carry additional information for error correction code
`(ECC), the mapping schemes must include those factors.
`According to another aspect of the present invention, the
`mapping scheme between LBAs 304 and PBAs of either the
`SLC flash memory array 326 or the MLC flash memory array
`328 is configured to allow more efficient usages of the SLC
`and MLC flash memory array. The mapping scheme together
`with other techniques such as wear leveling can prolong data
`endurance of the hybrid SSD while maintaining a reasonable
`manufacturing cost, hence overcoming shortcomings of the
`prior art approach.
`FIG. 4 is a flowchart illustrating an exemplary process 400
`of writing data in the exemplary hybrid SSD 200 of FIG. 2,
`according to an embodiment of the present invention. Since
`writing data to flash memory is a concern for data endurance,
`the process 400 needs to be implemented in a robust manner
`to ensure longest po ssible data reliability out of a given hybrid
`SSD. The process 400 may be implemented in hardware,
`software or a combination of both. Generally process 400 is
`implemented in a micro-controller 210 ofthe hybrid SSD 200
`of FIG. 2.
`Process 400 starts with the micro-controller 210 in an
`"idle" state until a data write request is received at step 402.
`
`10
`
`6
`For example, the SSD interface 202 receives a data transfer
`command that is then extracted by the command extractor
`212 to determine whether the command is a data write
`request. In the data write request, a logical block address
`5 (LBA) of a data file is provided. Next, at step 404, the micro-
`controller 210 stores particular metadata of the data file into
`the register files 206. For example, LBA range decoder 214
`may need to store starting cluster address/number and total
`number of cluster of the data file.
`Next, the process 400 moves to a decision 406, in which it
`is determined which one of the flash memory array (i.e., SLC
`or MLC) to store the data associated with the received LBA.
`There are a number of alternatives may be used in the present
`invention. Some of the alternative embodiments are shown in
`15 FIGS. 5A-5E and described in the corresponding description
`below.
`If the result of decision 406 is "SLC", then the micro-
`controller 210 maps the received LBA in the address mapping
`memory 220 to a corresponding physical block address of the
`20 SLC flash memory array 226 at step 408. The micro-control-
`ler 210 finally writes the data into the SLC flash memory array
`226 at the physical block address at step 410 before the
`process 400 moves back to the "idle" state. Otherwise, if the
`result of decision 406 is "MLC", then the micro-controller
`25 210 maps the received LBA in the address mapping memory
`220 to a corresponding physical block address of the MLC
`flash memory array 228 at step 412. The micro-controller 210
`writes the data to the physical block address of the MLC flash
`memory array 228 at step 414 before the process 400 goes
`so back to the "idle" state.
`FIGS. 5A-5E are flowcharts showing several alternative
`methods to triage files into SLC or MLC in the process of FIG.
`4. FIG. 5A shows a first alternative exemplary process 520 of
`triaging a data file to determine which one of the flash
`35 memory array (i.e., SLC or MLC) to store into, according to
`one embodiment of the present invention. The first process
`520 represents the decision 406 of the process 400 of FIG. 4.
`The process 520 starts at step 522 by examining particular
`metadata of the data file of a data write request stored in the
`4o register files 206 of the hybrid SSD 200 of FIG. 2. Next, the
`process 520 moves to a decision 523 to determine if the data
`file is a system file or not. If this is a system file (e.g., master
`boot record, file allocation table, partition boot sector, root
`directory, etc.). If "yes", the system file is marked to be stored
`45 in SLC at step 524. Otherwise the data file is a user file. The
`process 520 follows the "no" branch to another decision 525,
`in which it is determine whether the data file is a user file or a
`user directory. If it is a directory, the process 520 goes to step
`524 marking the user directory to be stored in the SLC flash
`50 memory array. If it is not a directory, the process 520 moves
`to step 526 marking the user file to be stored in the MLC flash
`memory array.
`A second alternative process 530 is shown in FIG. 5B.
`Steps 532, 533, 534 and 535 of the second process 530 are
`55 similar to steps 522, 523, 524 and 525 of the first process 520.
`The difference is when the decision 535 becomes "no", or the
`data file in the data write request is a user data file. The
`process 530 moves to another decision 536 to determine
`whether the user file has been accessed more than a threshold.
`6o The threshold may be defined as following examples: 1) the
`user file has been accesses more than a predefined number of
`times; 2) data blocks of the user file are found in the data write
`cache (i.e., have recently been accessed); 3) previously modi-
`fied time of the user file indicates very recent access; or 4) an
`65 access counter of the user file shows a high number of
`accesses (i.e., more than a predefined threshold). Any or all of
`the criteria may be implemented in the micro-controller 210
`
`Micron Ex. 1023, p. 19
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 8,078,794 B2
`
`7
`as logic, firmware or a combination of both. A user config-
`urable table may be implemented to allow user to modify the
`default threshold. In another embodiment, new criterion may
`be de