1 Market and applications for NAND Flash
`memories
`
`Gregory Wong"
`
`1.1 Introduction
`
`In the year 2000, the total semiconductor memory revenues of SRAM, DRAM,
`NOR Flash and NAND Flash memories amounted $46 billion. As the decade
`closed in 2009, total revenues are projected to have declined 8.7% to $42 billion.
`Of the major memory segments, only NAND Flash memory revenues have grown
`in the past decade at a CAGR of almost 50% (see Fig. 1.1).
`Standalone SRAM saw a steady decline (CAGR - 14.5%) throughout the
`decade from $6.5 billion in 2000 to $1.6 billion in 2009 as the L2 cache became
`integrated on the CPU and as low power DRAM replaces SRAM due to its lower
`cost structure.
`After the bursting of the Internet bubble DRAM declined by over 61% in 2001
`before climbing back to $33.8 billion in 2006. The latter half of the decade saw
`excessive oversupply resulting in a decline in revenues to $21 .2 billion in 2009.
`
`Semiconductor Memory Revenues
`
`35,000
`
`30,000
`
`25,000
`
`20,000
`
`15,000
`
`10,000
`
`5,000
`
`$ Million
`
`2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
`
`«“
`
`SRAM -®~DRAM
`
`: NOR -« “NAND
`
`Fig. 1.1. Semiconductor memory revenues (Source: WSTS, Forward Insights)
`
`* Forward Insights, greg@forward-insights.com
`
`R. Micheloni et al., Inside NAND Flash Memories, DOI 10. 1007/97 8-90-481 -943 1-5_1,
`© Springer Science+Business Media B.V. 2010
`
`1
`
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`2
`
`1 Market and applications for NAND Flash memories
`
`The NOR Flash market has shrunk almost 50% from $10.3 billion in 2000 to
`$5.5 billion in 2009 as NAND Flash penetrated the cell phone market in the latter
`half of the decade.
`NAND Flash experienced some volatility during the decade but its extremely
`low cost structure has allowed it to enable new applications such as digital
`photography, portable storage, portable audio and video and multi-functional
`portable devices. NAND Flash started the decade at $370 million and surpassed
`NOR Flash revenues in 2005. It grew 37 times to close out the decade at $13.8
`billion.
`
`1.2 Flash memory architectures
`
`Flash memory was invented by Dr. Fujio Masuoka of Toshiba Corp, in 1984.
`Based on Masuoka’s invention, Intel Corp, commercialised common ground NOR
`Flash memory in 1988 seeing a non-volatile storage medium to storage program
`codes including a PC’s BIOs and firmware for various consumer products. NOR
`Flash was also the basis for the first Flash memory cards and non-volatile solid
`state drives in the 1990s.
`
`BL1
`
`BL2
`
`Array
`Architectures
`
`Bl, I
`WL1 m
`
`BL2
`[ | hJ
`
`WL2
`
`Cells in
`parallel
`
`Cells in ™ a8g|
`series
`
`NAND
`
`NOR
`
`WL1|
`
`WL2|
`
`I
`Virtual
`Ground
`
`I
`
`NROM
`
`AMG
`Alternate
`
`“1
`Triple
`r
`poly
`
`I
`
`ACT
`
`A N D
`
`split9ale contactless
`S
`Ground AG " A N D
`transistor
`
`I
`~
`Common
`Ground
`
`DINOR
`Divided
`Bitline
`NOR
`
`EEPROM Standard
`
`Fig. 1.2. Flash memory array architectures (Source: Forward Insights)
`
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`1 .2 Flash memory architectures
`
`3
`
`Toshiba Corp, introduced NAND Flash memory in 1988 which promised lower
`cost per bit than NOR Flash and faster program and erase throughput. Unlike NOR
`Flash which is organized on a byte or word basis, NAND Flash is organized into
`pages and erased on a block basis. A block consists of 64 or more pages. The
`organization of the NAND Flash is conducive to lower cost per bit but not suitable
`for random access. NAND Flash is therefore employed as a data storage medium
`similar to optical media and hard disk drives.
`The two main array architectures are summarized in Fig. 1.2. NOR Flash
`memory employs a parallel array architecture where each cell may be accessed via
`a contact (Fig. 1.3). The direct cell access is the reason for the superior random
`performance of NOR Flash. The NOR array may be classified into the virtual
`ground or common ground array. A variety of device variations of these two
`classification have been introduced by various companies such as Saifun’s
`NROM, Sharp’s ACT and Renesas’ AND, AG-AND and DINOR, however the
`mainstream NOR Flash is the common ground implementation manufactured by
`the likes of Numonyx, Samsung and Winbond.
`In contrast, the memory cells in NAND Flash are organized serially. Figure 1.4
`shows 32 memory cells sandwiched between two large select transistors and two
`contacts. Random performance is slow due to the fact that there are no contacts
`directly accessing the memory cells. However, because there are only two contacts
`every 32 memory cells, the effective cell size is much smaller than for NOR Flash
`resulting in a smaller chip size and lower cost per bit. The cell size of NAND Flash
`is generally in the 4 F2 range where F is the design rule of the chip. Due to the
`parallel architecture of NOR Flash, its cell size is relatively large at 10 1? .
`
`Fig. 1.3. NOR array architecture (Source: Forward Insights)
`
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`4
`
`1 Market and applications for NAND Flash memories
`
`The device characteristics of NAND and NOR Flash memories are compared in
`Fig. 1.5. NOR Flash exhibits superior random read and write performance versus
`NAND Flash.
`
`GSL WL32 ••• WL2 WL1 BSL
`
`~BL1
`
`'BL2
`
`B L 3
`
`SL
`
`Fig. 1.4. NAND array architecture (Source: Forward Insights)
`
`Flash Memory
`
`random access
`"
`
`serial access
`
`I
`NOR
`
`Access time:
`Random: 60-1 20ns
`page mode/burstmode:
`30ns/1 5ns
`write speed:
`random: 10ps/byte orword
`
`• High Performance optimized
`• fast random read
`• fast random write
`
`NAND
`
`Accessspeed:
`Random: 10-50ps
`serial (page mode): 25-50ns
`write speed:
`random: 200ps/byte
`page: 200ps/page (0,4ps/byte)
`
`• Low Cost
`• small cell size
`• High sustained write
`• page write
`
`Fig. 1.5. NAND versus NOR (Source: Forward Insights)
`
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`1.3 Multi-bit per cell storage
`
`5
`
`However, NAND exhibits fast page writes due to the ability to write 4~8 kB
`simultaneously resulting in very high sequential write throughput. The serial
`architecture and small cell size make NAND Flash optimized for low cost mass
`storage whereas NOR Flash is optimized for performance code storage and
`execution.
`
`1.3 Multi-bit per cell storage
`
`1.3.1 Memories scaling
`
`Where other semiconductor memories were on a 2 year cadence for new process
`technology introduction, NAND Flash memories have historically been on a 1 year
`cadence. This accelerated process scaling resulted in the bit size of SLC NAND
`overtaking MLC NOR in 2005 as shown in Fig. 1.6. MLC NAND is by far the
`lowest cost semiconductor memory with none of the memory technologies even
`close to being cost competitive. This is mainly due to the very small cell size
`combined with multi-level cell capability.
`
`Bit Size Trend
`
`2003
`
`2004
`
`2005
`
`2006
`
`2007
`
`2008
`
`2009
`
`2010
`
`2011
`
`2012
`
`2013
`
`10.0000
`
`1.0000
`
`0.1000
`
`0.0100
`
`0.0010
`
`0.0001
`
`1 s
`
`MLC NAND
`
`oram
`
`«« SRAM
`
`Fig. 1.6. Scaling (Source: Forward Insights)
`
`1.3.2 Multi-level cell concept
`
`Figure 1.7 illustrates the concept of multi-level cell storage in Flash memories.
`Conventional SLC or single-level cell storage distinguishes between a ‘1’ and ‘0’
`by having no charge or charge present on the floating gate of the Flash memory
`cell. By increasing the number of charge or voltage threshold (Vt) levels, more
`
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`6
`
`1 Market and applications for NAND Flash memories
`
`than 1 -bit per cell may be stored. Two bits per cell (MLC) storage is enabled by
`increasing the number of Vt levels to four representing 11, 10, 01 and 00.
`Similarly by increasing the number of voltage threshold levels to eight and 16,
`3-bit per cell and 4-bit per cell storage is enabled.
`The benefit of multi-level cell storage is that storage capacity may be increased
`without a corresponding increase in process complexity. The same fab equipment
`used to manufacture silicon wafers for SLC products may be used to manufacture
`MLC, 3-bit per cell and 4-bit per cell devices. However, multi-level cell storage
`requires accurate placement of the Vt charge levels so that the charge distributions
`don’t overlap as well as accurate sensing of the different charge levels. As the
`number of Vt levels increases the time it takes for accurate programming and
`sensing increases. Additional circuitry and programming algorithms are necessary
`to ameliorate the degradation of the performance and endurance of such devices.
`However in effect, transitioning from SLC to MLC to 3-bit to 4-bit per cell
`technology is equivalent to a partial shrink of the device from one process
`technology generation to the next without additional capital investment.
`
`CG
`
`Substrate
`
`4 bits/cell
`
`3 bits/cell
`
`2 bits/cell
`
`1 bit/cell
`
`Fig. 1.7. Multi-level storage in floating gate NAND Flash memory
`
`1.3.3 NAND scaling
`
`Figure 1.8 shows the bit size trend for SLC, MLC, 8LC (3-bit per cell) and 16LC
`(4-bit per cell) technologies. The bit size is a proxy for the cost. The first MLC
`NAND Flash chip was introduced at the end of 2001 by SanDisk and Toshiba. It
`was a 1Gb chip based on 0.16 pm process technology. Subsequent MLC
`generations were introduced on an almost yearly basis.
`The first commercial production of 8LC began in 2008 also by SanDisk and
`Toshiba. The device, a 16 Gb product based on 56 nm process technology was
`introduced at a process technology one generation behind the mainstream MLC
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`1 3 Multi-bit per cell storage
`
`7
`
`products. As a result, the device was short-lived since the MLC products based on
`43 nm technology were more cost-competitive than the 8LC product. However in
`2010, the cost benefits of 8LC technology are expected to be realized as 8LC is
`manufactured on the same process technology as MLC.
`As with 8LC, 16LC also from SanDisk and Toshiba was introduced in 2009
`on a mature process technology - 43 nm. As a result, the first product - a 64 Gb
`chip - is not cost competitive with the mainstream 32 nm MLC products. It is
`mainly being used as a learning vehicle. Only when 16LC can be manufactured on
`the leading edge process technology will the full cost benefits be realized.
`Note that the cost per bit reduction becomes progressively smaller as one
`transitions from SLC to MLC to 8LC to 16LC. An approximate 40-50% reduction
`can be obtained moving from SLC to MLC but this figure drops to 20% for MLC
`to 8LC and 10% for 8LC to 16LC. As a result, the economic benefit of 16LC may
`not be enough to justify the additional design efforts to implement it.
`One of the main scaling challenges is that the number of electrons stored in the
`floating gate is decreasing significantly with each process generation. This has
`consequences for the sensing of the data value stored and data retention. These
`issues combined with inter-cell interference will make 16LC a less scalable
`technology. To overcome these challenges, innovative programming algorithms
`and signal processing techniques filter the signal from the noise will be required
`for future generations of NAND Flash.
`
`NAND Flash Bit Size Trend
`
`Bit size (pm2)
`
`........... SLC NAND — — MLCNAND ™i&«“8LCNAND
`
`•— *—
`
`16LCNAND
`
`Fig. 1.8. NAND Flash bit size trend (Source: Forward Insights)
`
`1.3.4 Capacity
`
`Until 2006, MLC chip density was doubling every year. This doubling of chip
`density is being extended to 18 months to 2 years as the scaling challenges
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`8
`
`1 Market and applications for NAND Flash memories
`
`increase. As MLC became mainstream, SLC began to lag behind in process
`migration and density transition. For example, it will take 3 years for the transition
`from 8 to 1 6 Gb SLC chips.
`The benefit of 8LC and 16LC is the ability to enable monolithic chip densities
`which would not be possible with SLC and MLC. For example, the first 16LC
`device was the first monolithic chip with a capacity of 64 Gb. It is expected that
`8LC and 16LC will continue to lead the introduction of the highest capacity
`devices (Fig. 1.9).
`
`Density
`
`NAND Flash Density Trend
`
`128Gb
`
`64Gb
`
`32Gb
`
`16Gb
`
`8Gb
`
`4Gb
`
`2Gb
`
`1Gb
`
`512Mb
`
`256Mb
`
`2000
`
`2001
`
`2002 j 2003
`
`2004
`
`2005
`
`2006
`
`2007
`
`2008
`
`2009
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`(mlc
`]sLC
`I--::
`phit/ceiif
`]4bit/cell
`Fig. 1.9. NAND Flash density roadmap (Source: Forward Insights)
`
`1.3.5 Device characteristics
`
`The lower costs associated with multi-level cell technology does not come for
`free. The lower cost comes at the expense of reduced performance and endurance.
`A comparison of the device characteristics for SLC, MLC, 3- and 4-bit per cell is
`summarized in Fig. 1.10. Significant degradation in endurance, retention and write
`performance occurs with increasing number of bits per cell. Read performance and
`operating current are also negatively impacted.
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`1 .3 Multi-bit per cell storage
`
`9
`
`NAND Flash Device Characteristics
`
`Program (MB/s)
`
`1/Op. Current
`
`300*
`
`Read (MB/s)
`
`SLC NAND
`
`MLC NAND
`
`3b/c NAND
`
`4b/c NAND
`
`Density j
`
`Erase (MB/s)
`
`Endurance
`
`Retention
`
`Fig. 1.10. NAND device characteristics (Source: Forward Insights)
`
`Industrial CF
`card
`
`Consumer SSD
`
`Flash cache
`
`Enterprise SSD
`
`Pause TV
`
`hb
`
`DSC
`
`PMP player
`
`GPS
`
`SDHC2
`
`Endurance
`
`Preloaded
`Content
`
`Fig. 1.11. Applications for multi-bit per cell NAND Flash memories (Source: Forward
`Insights)
`
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`1 0
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`1 Market and applications for NAND Flash memories
`
`Of course, the trade-off is higher capacity and lower cost per bit. Erase
`performance actually improves due to the larger block size.
`The implication of the disparate device characteristics is that the applications
`usage model will dictate the type of devices that will be used.
`Figure 1.11 provides a simplified overview of the applications based on two
`key parameters - endurance and write speed. Applications with less demanding
`endurance and write performance requirements are better suited for devices with
`multi-bit per cell storage. Content storage and archiving may be facilitated by
`4-bit per cell devices. Consumer applications that are largely read intensive such
`as MP3/PMP players, Flash memory cards, personal navigation devices can use
`3-bit per cell devices. MLC may be found in consumer and netbook solid state
`drives and SLC for solid state drives in the enterprise. However, for certain enter
`prise applications especially read intensive with low duty cycles, MLC may be
`sufficient.
`
`1.4 Market and applications
`
`1.4.1 Removable portable storage
`
`The application which triggered the rise of NAND Flash was digital photography
`and digital storage. The first Flash memory card format, Compact Flash I
`incorporated NOR Flash at its inception in 1 994. The SmartMedia card introduced
`in 1995 was the first removable media format to incorporate NAND Flash
`followed by the MultiMedia Card in 1997, Memory Stick in 1998, Secure Digital
`in 1999, and xD-Picture Card in 2002. Miniaturized “mini” and “micro” versions
`of these cards have been subsequently introduced.
`Figure 1.12 shows the plethora of Flash memoty card form factors that have
`replaced analog film. In fact, Flash memory cards store not only images but also
`audio and video enabling portable transport of files from one device to another.
`USB Flash drives introduced in 2000 by Trek and IBM have driven the floppy disk
`to extinction.
`
`1 .4.2 Embedded storage
`
`NAND Flash is employed for code/data storage or data storage in a variety of
`portable and mobile applications such as cellular phones, MP3/PMP players,
`digital video camcorders and personal navigation devices. NAND Flash may be
`embedded in applications in several ways.
`Raw NAND - NAND Flash chips are soldered onto the PCB of the device with
`the host-side handling the Flash translation layer (FTL), bad block management
`and error correction (ECC). For example, MP3/PMP players employ a Flash
`controller to manage the raw NAND.
`
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`

`1 .4 Market and applications
`
`1 1
`
`Flash
`
`USB
`
`Secure
`Digital
`
`MQn
`'
`xD
`Memory
`Stick
`
`MMC
`
`SmartMedia
`Mini MMC
`jS9 Mini SD
`-. ■ t
`"...
`-
`
`M
`
`MgHSSSI
`etBsMil
`?-FWM
`
`Fig. 1.12. Removable portable storage
`
`NAND with on-chip controller - The NAND Flash devices are used for code
`and data storage with only the Flash translation layer managed by the host. In some
`instances, these devices such as ONENAND from Samsung, Toshiba and Numonyx
`and mDOC (mobile Disk-on-Chip) from SanDisk come with a NOR Flash inter
`face and act as a replacement for the NOR Flash.
`Multi-chip Package (MCP) - The NAND Flash is combined with both a NOR
`Flash and low power DRAM or just a DRAM for code and data storage. MCPs are
`primarily used in mobile phones.
`An overview of memory architectures for different mobile phones is presented
`in Fig. 1.13. The architectures depend on the functionality of the phones.
`The primary function of entry level mobile phones is voice communications.
`The phones are generally capable of SMS and basic web browsing. As a result,
`large memory capacity is not a requirement. Entry level mobile phones employ a
`XI P (execute in place) architecture whereby the program code is stored and
`directly executed from the NOR Flash and pseudo-SRAM is used as the working
`memory. This memory system
`is cost optimized solution for small memory
`densities and low power.
`Feature phones provide voice, MMS, camera, audio, video and web browsing
`functionality. Higher capacity for data storage
`is therefore necessary. Feature
`phones combine three memories - NOR Flash for code execution, NAND Flash for
`data storage and RAM as a working memory. This architecture is essentially a XIP
`with additional NAND Flash for data storage.
`
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`12
`
`1 Market and applications for NAND Flash memories
`
`Smartphones have morphed into convergence devices. In addition to the feature
`phone capabilities, these devices are designed for multi-tasking - running more
`than one application at the same time, e-mailing and infotainment.
`The store and download (SnD) architecture used in smartphones employs a PC-
`like approach. Instead of storing in NOR Flash, the code is stored in NAND Flash,
`copied into DRAM and executed from DRAM. In this scenario, code has to be
`swapped in and out of the DRAM for execution. Since the RAM has to act as both
`a code execution and work memory, the RAM capacity is larger than the RAM
`required in the NOR/NAND/RAM implementation in feature phones. Because of
`the very low cost per bit of NAND Flash, this architecture is cost optimized for
`medium/large memory capacity requirements at the expense of higher power
`consumption and longer boot time than the XIP implementation.
`
`Basic
`(Voice) 2G
`
`MCU
`
`Feature
`2.5G
`
`MCU
`
`Smartphone
`3G
`
`MCU
`
`Code
`
`NOR
`
`RAM
`
`NOR
`
`NAND
`
`RAM
`
`RAM
`
`Fig. 1.13. Memory system architectures in mobile phones
`
`XI P Architecture
`
`SnD Architecture
`
`NOR
`
`Code
`
`SRAM
`
`Work
`
`• Copy OS kernel,
`program
`into DRAM
`
`NAND
`
`Code
`
`DRAM
`Code
`Work
`
`• Execute in
`DRAM
`
`• Program execution in NOR
`
`•Demand paging
`•Additional RAM overhead
`
`Fig. 1.14. Store and download versus XIP architecture
`
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`1 .4 Market and applications
`
`1 3
`
`Figure 1.14 contrasts the SnD and XIP architectures.
`Managed NAND solutions ~ NAND Flash device ECC requirements and in
`some cases page sizes and block sizes are changing with each new technology
`generation. Instead of having to continually update the host firmware to manage
`these details, these changes are managed within the device by combining raw
`NAND and a controller in a package. All the FTL, bad block management and
`ECC are handled within the package allowing the host to perform only a
`simplified read/write to the device. The host side requires a basic driver to inter
`face with the managed NAND device typically using a eMMC or eSD protocol.
`The raw NAND and managed NAND implementations are illustrated in Fig. 1.15.
`
`Raw NAND
`
`Processor
`
`Managed NAND
`
`Processor
`
`Managed NAND ; -
`
`Fig. 1.15. Managed NAND versus raw NAND (Source: Micron Technology)
`
`1.4.3 Solid state drives
`
`The first SSDs pioneered by StorageTek in 1978 were RAM-based SSDs. It
`wasn’t until late 1980s and early 1990s when the first Flash-based SSDs were
`developed. Western Digital demonstrated a 2.5" NAND Flash SSD in 1989,
`however the main promoters of Flash-based SSDs, SanDisk and Intel, based their
`SSDs on NOR Flash technology in the early 1990s. Due to the higher cost of NOR
`Flash versus DRAM, Flash-based SSDs were relegated to niche markets.
`However, the remarkable and rapid price decline of NAND Flash memory in
`recent years which has driven analog film and the floppy disk to extinction is now
`enabling NAND Flash memory to penetrate the realm of hard disk drives (HDDs).
`Solid state drives (SSDs) offer the promise of significantly better performance and
`reliability due to the lack of mechanical parts.
`
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`14
`
`1 Market and applications for NAND Flash memories
`
`Platter
`
`DRAM Controller
`
`Connector
`
`Spine
`
`ActUc
`Arr
`
`ActUc
`
`Head
`
`/Connector
`
`Flash Memory
`
`Fig. 1.16. Solid state drive versus hard disk drive (Source: Toshiba Corp., Forward
`Insights)
`
`Figure 1.16 details the major components of an SSD and HDD. The HDD,
`being based on storage in a spinning magnetic platter, requires an actuator and
`actuator arm to move the head to the appropriate sector to be read or written. This
`movement of the read head results in extremely long latencies in the milliseconds
`and a DRAM buffer is used to hide the seek time. The HDD controller,
`particularly if it is a system-on-chip, incorporates the processor, servo control
`logic, interface, error correction code, disk sequencer and buffer controller.
`In contrast, the SSD contains no mechanical parts and consists of a few major
`components: NAND Flash memory, SSD controller, connector, DRAM, PCB and
`passives. In addition, because of the small size of NAND Flash memory, the SSD
`form factor is not limited to standard 1.8, 2.5 or 3.5" HDD form factors but can
`also come in module form.
`NAND-based SSDs started out in industrial and military where ruggedness and
`reliability are a priority. In 2006, the first SSD for personal computers was
`introduced followed by SSDs for enterprise computing.
`Table 1.1 summarizes the NAND Flash/SSD usage models in the different
`market segments. There are several ways NAND Flash or SSDs may utilized.
`Firstly, it can act as an alternate storage device, in many cases replacing a HDD
`for latency or reliability improvement and power consumption reduction. An
`optimized OS or file-system is required to obtain the full benefits of the SSD.
`Secondly, the SSD may act as an I/O accelerator. I/O acceleration is primarily
`used in the enterprise computing environment. A software driver is required for
`this approach.
`Thirdly, the SSD/NAND Flash may be part of the tiered system memory and
`replace part of the DRAM. Due to the better economics of NAND Flash versus
`DRAM, this allows an increase in system memory storage capacity with the
`
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`1 .4 Market and applications
`
`1 5
`
`benefits of reduced power consumption. To manage this tiered system memory,
`the kernel memory manager needs to be designed to manage the Flash memory.
`A comparison of SSD and HDD in PCs (Fig. 1.17) shows that SSDs are
`superior to HDDs in all aspects except for cost and capacity. The cost and capacity
`are related since the major impediment to higher SSD capacities is the high cost
`per gigabyte.
`
`Table 1.1. NAND usage model
`
`NAND Usage Model
`Alternate Storage
`I/O Accelerator
`Extended System Memory
`
`Co nsumer Enterprise
`“V
`
`In dustrial Mil ita ry
`~ "7
`~
`
`a/
`
`7
`7
`
`In the enterprise space, high throughput and low access latency are critical.
`Enterprise HDDs employ several techniques to improve system throughput and
`decrease the access latency. High performance 15 k rptn HDDs may be organized
`in a RAID configuration with the data being striped across multiple disks thereby
`increasing the bandwidth of the total system. Adding HDDs increase system
`bandwidth but result in increased space, power and cooling requirements.
`“Short-stroking” the HDDs whereby data is placed on the outer tracks of the
`disk to reduce the seek time of the mechanical heads reduces system access
`latencies. However, this entails that only part of the HDD is being used to achieve
`the required performance resulting in excess storage capacity than would other
`wise be necessary. As illustrated in Fig. 1.18, one SSD can replace several striped,
`short-stroked HDDs.
`
`SSDs vs. HDDs in PCs - Performance Characteristics
`
`Capacity
`
`Small siz<
`
`.ow$/GB
`
`Low weight*
`
`’ 0(
`
`0
`
`Read
`
`mlcssd
`
`—
`
`HDD
`
`Low noise
`
`Write
`
`Operating
`shock
`
`MTBF
`
`Low Op.
`power
`
`Fig. 1.17. 2.5" SSDs versus HDDs in PCs - performance characteristics (Source: Forward
`Insights)
`
`Micron Ex. 1019, p. 15
`Micron v. Vervain
`IPR2021-01547
`
`

`

`1 6
`
`1 Market and applications for NAND Flash memories
`
`Hard Disk Drive Storage Array
`
`Solid State Drive
`
`Fig. 1.18. Enterprise SSD value proposition
`
`Figure 1,19 shows that although on a price per GB basis, HDDs are far superior
`to SSDs, the cost for an HDD system to obtain comparable metrics in terms of
`$/IOPS, IOPS/GB or 1OPS/W is far higher than for SSDs, This is just the storage
`comparison. When the total system is considered, far fewer SSDs will be required
`for a given performance than HDDs. If the maintenance, power and space savings
`are included, the economics of using SSDs are even more attractive.
`
`SPECIFICATION
`Capacity (GB)
`Price ($)
`Performance
`Random
`Read
`Write
`Power
`Operating mode
`$ / G B
`$ / IOPS
`Read
`Write
`IOPS / GB
`Read
`Write
`IOPS / w
`Read
`Write
`1 STEC ZeuslOPS
`
`Enterprise Class SSD 1
`146
`12,500
`
`Enterprise Class HDD
`73
`389
`
`52,000 IOPS
`18,000 IOPS
`
`8.4W
`85.62
`
`0.24
`0.69
`
`356
`123
`
`6,190
`2,143
`
`300 IOPS (est)
`300 IOPS (est)
`
`10-12W
`5.33
`
`1.30
`1.30
`
`4
`4
`
`27
`27
`
`Delta
`100%
`3113%
`
`17233%
`5900%
`
`-24%
`1607%
`
`-81%
`-46%
`
`8567%
`2900%
`
`22598%
`7757%
`
`Fig. 1.19. Enterprise SSD versus HDD key metrics
`
`Micron Ex. 1019, p. 16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`1.5 Market outlook
`
`17
`
`1.5 Market outlook
`
`In the early years, the NAND Flash market was driven by removable storage
`applications such as the Flash memory card following by the USB Flash drive. In
`2004, NAND Flash began to replace 1" HDD in MP3 players led by Apple’s iPod
`Mini. The era of high capacity embedded Flash storage in mobile phones began
`with the 4 and 8 GB iPhone from Apple Corp, in 2007. Prior to 2007, smartphones
`only had relatively low density Flash on-board and in some models, high density
`storage was supplemented via a slot which allowed the insertion of a Flash memory
`card. The iPhone is not just a phone but a convergence device incorporating camera,
`video, audio and gaming functionalities supported by content and applications
`from an online store.
`Following the iPhone’s lead, smartphone from other handset manufacturers are
`increasing the embedded Flash memory storage of their devices and mobile market
`is forecast to become the major consumer of NAND Flash gigabytes within the
`next 5 years.
`The next frontier after consumer and communications is computing. NAND
`Flash-based SSDs are expected
`to become a new driver of NAND Flash bit
`consumption beyond 2012 driven by adoption of SSDs in mainstream consumer
`PCs.
`The NAND Flash industry’s historical triple digit bit growth ended in 2009 as a
`result of the global economic downturn. As technology transitions slow down, bit
`growth is forecast to experience a more moderate 69% CAGR from 2007 to 2016
`(Figs. 1.20 and 1.21).
`
`NAND Flash Applications Demand
`
`Mobile Phone
`
`USB Flash Drive
`
`2008
`
`2009
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`2015
`
`2016
`
`100%
`
`90%
`
`80%
`
`60%
`
`50%
`
`40%
`
`30%
`
`20%
`
`10%
`
`0%
`2007
`
`SI
`
`Fig. 1.20. NAND Flash applications demand (% GB) (Source: Forward Insights)
`
`Micron Ex. 1019, p. 17
`Micron v. Vervain
`IPR2021-01547
`
`

`

`---
`Zzxx-/Z
`
`1 8
`
`1 Market and applications for NAND Flash memories
`
`NAND Flash Applications Demand
`-T ------------------------- ----------------------------------------------------------
`
`250,000
`
`200,000
`
`---------------------
`
`150,000
`
`100,000
`
`50,000
`
`MillionGB
`
`2006
`
`2007
`
`2008
`
`2009
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`2015
`
`2016
`
`Fig. 1.21. NAND Flash applications demand (Source: Forward Insights)
`
`NAND Flash memory is facing serious scaling issues and it is within the next
`5 years, that a successor technology is expected take the reins and fuel the insatiable
`storage demands of emerging applications.
`
`Micron Ex. 1019, p. 18
`Micron v. Vervain
`IPR2021-01547
`
`

`

`2 NAND overview: from memory to systems
`
`1 2
`
`7?. Micheloni\ A. MarelIF and S. Commodaro
`
`3
`
`2.1 Introduction
`
`It was in 1965, just after the invention of the bipolar transistor by W. Shockley,
`W. Brattain and J. Bardeen, that Gordon Moore, co-founder of Intel, observed that
`the number of transistors per square centimeter in a microchip doubled every year.
`Moore thought that such trend would have proven true for the years to come as
`well, and indeed in the following years the density of active components in an
`integrated circuit kept on doubling every 18 months. For example, in the 18
`months that elapsed between the Pentium processor 1.3 and the Pentium-4, the
`number of transistors grew from 28 to 55 million.
`Today, a standard desktop PC has processors whose operating frequency is in
`the order of some gigahertz, while its memory can store as much information as
`terabytes.
`In this scenario, a meaningful portion of the devices produced is represented by
`memories, one of the key components of any electronic systems.
`Semiconductor memories can be divided into two major categories: RAM,
`acronym for Random Access Memories, and ROM, acronym for Read Only
`Memories: RAM loses its content when power supply is switched off, while ROM
`virtually holds it forever. A third category lies in between, i.e. NVM, acronym for
`Non-Volatile Memories, whose content can be electrically altered but it is also
`preserved when power supply is switched off. These are more flexible than the
`original ROM, whose content is defined during manufacturing and cannot be
`changed by the consumer anymore.
`The history of non-volatile memories began in the 1970s, with the introduction
`of the first EPROM memory (Erasable Programmable Read Only Memory), Since
`then, non-volatile memories have always been considered one of the most
`important families of semiconductors and, up to the 1990s, their interest was tied
`up more to their role as a product of development for new technologies than to
`their economic value. Since the early 1990s, with the introduction of non-volatile
`Flash memories into portable products like mobile phones, palmtop, camcorders,
`digital cameras and so on, the market of these memories has experienced a
`stunning increase.
`
`1 Integrated Device Technology, rino.micheloni@ieee.org
`2 Integrated Device Technology, alessiamarelli@gmail.com
`3 Pegasus MicroDesign, stefano_commodaro@yahoo.it
`
`R. Micheloni et al., Inside NAND Flash Memories, DOI 10.1007/978-90-481-9431-5_2,
`© Springer Science+Business Media B.V. 2010
`
`19
`
`Micron Ex. 1019, p. 19
`Micron v. Vervain
`IPR2021-01547
`
`

`

`20
`
`2 NAND overview: from memory to systems
`
`The most popular Flash memory cell is based on the Floating Gate (FG)
`technology, whose cross section is shown in Fig. 2.1. A MOS transistor is built
`with two overlapping gates rather than a single one: the first one is completely
`surrounded by oxide, while the second one is contacted to form the gate terminal.
`The isolated gate constitutes an excellent “trap” for electrons, which guarantees
`charge retention for years. The operations performed to inject and remove electrons
`from the isolated gate are called program and erase, respectively. These operations
`modify the threshold voltage VTH of the memory cell, which is a special type of
`MOS transistor. Applying a fixed voltage to cell’s terminals, it is then possible to
`discriminate two storage levels: when the gate voltage is higher than the cell’s
`VTHs the cell is on (“1”), otherwise it is off (“0”).
`It is worth mentioning that, due to floating gate scalability reasons, charge trap
`memories are gaining more and more attention and they are described in Chap. 5,
`together with their 3D evolution.
`
`floating gate (FG)
`
`control gate (CG)
`
`Drain (D)
`
`substrate
`
`electrons
`
`D
`
`S
`
`(a)
`(b)
`Fig. 2.1. (a) Floating gate memory cell and (b) its schematic symbol
`
`2.2 NAND memory
`
`2.2.1 Array
`
`The memory cells are packed to form a matrix in order to optimize silicon area
`occupation. Depending on how the cells are organized in the matr