(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2009/0327591 A1
`Moshayedi
`(43) Pub. Date:
`Dec. 31, 2009
`
`US 20090327591A1
`
`(54) SLC-MLC COMBINATION FLASH STORAGE
`DEVICE
`(75) Inventor:
`
`Mark Moshayedi, Newport Coast,
`CA (US)
`Correspondence Address:
`MCDERMOTT WILL & EMERY LLP
`18191 VON KARMANAVE., SUITE 500
`IRVINE, CA 926.12-7108 (US)
`
`(73) Assignee:
`(21) Appl. No.:
`
`1-1.
`22) Filed:
`(22) File
`
`STEC, INC., Santa Ana, CA (US)
`12A492,113
`9
`Jun. 25, 2009
`ll. A5.
`
`O
`O
`Related U.S. Application Data
`(60) Provisional application No. 61/075,709, filed on Jun.
`25, 2008.
`
`Publication Classification
`
`(51) Int. Cl.
`2006.O1
`G06F 12/00
`30.8
`G06F 2/02
`(52) U.S. Cl. ........... 711/103; 711/E12.001: 711/E12.008
`(57)
`ABSTRACT
`Flash memory drives and related methods are disclosed that
`operate to keep frequently written data, which results in fre
`quently erased blocks, in SLC flash, and relatively static data
`in MLC flash. A flash drive according to the present disclo
`sure keeps track of the number of times that data for each
`logical block address (LBA) has been written to the flash
`memory, and determines whether to store newly received data
`associated with a particular LBA in SLC flash or in MLC flash
`depending on the number of writes that have occurred for that
`particular LBA. For each logical block sent to the flash drive,
`a comparison is made of the write count of the associated
`LBA to a threshold. If the write count is above the threshold,
`the logical block is written to SLC flash. If the write count is
`below the threshold, the logical block is written to MLC flash.
`
`
`
`
`
`soa
`
`
`
`Free Page Point
`
`a
`note
`its
`end
`
`Relative Physical Unit No in
`the channel
`
`
`
`
`
`so
`1000000(b)
`
`2.
`
`0111111.0000001(b)
`0000000(b)
`
`
`
`
`
`This block is
`e moved from MLC
`
`Block is full
`free page number
`
`unit need Screen Of
`system unit
`
`
`
`The relative physical unit number
`of virtual unit in the channel
`
`Micron Ex. 1012, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 1 of 9
`
`US 2009/0327591 A1
`
`FIG. 1
`
`1 OO
`
`I/F
`
`104
`
`102
`Controller
`
`- - - - - - - -
`AUX
`POWER -110
`- - - - - - - - J
`
`- - - - - - -
`106
`N
`DRAM
`-------
`
`10,
`
`114(O)
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`
`
`114
`
`- - - - - - -
`
`MLC
`
`F - - - - - - -
`
`MLC
`
`MLC
`
`Micron Ex. 1012, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 2 of 9
`
`US 2009/0327591 A1
`
`s
`
`
`
`Micron Ex. 1012, p. 3
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 3 of 9
`
`US 2009/0327591 A1
`
`| || || ||
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`(q)1000000'||||||0
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`
`
`Micron Ex. 1012, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 4 of 9
`
`US 2009/0327591 A1
`
`FIG. 4
`
`400 Ya
`
`
`
`PUFO
`
`K9K8GO8
`PU#1
`has
`8192 blocks=4096 unitsPU#2
`PU#3
`
`4013 data units
`
`Free block
`
`Free block
`
`3 free units for data Copy
`
`Free block
`Spare for defect
`block
`
`Reserved 2%
`(80 units for defect replacement)
`PU#4094
`PU4095 Spare for defect-1
`
`Micron Ex. 1012, p. 5
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 5 of 9
`
`US 2009/0327591 A1
`
`FIG. 5
`
`500 \
`PUE4096
`K9G8G08
`PUFA097
`has
`8192 blockSF4096 units PUAO98
`PU#4099 |
`
`Chip 1 at channel O
`
`4096 data units
`
`Chip 2 at
`channel O
`
`Chip 3 at
`channel O
`
`PU16395
`PU16396
`PU#16397
`PU#16398
`
`Chip 4 at channel 0
`
`3772 data units
`
`
`
`
`
`Free unit
`Free unit
`Free unit
`Spare for defect
`unit
`
`
`
`PU#20478
`
`PU#20479
`
`
`
`Spare for defect
`unit
`System unit
`
`3 free units for data copy
`
`Reserved 2%
`(320 units for defect
`replacement)
`
`Micron Ex. 1012, p. 6
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 6 of 9
`
`US 2009/0327591 A1
`
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`Micron Ex. 1012, p. 7
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 7 of 9
`
`US 2009/0327591 A1
`
`700
`
`FIG. 7A
`
`Receiving a write command dispatched from a host
`
`
`
`
`
`
`
`
`
`Caculating the channel number, virtual unit number, virtual page
`number, and area number for a page according to the LBA address
`
`Transferring the date from host to buffer
`
`y
`Finding the specified location that the host is attempting to write
`data into by checking the V2P table and replacement unit table
`
`Reading the redundancy of the specific block location can be to
`check the erase count of the block
`
`If the erase count is over a specified number (e.g., 1000) for MLC
`flash blocks, then processing MLC flash data swap to SLC flash
`
`
`
`Continued
`
`702
`
`704
`
`706
`
`708
`
`710
`
`712
`
`Micron Ex. 1012, p. 8
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 8 of 9
`
`US 2009/0327591 A1
`
`FIG. 7B
`
`Y
`
`Copying the date from the buffer into flash, and appropriately
`marking the free unit (e.g., with "VU")
`
`If the target unit is "dirty', finding a free unit can from a SLC or
`MLC area based on the selected block address
`
`Writing a NTU mark to the redundancy area of the selected block
`
`Transferring the data from the selected block to the free block
`
`Copying the data from the buffer to the free block
`
`Erasing the selected block and writing the erase count to the
`redundancy area when the erase is done
`
`END
`
`
`
`
`
`
`
`714
`
`716
`
`718
`
`720
`
`722
`
`724
`
`Micron Ex. 1012, p. 9
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 31, 2009 Sheet 9 of 9
`
`US 2009/0327591 A1
`
`800
`
`
`
`
`
`
`
`FIG. 8
`
`Copying the MLC block data (for a MLC block with erase count
`= 500) to a free block of SLC
`
`Erasing the MLC block, and updating and adding the new erase to
`the free block of MLC
`
`Selecting the smallest value of erase count in the SLC area
`
`Copying the SLC block data to the free block of MLC
`
`Erasing the SLC block, and updating and adding a new erase
`count to the free block of SLC
`
`Performing wear leveling for the MLC area based on the erase
`count of every block
`
`End
`
`802
`
`804
`
`806
`
`808
`
`810
`
`812
`
`Micron Ex. 1012, p. 10
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2009/0327591 A1
`
`Dec. 31, 2009
`
`SLC-MILC COMBINATION FLASH STORAGE
`DEVICE
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`0001. The present application claims the benefit of priority
`under 35 U.S.C. S 119 from U.S. Provisional Patent Applica
`tion Ser. No. 61/075,709, entitled “SOLID STATE DEVICE,
`filed on Jun. 25, 2008, the disclosure of which is hereby
`incorporated by reference in its entirety for all purposes.
`
`BACKGROUND
`0002 Flash memory is an improved form of Electrically
`Erasable Programmable Read-Only Memory (EEPROM).
`Traditional EEPROM devices are only capable of erasing or
`writing one memory location at a time. In contrast, flash
`memory allows multiple memory locations to be erased or
`written in one programming operation. Flash memory can
`thus operate at higher effective speeds than traditional
`EEPROM.
`0003 Flash memory enjoys a number of advantages over
`other storage devices. It generally offers faster read access
`times and better shock resistance than a hard disk drive
`(HDD). Unlike dynamic random access memory (DRAM),
`flash memory is non-volatile, meaning that data stored in a
`flash storage device is not lost when power to the device is
`removed. For this reason, a flash memory device is frequently
`referred to as a flash storage device, to differentiate it from
`Volatile forms of memory. These advantages, and others, may
`explain the increasing popularity of flash memory for storage
`applications in devices Such as memory cards, USB flash
`drives, mobile phones, digital cameras, mass storage devices,
`MP3 players and the like.
`0004. In addition to non-volatile flash memory, many flash
`storage devices include a controller and Volatile memory,
`such as DRAM, which are used in the management of the read
`and write operations of the flash storage devices and in the
`communication between the flash storage devices and the
`host devices to which they are connected. For example,
`DRAM may contain an addressing table correlating logical
`addresses used by the host device with physical addresses in
`the non-volatile flash memory where data is stored.
`0005 Flash memory is organized into a number of blocks
`which are each divided into a number of smaller data units
`that may be referred to as segments, pages, logical blocks, etc.
`For example, each block may contain 128Kbytes divided into
`324. Kbyte segments. Flash memory writes individual seg
`ments into flash memory, but can only erase entire blocks.
`0006. A host system sends a logical block of data (e.g.,
`4K) addressed by a logical blockaddress (“LBA) to the flash
`drive for storage. The flash drive maps the LBA to a location
`of a segment within a physical block in the flash memory and
`writes the logical block of data to that location. When new
`data is written to that same LBA, the flash drive remaps the
`LBA to a new location and marks the previous location as
`invalid. Eventually, blocks containing invalid segments are
`erased and made available for new write operations. As noted
`previously, flash memory can be limited in the number of
`times it can be erased before failure occurs. SLC flash can be
`erased approximately 100 times more often than MLC flash
`before the same number of defects (e.g., unwriteable blocks)
`occurs. SLC flash, however, is significantly more expensive
`than MLC flash.
`
`0007 Flash memory is limited in the number of times it
`can be erased before failure occurs. For example, single level
`cell (“SLC) flash may have an endurance life of 100K write
`erase cycles before the wear begins to deteriorate the integrity
`of the storage. SLC flash can be erased around 100 times more
`often than MLC flash. While SLC flash can have a much
`greater endurance life than MLC flash, SLC flash is signifi
`cantly more expensive than MLC flash. Accordingly, there is
`a need for improved techniques for more efficiently utilizing
`MLC and SLC flash memory for data storage.
`
`SUMMARY
`
`0008 Aspects and embodiments of the of the present dis
`closure address problems previously noted by providing for
`the allocation and storage of data received from a host across
`multiple channels of flash memory, where each channel
`includes both a single level cell (SLC) flash and multi-level
`cell (MLC) flash memory. The resulting memory capabilities
`can accommodate application memory needs at desirable
`prices, in addition to increasing read/write performance.
`0009 Embodiments of the present disclosure are directed
`to flash memory drives and related methods that operate to
`keep frequently written data, which results in frequently
`erased blocks, in SLC flash, and relatively static data in MLC
`flash. A flash drive according to the present disclosure keeps
`track of the number of times that data for each logical block
`address (LBA) has been written to the flash memory, and
`determines whether to store newly received data associated
`with a particular LBA in SLC flash or in MLC flash depending
`on the number of writes that have occurred for that particular
`LBA. For each logical block sent to the flash drive by the host,
`the host compares the write count of the associated LBA
`against a threshold. If the write count is above the threshold,
`the logical block is written to SLC flash. If the write count is
`below the threshold, the logical block is written to MLC flash.
`The threshold may be set at 0 initially, resulting in all data
`being written to SLC flash, and then increased as needed.
`When SLC flash has reached a designated capacity, blocks
`with the lowest write counts are moved down to MLC flash.
`The flash drive uses sets of link lists to keep track of a number
`of metrics used to manage the flash memory. A set is kept for
`both the SLC flash and the MLC flash in each channel of the
`flash drive.
`0010. It is to be understood that both the foregoing sum
`mary of the invention and the following detailed description
`are exemplary and explanatory and are intended to provide
`further explanation of the invention as claimed.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`0011. The accompanying drawings, which are included to
`provide further understanding of the invention and are incor
`porated in and constitute a part of this specification, illustrate
`embodiments of the invention and together with the descrip
`tion serve to explain the principles of the invention. In the
`drawings:
`0012 FIG. 1 depicts a schematic view of a flash storage
`system in accordance with exemplary embodiments of the
`present disclosure;
`0013 FIG. 2 depicts a schematic view of a controller
`architecture, in accordance with exemplary embodiments of
`the present disclosure;
`
`Micron Ex. 1012, p. 11
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2009/0327591 A1
`
`Dec. 31, 2009
`
`0014 FIG.3 depicts a schematic view of a 32 bit virtual
`to-physical (“V2P) entry for a V2Ptable, in accordance with
`exemplary embodiments of the of the present disclosure;
`0015 FIG. 4 depicts a schematic view of a SLC data
`structure outline, in accordance with exemplary embodi
`ments of the of the present disclosure;
`0016 FIG. 5 depicts a schematic view of a MLC data
`structure outline, in accordance with exemplary embodi
`ments of the of the present disclosure;
`0017 FIG. 6 depicts a schematic view of data structure
`within NAND flash, in accordance with exemplary embodi
`ments of the of the present disclosure;
`0018 FIGS. 7A-7B depict a method of writing to flash
`memory, in accordance with exemplary embodiments of the
`present disclosure; and
`0019 FIG. 8 depicts a method of swapping data between
`MLC flash and SLC flash, in accordance with exemplary
`embodiments of the present disclosure.
`0020 While certain embodiments are depicted in the
`drawings, one skilled in the art will appreciate that the
`embodiments depicted are illustrative and that variations of
`those shown, as well as other embodiments described herein,
`may be envisioned and practiced within the scope of the
`present disclosure. Accordingly, the drawings and detailed
`description are to be regarded as illustrative in nature and not
`as restrictive.
`
`DETAILED DESCRIPTION
`0021. In the following detailed description, numerous spe
`cific details are set forth to provide a full understanding of
`aspects and embodiments of the present disclosure. It will be
`apparent, however, to one ordinarily skilled in the art that
`aspects and embodiments of the present disclosure may be
`practiced without some of these specific details. In other
`instances, well-known structures and techniques have not
`been shown in detail to for ease in comprehension.
`0022. As was noted previously, SLC flash has a relatively
`high endurance (e.g. more than 100K erase cycles with 10
`year data retention) compared to MLC flash (e.g., having 1 K
`erase cycle endurance with 10 year data retention). For may
`typical user software applications, there may be 80% of asso
`ciated memory storage that is installed for the application
`program to run, while only 20% of the storage utilized is for
`user data that is changed often. As the price of SLC flash
`relatively high, e.g., almost double the cost of MLC, flash
`memory systems can be overly expensive if they consist
`entirely of SLC flash. On the other hand, a SSD drive that
`contains all MLC flash, can accordingly have reliability
`issues for intensive usage. To meet the needs of real word
`applications at a reasonable cost, embodiments of the present
`disclosure provide for the concurrent use of SLC flash and
`MLC flash for memory storage.
`0023. An aspect of the present disclosure is directed to
`solid state drives (SSD) that utilize flash memory that com
`bine both SLC and MLC flash to provide high endurance of
`SLC flash for frequently written (or updated) data while uti
`lizing lower cost MLC flash for data that are written (or
`updated) less frequently. Embodiments of the present disclo
`sure can include SSDs that contain multiple channels of flash
`memory to speed up the read/write performance.
`0024. A flash drive according to the present disclosure
`keeps track of the number of times that data for each logical
`block address (LBA) has been written to the flash memory,
`and determines whether to store newly received data associ
`
`ated with a particular LBA in SLC flash or in MLC flash,
`depending on the number of writes that have occurred for that
`particular LBA. For each logical block sent to the flash drive
`by the host, the host compares the write count of the associ
`ated LBA against a threshold. If the write count is above the
`threshold, the logical block is written to SLC flash. If the write
`count is below the threshold, the logical block is written to
`MLC flash. The threshold may be set at 0 initially, resulting in
`all data being written to SLC flash, and then increased as
`needed. When SLC flash has reached a designated capacity,
`blocks with the lowest write counts are moved down to MLC
`flash. The flash drive uses sets of link lists to keep track of a
`number of metrics used to manage the flash memory. A set is
`kept for both the SLC flash and the MLC flash in each channel
`of the flash drive.
`0025 FIG. 1 is a block diagram of a multiple-channel flash
`storage device or SSD 100 according to exemplary embodi
`ments of the present disclosure. The multiple-channel flash
`storage device 100 can include a controller 102 that is con
`nected by way of an interface (I/F) 104 to a host system (not
`shown), and an array of flash memory 108. The interface 104
`interfaces the flash storage device 100 to a host system, and
`allows the flash storage device 100 to receive data (e.g., to be
`written into the flash array 108) from the host system and send
`data to the host system (e.g., data read from the flash array
`108). The controller 102 controls operations of the flash stor
`age device 10, as discussed further below. It should be noted
`that, while four channels are indicated (0-3), the number of
`channels “N” is arbitrary and can be selected as desired. For
`example, exemplary embodiments, can include 4, 8, or 16,
`etc. channels. Various other number of channels may be used.
`(0026. Each flash memory channel 108(0) to 108(N) can
`included or be distributed over multiple flash chips (e.g.,
`NAND flash) that can include both SLC and MLC flash. Each
`of the N channels may be implemented using one or more
`physical I/O buses coupled between the controller 102 and
`respective the flash channel 108(0)-108(N). Each of the N
`channels allows the controller 102 to send read, write and/or
`erase commands to the corresponding flash memory 108(0)-
`108(N).
`(0027. The data stored in the memory channels 108(0)-108
`(N) can be divided into logical data blocks. Each data block
`may be further divided into data segments. While the term
`“data block” is used throughout the description, it will be
`understood by those of skill in the art that the term data block
`is frequently used interchangeably with the term “memory
`block” in the art. Each data block has a plurality of data
`segments for storing data. In the present exemplary flash
`storage device, each data block is illustrated as including 16
`data segments. The scope of the present invention, however, is
`not limited to Such an arrangement. Rather, as will be appar
`ent to one of skill in the art, a data block may be configuredd
`with more or less than 16 data segments as desired to provide
`various levels of storage space. For example, in accordance
`with one aspect of the Subject disclosure, a data block may
`include 32 data segments of 4 kilobytes (kB) each to provide
`128 kB of data storage. While data blocks are usually config
`ured with 2" data segments (e.g., 16, 32, 64, 128, 256, etc.),
`the scope of the invention is not so limited. Similarly, while
`each data block is illustrated as including the same number of
`data segments, the scope of the invention is not so limited, as
`a flash storage device may comprise a number of data blocks
`with differing capacities and/or numbers of data segments. In
`accordance with one aspect of the Subject disclosure, a data
`
`Micron Ex. 1012, p. 12
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2009/0327591 A1
`
`Dec. 31, 2009
`
`block may span over more than one flash memory chip in a
`storage array of multiple chips. In accordance with another
`aspect, a data block is stored on a single flash memory chip in
`a storage array of multiple flash memory chips.
`0028. The flash storage device (or SSD) 100 can option
`ally include a Dynamic Random Access Memory (DRAM)
`106, as shown, though DRAM can be present in controller
`102, as explained for FIG. 2. Other types of random access
`memory and/or Volatile memory may also be used. The
`DRAM 106 may be used to buffer data to be written into the
`flash array 108. The data to be written may be incoming data
`from a host system and/or data being rewritten from one
`portion of the flash array 108 to another portion of the flash
`array 108. The flash storage device 100 can also optionally
`include an auxiliary power device 100 for providing backup
`power.
`0029 Flash storage device 100 can also include, employ,
`or be linked to a data structure or list for storing information
`associated with each data block in the flash memory (one or
`more channels). For example, a set of linked lists can be
`employed to track the number of valid segments in each block
`of flash memory (e.g., one list identifies all blocks with 32
`valid segments, another lists identifies all blocks with 31 valid
`segments, down to the final list which identifies all blocks
`with no valid segments). When empty blocks are needed to
`write new data from the host, blocks with the least number of
`valid segments are selected for garbage collection, where any
`remaining valid segments are copied to a new block and the
`old block is erased.
`0030. A set of linked lists can be used for device 100 to
`track the relative number of times blocks have been erased
`based on the lowest erase count among the blocks. For
`example, one list may contain all blocks with erase count
`within 0 to 1000 of the erase count of the lowest count block,
`the next list may contain all blocks with erase counts that are
`within 1001 to 2000 of the erase count of the lowest count
`block, etc. When a block reaches the highest erase count list,
`the data contained within that block is swapped with data
`from a block on the lowest erase count list, which is presumed
`to be more static since the block containing the data has a low
`erase count. This wear leveling is done to keep all of the flash
`memory chips within a specified range of erase counts.
`0031. According to embodiments of the present disclo
`Sure, the data structures or linked lists may store information
`about the number of data errors that have occurred in read
`operations corresponding to each of the data blocks. This
`information may allow controller to select a data block from
`which to move dynamic data in favor of static data, as
`described in greater detail below. The data structures or linked
`lists may include information about the number of data read
`errors that have occurred in each data block since flash stor
`age device 100 was last powered on. The data structures of
`linked lists may include information about the total number of
`data read errors that have occurred in each data block since
`some time prior to the last time flash storage device 100 was
`powered on (e.g., since flash storage device 100 was initial
`ized, formatted, manufactured, first powered on, etc.). In
`accordance with still another aspect of the Subject disclosure,
`the data structures (linked lists) may include information
`about the number of data read errors that have occurred in
`each data block both since flash storage device 100 was last
`powered on and since a time previous to the last time flash
`
`storage device 100 was powered on (e.g., since flash storage
`device 100 was initialized, formatted, manufactured, first
`powered on, etc.).
`0032. The flash drive may use the erase count lists to move
`data between MLC flash and SLC flash. For example, once a
`block in MLC flash reaches a threshold erase count (e.g.,
`500), the next write operation to that block triggers a swap
`where the data from the MLC flashblock is written to a block
`in SLC flash. In this manner, data for an LBA that is fre
`quently written and causes frequent erasures is moved to SLC
`flash which can perform more erase cycles than MLC flash.
`0033 Information regarding the number of data read
`errors associated with a given data block may be used to
`determine whether the data stored therein is dynamic or static.
`For example, if the number of read errors of a certain data
`block, such as data block, is below a predetermined threshold
`(e.g. 2), then controller may be configured to determine that
`the data segments therein contain “static' data. If the number
`ofread errors of a certain data block, Such as data block, meets
`or exceeds a predetermined threshold (e.g. 2), then controller
`may be configured to determine that the data segments therein
`contain 'dynamic data. In this way, data which is subject to
`more frequent write or rewrite operations (e.g., operations
`which may reduce the reliability of the associated data seg
`ments and/or data blocks) is determined to be dynamic data,
`and can be relocated to data blocks with less wear (e.g., as
`determined by the number of data read errors associated
`therewith).
`0034. While in the foregoing description, a data block has
`been described as being determined to contain static or
`dynamic databased upon a predetermined threshold of two
`data read errors, the scope of the present invention is not
`limited to Such an arrangement. Rather, as will be apparent to
`those of skill in the art, any threshold value greater than 0 may
`be used to determine whether a data block contains static or
`dynamic data. Moreover, the predetermined threshold may be
`Subject to change as necessary to characterize at least Some of
`the data in flash storage device 100 as static, as is described in
`greater detail below. Accordingly, the terms “dynamic and
`“static' are used hereinto describe the relative frequency with
`which data is updated among data blocks in a flash storage
`device, and do not imply a rigid or unchanging definition.
`Moreover, data which is at one time determined to be static
`may later be determined to be dynamic, and Vice versa.
`0035. The I/O interface 104 between the controller 102
`and host system (not shown) may be any Suitable one, e.g.,
`including, but not limited to compact flash (CF), integrated
`drive electronics (IDE), advanced technology attachment
`(ATA), serial-ATA (SATA), universal serial bus (USB),
`secure digital (SD), multi-media card (MMC), fiber channel
`(FC), small computer systems interface (SCSI), and serial
`attached SCSI (SAS).
`0036 FIG. 2 depicts a schematic view of a controller
`architecture 200 of a controller, e.g., controller 102 of FIG. 1,
`in accordance with exemplary embodiments of the present
`disclosure. Controller 200 serves to control the writing and
`erasing of data (blockS/segments) to the channels of flash
`memory in the flash array (shown as four channels 0-3). The
`controller architecture 200 can include a host I/F Register and
`control (I/F Register) 202 connected to a buffer control 204.
`Buffer control 204 can be connected to a sector buffer 206, a
`memory control unit (MCU) 208, and RAM for virtual-to
`physical mapping (V2P) 214. The MCU 208 can be con
`nected to ROM 210 and variable RAM 212.
`
`Micron Ex. 1012, p. 13
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2009/0327591 A1
`
`Dec. 31, 2009
`
`0037) Sector buffer 206 is a buffer configured to transfer
`data from the host system (not shown) to buffer, buffer to flash
`and vice versa and can include a dedicated buffer for each
`memory channel present. For example, four sector buffers
`206(0)-206(3) are shown corresponding to channels 0-3. V2P
`RAM 214 includes one or more tables that serve to record the
`physical block address of a specific virtual block. As shown,
`V2P 214 can include a separate buffer/list 214(0)-214(3) for
`each channel in the memory device, e.g., SSD 100 of FIG.1.
`0038 Multiple channels can be used for a SSD according
`to the present disclosure to parallel data transfer to maximize
`the read/write performance. For example, each channel can
`connects with five chips of flash (e.g., the first chip can be a
`K9K8G08 SLC flash, and the rest can be K9G8G08 MLC
`flash). The V2P RAM for each channel can be 80K Bytes. For
`4 channels SSD, V2P size is preferably 320K (or more) Bytes
`to support 20G Bytes. (FIG. 2)
`0039 Each V2P entry can be 32 bits, which, in exemplary
`embodiments, can be arranged according to the format 300
`depicted in FIG. 3.
`0040 FIG. 4 depicts a schematic view of a SLC data
`structure outline, in accordance with exemplary embodi
`ments of the of the present disclosure. For example, assuming
`that a SLC flash chip (e.g., K9K8G08) has 8192 blocks, it can
`be regarded as 4096 units (one unit is made of two blocks—
`one is in even plane and the other is at odd plane). As shown
`in FIG. 4, for such a data structure, there are 3 free units in
`SLC for data buffer while doing data copy. There are 80 units
`for defect unit's replacement unit this SLC chip. Free units
`also include the reserved units for defect replacement.
`004.1
`FIG. 5, depicts the data structure outline for MLC
`chips (e.g., 4 MLC chips in each channel), in accordance with
`exemplay embodiments of the present disclosure. In accor
`dance with exemplary embodiments of the present disclosure,
`only 3 units are kept for free units as the data buffer while
`copying data, e.g., for the four MLC chips in exemplary
`channels. The reserved defect replacement units can be
`located at the last chip of each channel. The system unit which
`describes the original defect block table, on-going defect
`blocktable, and features offlash devices and systems can also
`be located at the last chip of each channel.
`0042 FIG. 6 depicts a schematic view of data structure
`600 within NAND flash, in accordance with exemplary
`embodiments of the of the present disclosure. The data struc
`ture 600 can result after one or more pre-format procedures
`have occurred, e.g., procedures that search the defect blocks,
`build defect block tables, replacement defect block tables,
`and build the system units.
`0043. After a pre-format, a data block in not automatically
`assigned with the VU and VS. The block is free if bit 0 to bit
`15 of V2P is “FFFFH. The incoming data was written to a
`free block (if the corresponding V2P value is “FFFFH).
`After data is written to flash, the corresponding VU is marked
`to the redundancy area of the block.
`0044) Through the use of dynamic assigning LBA to
`physical address, a block that is blank can be use as a free
`block as well. Thus, the maximum number of blocks for to be
`used as free blocks can be obtained to reduce the erase count
`for free block. System firmware (FW) assigns the physical
`address to SLC in each channel first. When the SLC is full
`then data will be assign to an MLC area, e.g., one of the MLC
`chips in a channel. For the exemplary data structure depicted
`in FIG. 6, there is a Data Area (byte 0 to byte 2027), a
`Redundancy area 1 (byte 0 to byte 31), and Redundancy area
`
`1' (byte 32 to byte 63). In FIG. 6, for the data structure shown,
`ECCNTU is the ECC of NTU, ECCVU is the ECC of VU,
`Ecount is the erase count of the block, *) FPP=Free Page
`Pointer, **) DFPP is the ECC of FPP VSECC is the ECC of
`VS, and VU virtual unit number during one channel. NTU
`represents the new physical unit number during one channel.
`EraseGnt is the erase count of the physical unit. When a value
`is “FEFEH' it indicates that the erase count of this block is
`more than 1000 and has been moved from SLC to MLC. In
`such a case, the bit 16 of V2P table can be marked as “1” as
`shown.
`0045. For the initialization of exemplary embodiments,
`FW can read the second page of every block to find the W
`value. The block which is sys