1111111111111111 IIIIII IIIII 11111 1111111111 111111111111111 111111111111111 1111111111 11111111
`US 20080140918Al
`
`c19) United States
`c12) Patent Application Publication
`Sutardja
`
`c10) Pub. No.: US 2008/0140918 Al
`Jun. 12, 2008
`(43) Pub. Date:
`
`(54) HYBRID NON-VOLATILE SOLID STATE
`MEMORY SYSTEM
`
`(76)
`
`Inventor:
`
`Pantas Sutardja, Los Gatos, CA
`(US)
`
`Correspondence Address:
`HARNESS, DICKEY & PIERCE P.L.C.
`5445 CORPORATE DRIVE, SUITE 200
`TROY, MI 48098
`
`(21) Appl. No.:
`
`11/952,648
`
`(22) Filed:
`
`Dec. 7, 2007
`
`Related U.S. Application Data
`
`(60) Provisional application No. 60/869,493, filed on Dec.
`11, 2006.
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`G06F 12102
`(2006.01)
`G06F 12100
`(2006.01)
`(52) U.S. Cl. ................. 711/103; 711/154; 711/E12.008;
`711/E12.001
`
`(57)
`
`ABSTRACT
`
`A solid state memory system comprises a first nonvolatile
`semiconductor (NVS) memory that has a first write cycle
`lifetime, a second nonvolatile semiconductor (NVS) memory
`that has a second write cycle lifetime that is different than the
`first write cycle lifetime, and a wear leveling module. The
`wear leveling module generates first and second wear levels
`for the first and second NVS memories based on the first and
`second write cycle lifetimes and maps logical addresses to
`physical addresses of one of the first and second NVS memo(cid:173)
`ries based on the first and second wear levels.
`
`450··(
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`,--------------------1
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`
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`
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`
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`
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`
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`Mapping Module
`
`465
`
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`Module
`
`260
`
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`Interface
`
`Second Solid•Slate
`Nonvolatile Memory
`
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`-----················································································
`
`Micron Ex. 1011, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 1 of 16
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`Micron Ex. 1011, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
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`Jun. 12, 2008 Sheet 2 of 16
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`Micron Ex. 1011, p. 3
`Micron v. Vervain
`IPR2021-01547
`
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`Micron Ex. 1011, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`

`

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`Micron Ex. 1011, p. 5
`Micron v. Vervain
`IPR2021-01547
`
`

`

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`
`Micron Ex. 1011, p. 6
`Micron v. Vervain
`IPR2021-01547
`
`

`

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`
`Micron Ex. 1011, p. 7
`Micron v. Vervain
`IPR2021-01547
`
`

`

`> ....
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`
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`·····----••••••••••• -•• ------••••••••••• 1. --............ _ --·· ----· --• --•••••••••••••••• ----------. ·----• -•••••••••••••• -•• --•••• ------------
`
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`
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`
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`
`450··: . . . .
`
`Micron Ex. 1011, p. 8
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 8 of 16
`
`US 2008/0140918 Al
`
`502
`
`Start
`
`!500
`
`Receive Write Frequencies For
`Logical Addresses From Host
`
`Map Logical Addresses With
`Low Write Frequencies To
`First Memory
`
`Map Logical Addresses With
`High Write Frequencies To
`Second Memory
`
`504
`
`506
`
`508
`
`Write Data According
`To Mapping
`
`510
`
`Measure Actual Write Frequencies
`And Update Mapping
`
`512
`
`FIG. 7A
`
`Micron Ex. 1011, p. 9
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 9 of 16
`
`US 2008/0140918 Al
`
`N
`
`N
`
`N
`
`FIG. 7B
`
`Micron Ex. 1011, p. 10
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 10 of 16
`
`US 2008/0140918 Al
`
`N
`
`N
`
`y
`
`Map Corresponding Logical
`Addresses To A Block Of Second
`Memory
`
`522
`
`y
`
`Identify LUB In Second Memory
`
`Map Corresponding Logical
`Addresses To A Block Of First
`Memory
`
`526
`
`528
`
`FIG. 7C
`
`Micron Ex. 1011, p. 11
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 11 of 16
`
`US 2008/0140918 Al
`
`Write Data To A
`Physical Address
`At A First Time
`
`Write Data To
`The Physical
`Address At A
`Second Time
`
`Read Back
`
`Generate A
`Degradation
`Value For The
`Physical Address
`Based On The
`Two Readbacks
`
`Update Mapping
`Based On
`Degradation
`Value
`
`530
`
`532
`
`534
`
`536
`
`538
`
`540
`
`FIG. 7D
`
`Micron Ex. 1011, p. 12
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 12 of 16
`
`US 2008/0140918 Al
`
`Generate Wear Levels For
`First And Second Memories
`
`542
`
`y
`
`y
`
`546
`
`Map All Logical
`Addresses To
`First Memory
`
`550
`
`Map All Logical
`Addresses To
`Second Memory
`
`N
`
`N
`
`FIG. 7E
`
`Micron Ex. 1011, p. 13
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 13 of 16
`
`US 2008/0140918 Al
`
`602
`
`Start
`
`/600
`
`Receive data related to write
`frequency, access time
`requirement, etc., for writing data
`to logical addresses from host
`
`604
`
`Map logical addresses where data is
`written more frequently and/or requires
`faster access time to second memory
`
`606
`
`Map logical addresses where data is
`written less frequently and/or requires
`slower access time to first memory
`
`608
`
`Write Data According
`To Mapping
`
`610
`
`Measure Actual Write Frequencies
`And Update Mapping
`
`612
`
`614
`
`FIG. 8
`
`Micron Ex. 1011, p. 14
`Micron v. Vervain
`IPR2021-01547
`
`

`

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`Micron Ex. 1011, p. 15
`Micron v. Vervain
`IPR2021-01547
`
`

`

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`Micron Ex. 1011, p. 16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 16 of 16
`
`US 2008/0140918 Al
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`Micron Ex. 1011, p. 17
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2008/0140918 Al
`
`Jun. 12,2008
`
`1
`
`HYBRID NON-VOLATILE SOLID STATE
`MEMORY SYSTEM
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application claims the benefit of U.S. Provi(cid:173)
`sional Application No. 60/869,493 filed on Dec. 11, 2006.
`The disclosure of the above application is incorporated herein
`by reference in its entirety.
`
`FIELD
`
`[0002] The present disclosure relates to solid state memo(cid:173)
`ries, and more particularly to hybrid non-volatile solid state
`memones.
`
`BACKGROUND
`
`[0003] The background description provided herein is for
`the purpose of generally presenting the context of the disclo(cid:173)
`sure. Work of the presently named inventors, to the extent it is
`described in this background section, as well as aspects of the
`description that may not otherwise qualify as prior art at the
`time of filing, are neither expressly nor impliedly admitted as
`prior art against the present disclosure.
`[0004] Flash memory chips, which use charge storage
`devices, have become a dominant chip type for semiconduc(cid:173)
`tor-based mass storage devices. The charge storage devices
`are particularly suitable in applications where data files to be
`stored include music and image files. Charge storage devices,
`however, can sustain a limited number of write cycles after
`which the charge storage devices can no longer reliably store
`data.
`[0005] A limited number of write cycles may be acceptable
`for many applications such as removable USB (universal
`serial bus) drives, MP3 (MPEG Layer 3) players, and digital
`camera memory cards. However, when used as general
`replacements for built-in primary data drives in computer
`systems, a limited number of write cycles may not be accept(cid:173)
`able.
`[0006] Lower density flash devices, where a single bit is
`stored per storage cell, typically have a usable lifetime on the
`order of 100,000 write cycles. To reduce cost, flash devices
`may store 2 bits per storage cell. Storing 2 bits per storage
`cell, however, may reduce the usable lifetime of the device to
`a level on the order of 10,000 write cycles.
`[0007] Flash devices may not have a long enough lifetime
`to serve as mass storage, especially where part of the mass
`storage is used as virtual memory paging space. Virtual
`memory paging space is used by operating systems to store
`data from RAM (random access memory) when available
`space in RAM is low. For purposes of illustration only, a flash
`memory chip may have a capacity of 2 GB (gigabytes), may
`store 2 bits per cell, and may have a write throughput of about
`4 MB/s (megabytes per second). In such a flash memory chip,
`it is theoretically possible to write every bit in the chip once
`every 500 seconds (i.e., 2E9 bytes/4E6 bytes/s).
`[0008]
`It is then theoretically possible to write every bit
`10,000 times in only 5E6 seconds (1E4 cycles*5E2 seconds),
`which is less than two months. In reality, however, most drive
`storage will not be written with 100% duty cycle. A more
`realistic write duty cycle may be 10%, which may happen
`when a computer is continuously active and performs virtual
`memory paging operations. At 10% write duty cycle, the
`usable lifetime of the flash device may be exhausted in
`
`approximately 20 months. By contrast, the life expectation
`for a magnetic hard disk storage device typically exceeds 10
`years.
`[0009] Referring now to FIG. 1, a functional block diagram
`of a solid-state disk according to the prior art is presented. The
`solid-state disk 100 includes a controller 102 and a flash
`memory 104. The controller 102 receives instructions and
`data from a host (not shown). When a memory access is
`requested, the controller 102 reads or writes data to the flash
`memory 104, and communicates this information to the host.
`[001 OJ An area of the flash memory 104 may become unre(cid:173)
`liable for storage after it has been written to or erased a
`predetermined number of times. This predetermined number
`of times is referred to as the write cycle lifetime of the flash
`memory 104. Once the write cycle lifetime of the flash
`memory 104 has been exceeded, the controller 102 can no
`longer reliably store data in the flash memory 104, and the
`solid-state disk 100 may no longer be usable.
`
`SUMMARY
`
`[0011] A solid state memory system comprises a first non(cid:173)
`volatile semiconductor (NVS) memory that has a first write
`cycle lifetime, a second nonvolatile semiconductor (NVS)
`memory that has a second write cycle lifetime that is different
`than the first write cycle lifetime, and a wear leveling module.
`The wear leveling module generates first and second wear
`levels for the first and second NVS memories based on the
`first and second write cycle lifetimes and maps logical
`addresses to physical addresses of one of the first and second
`NVS memories based on the first and second wear levels.
`[0012]
`In other features, the first wear level is based on a
`ratio of a first number of write operations performed on the
`first NVS memory to the first write cycle lifetime. The second
`wear level is based on a ratio of a second number of write
`operations performed on the second NVS memory to the
`second write cycle lifetime. The wear leveling module maps
`the logical addresses to the physical addresses of the second
`memory when the second wear level is less than the first wear
`level. The first NVS memory has a first storage capacity that
`is greater than a second storage capacity of the second NVS
`memory.
`[0013]
`In further features, the solid state memory system
`further comprises a mapping module that receives first and
`second frequencies for writing data to first and second of the
`logical addresses. The wear leveling module biases mapping
`of the first of the logical addresses to the physical addresses of
`the second NVS memory when the first frequency is greater
`than the second frequency and the second wear level is less
`than the first wear level.
`[0014]
`In still other features, the wear leveling module
`biases mapping of the second of the logical addresses to the
`physical addresses of the first NVS memory. The solid state
`memory system further comprises a write monitoring module
`that monitors subsequent frequencies of writing data to the
`first and second of the logical addresses and that updates the
`first and second frequencies based on the subsequent frequen(cid:173)
`cies.
`[0015]
`In other features, the solid state memory system
`further comprises a write monitoring module that measures
`first and second frequencies of writing data to first and second
`of the logical addresses. The wear leveling module biases
`mapping of the first of the logical addresses to the physical
`addresses of the second NVS memory when the first fre(cid:173)
`quency is greater than the second frequency and the second
`
`Micron Ex. 1011, p. 18
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2008/0140918 Al
`
`Jun. 12,2008
`
`2
`
`wear level is less than the first wear level. The wear leveling
`module biases mapping of the second of the logical addresses
`to the physical addresses of the first NVS memory.
`[0016]
`In further features, the solid state memory system
`further comprises a degradation testing module that writes
`data at a first predetermined time to one of the physical
`addresses; generates a first stored data by reading data from
`the one of the physical addresses; writes data to the one of the
`physical addresses at a second predetermined time; generates
`a second stored data by reading data from the one of the
`physical addresses; and generates a degradation value for the
`one of the physical addresses based on the first and second
`stored data.
`[0017]
`In still other features, the wear leveling module
`maps one of the logical addresses to the one of the physical
`addresses based on the degradation value. The wear leveling
`module maps the logical addresses to the physical addresses
`of the first NVS memory when the second wear level is
`greater than or equal to a first predetermined threshold; and
`the wear leveling module maps the logical addresses to the
`physical addresses of the second NVS memory when the first
`wear level is greater than or equal to a second predetermined
`threshold.
`[0018]
`In other features, when write operations performed
`on a first block of the physical addresses of the first NVS
`memory during a predetermined period are greater than or
`equal to a predetermined threshold, the wear leveling module
`biases mapping of corresponding ones of the logical
`addresses from the first block to a second block of the physi(cid:173)
`cal addresses of the second NVS memory. The wear leveling
`module identifies a first block of the physical addresses of the
`second NVS memory as a least used block (LUB).
`[0019]
`In further features, the wear leveling module biases
`mapping of corresponding ones of the logical addresses from
`the first block to a second block of the physical addresses of
`the first NVS memory when available memory in the second
`NVS memory is less than or equal to a predetermined thresh(cid:173)
`old. The first NVS memory comprises a flash device and the
`second NVS memory comprises a phase-change memory
`device. The first NVS memory comprises a Nitride Read(cid:173)
`Only Memory (NROM) flash device. The first write cycle
`lifetime is less than the second write cycle lifetime.
`[0020] A method comprises generating first and second
`wear levels for first and second nonvolatile semiconductor
`(NVS) memories based on first and second write cycle life(cid:173)
`times. The first and second write cycle lifetimes correspond to
`the first and second NVS memories, respectively; and map(cid:173)
`ping logical addresses to physical addresses of one of the first
`and second NVS memories based on the first and second wear
`levels.
`[0021]
`In other features, the first wear level is based on a
`ratio of a first number of write operations performed on the
`first NVS memory to the first write cycle lifetime. The second
`wear level is based on a ratio of a second number of write
`operations performed on the second NVS memory to the
`second write cycle lifetime. The method further comprises
`mapping the logical addresses to the physical addresses of the
`second memory when the second wear level is less than the
`first wear level.
`[0022]
`In further features, the first NVS memory has a first
`storage capacity that is greater than a second storage capacity
`of the second NVS memory. The first write cycle lifetime is
`less than the second write cycle lifetime. The method further
`comprises receiving first and second frequencies for writing
`
`data to first and second of the logical addresses; and biasing
`mapping of the first of the logical addresses to the physical
`addresses of the second NVS memory when the first fre(cid:173)
`quency is greater than the second frequency and the second
`wear level is less than the first wear level.
`[0023]
`In still other features, the method further comprises
`biasing mapping of the second of the logical addresses to the
`physical addresses of the first NVS memory. The method
`further comprises monitoring subsequent frequencies of writ(cid:173)
`ing data to the first and second of the logical addresses; and
`updating the first and second frequencies based on the sub(cid:173)
`sequent frequencies.
`[0024]
`In other features, the method further comprises
`measuring first and second frequencies of writing data to first
`and second of the logical addresses; and biasing mapping of
`the first of the logical addresses to the physical addresses of
`the second NVS memory when the first frequency is greater
`than the second frequency and the second wear level is less
`than the first wear level. The method further comprises bias(cid:173)
`ing mapping of the second of the logical addresses to the
`physical addresses of the first NVS memory.
`[0025]
`In further features, the method further comprises
`writing data at a first predetermined time to one of the physi(cid:173)
`cal addresses; generating a first stored data by reading data
`from the one of the physical addresses; writing data to the one
`of the physical addresses at a second predetermined time;
`generating a second stored data by reading data from the one
`of the physical addresses; and generating a degradation value
`for the one of the physical addresses based on the first and
`second stored data.
`[0026]
`In still other features, the method further comprises
`mapping one of the logical addresses to the one of the physi(cid:173)
`cal addresses based on the degradation value. The method
`further comprises mapping the logical addresses to the physi(cid:173)
`cal addresses of the first NVS memory when the second wear
`level is greater than or equal to a first predetermined thresh(cid:173)
`old; and mapping the logical addresses to the physical
`addresses of the second NVS memory when the first wear
`level is greater than or equal to a second predetermined
`threshold.
`[0027]
`In other features, when write operations performed
`on a first block of the physical addresses of the first NVS
`memory during a predetermined period are greater than or
`equal to a predetermined threshold, biasing mapping of cor(cid:173)
`responding ones of the logical addresses from the first block
`to a second block of the physical addresses of the secondNVS
`memory. The method further comprises identifying a first
`block of the physical addresses of the second NVS memory as
`a least used block (LUB).
`[0028]
`In further features, the method further comprises
`biasing mapping of corresponding ones of the logical
`addresses from the first block to a second block of the physi(cid:173)
`cal addresses of the first NVS memory when available
`memory in the second NVS memory is less than or equal to a
`predetermineed threshold. The first NVS memory comprises
`a flash device and the second NVS memory comprises a
`phase-change memory device. The first NVS memory com(cid:173)
`prises a Nitride Read-Only Memory (NROM) flash device.
`[0029] A computer program stored for use by a processor
`for operating a solid state memory system comprises gener(cid:173)
`ating first and second wear levels for first and second non(cid:173)
`volatile semiconductor (NVS) memories based on first and
`second write cycle lifetimes. The first and second write cycle
`lifetimes correspond to the first and second NVS memories,
`
`Micron Ex. 1011, p. 19
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2008/0140918 Al
`
`Jun. 12,2008
`
`3
`
`respectively; and mapping logical addresses to physical
`addresses of one of the first and second NVS memories based
`on the first and second wear levels.
`In other features, the first wear level is based on a
`[0030]
`ratio of a first number of write operations performed on the
`first NVS memory to the first write cycle lifetime. The second
`wear level is based on a ratio of a second number of write
`operations performed on the second NVS memory to the
`second write cycle lifetime. The computer program further
`comprises mapping the logical addresses to the physical
`addresses of the second memory when the second wear level
`is less than the first wear level.
`In further features, the first NVS memory has a first
`[0031]
`storage capacity that is greater than a second storage capacity
`of the second NVS memory. The first write cycle lifetime is
`less than the second write cycle lifetime. The computer pro(cid:173)
`gram further comprises receiving first and second frequencies
`for writing data to first and second of the logical addresses;
`and biasing mapping of the first of the logical addresses to the
`physical addresses of the second NVS memory when the first
`frequency is greater than the second frequency and the second
`wear level is less than the first wear level.
`In still other features, the computer program further
`[0032]
`comprises biasing mapping of the second of the logical
`addresses to the physical addresses of the first NVS memory.
`The computer program further comprises monitoring subse(cid:173)
`quent frequencies of writing data to the first and second of the
`logical addresses; and updating the first and second frequen(cid:173)
`cies based on the subsequent frequencies.
`In other features, the computer program further
`[0033]
`comprises measuring first and second frequencies of writing
`data to first and second of the logical addresses; and biasing
`mapping of the first of the logical addresses to the physical
`addresses of the second NVS memory when the first fre(cid:173)
`quency is greater than the second frequency and the second
`wear level is less than the first wear level. The computer
`program further comprises biasing mapping of the second of
`the logical addresses to the physical addresses of the first
`NVSmemory.
`In further features, the computer program further
`[0034]
`comprises writing data at a first predetermined time to one of
`the physical addresses; generating a first stored data by read(cid:173)
`ing data from the one of the physical addresses; writing data
`to the one of the physical addresses at a second predetermined
`time; generating a second stored data by reading data from the
`one of the physical addresses; and generating a degradation
`value for the one of the physical addresses based on the first
`and second stored data.
`In still other features, the computer program further
`[0035]
`comprises mapping one of the logical addresses to the one of
`the physical addresses based on the degradation value. The
`computer program further comprises mapping the logical
`addresses to the physical addresses of the first NVS memory
`when the second wear level is greater than or equal to a first
`predetermined threshold; and mapping the logical addresses
`to the physical addresses of the second NVS memory when
`the first wear level is greater than or equal to a second prede(cid:173)
`termined threshold.
`In other features, when write operations performed
`[0036]
`on a first block of the physical addresses of the first NVS
`memory during a predetermined period are greater than or
`equal to a predetermined threshold, biasing mapping of cor(cid:173)
`responding ones of the logical addresses from the first block
`to a second block of the physical addresses of the