EXHIBIT A-3
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`U.S. Patent Application Publication No. 2011/0099460 (“Dusija”) was filed on December 18, 2009 and published on April 28, 2011.
`Dusija is prior art to the ’298 patent under at least 35 U.S.C. §§ 102(a), (e) (pre-AIA). The asserted claims of the ’298 patent are
`anticipated by Dusija expressly and/or inherently or rendered obvious, either alone or in combination with other references, as set
`forth in the cover pleading for Micron’s Initial Invalidity Contentions and as further explained in the chart below.
`
`This chart is based on Defendants’ present understanding of Plaintiff’s apparent positions as to the scope of the asserted claims. By
`including prior art that invalidates the claims of the patent based on Plaintiff’s claim construction and infringement positions,
`Defendants are neither adopting nor acceding in any manner to Plaintiff’s claim construction and infringement positions.
`Furthermore, nothing stated herein shall be treated as an admission or suggestion that Defendants agree with Plaintiff regarding either
`the scope of any of the asserted claims or the claim constructions Plaintiff advances in its infringement allegations or anywhere else.
`Nor shall anything in this chart be treated as an admission that any of Defendants’ accused technology meets any limitations of the
`claims.
`
`Claim 1
`[1.Pre] A system for storing
`data comprising:
`
`U.S. Pat. No. 8,891,298
`Disclosure in Dusija
`To the extent the preamble is limiting, Dusija discloses and/or renders obvious a system for storing
`data.
`
`[1.A] at least one MLC non-
`volatile memory module
`comprising a plurality of
`individually erasable blocks;
`
`See, e.g.,
`
`[0059]
`
` FIG. 1
`
`Dusija discloses and/or renders obvious at least one MLC non-volatile memory module comprising a
`plurality of individually erasable blocks.
`
`See, e.g.,
`
` FIGs. 6, 14A
`[0109]
`
`[0079]
`
`
`1
`
`Vervain Ex. 2009, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`U.S. Patent Application Publication No. 2011/0099460 (“Dusija”) was filed on December 18, 2009 and published on April 28, 2011.
`Dusija is prior art to the ’298 patent under at least 35 U.S.C. §§ 102(a), (e) (pre-AIA). The asserted claims of the ’298 patent are
`anticipated by Dusija expressly and/or inherently or rendered obvious, either alone or in combination with other references, as set
`forth in the cover pleading for Micron’s Initial Invalidity Contentions and as further explained in the chart below.
`
`This chart is based on Defendants’ present understanding of Plaintiff’s apparent positions as to the scope of the asserted claims. By
`including prior art that invalidates the claims of the patent based on Plaintiff’s claim construction and infringement positions,
`Defendants are neither adopting nor acceding in any manner to Plaintiff’s claim construction and infringement positions.
`Furthermore, nothing stated herein shall be treated as an admission or suggestion that Defendants agree with Plaintiff regarding either
`the scope of any of the asserted claims or the claim constructions Plaintiff advances in its infringement allegations or anywhere else.
`Nor shall anything in this chart be treated as an admission that any of Defendants’ accused technology meets any limitations of the
`claims.
`
`Claim 1
`[1.Pre] A system for storing
`data comprising:
`
`U.S. Pat. No. 8,891,298
`Disclosure in Dusija
`To the extent the preamble is limiting, Dusija discloses and/or renders obvious a system for storing
`data.
`
`[1.A] at least one MLC non-
`volatile memory module
`comprising a plurality of
`individually erasable blocks;
`
`See, e.g.,
`
`[0059]
`
` FIG. 1
`
`Dusija discloses and/or renders obvious at least one MLC non-volatile memory module comprising a
`plurality of individually erasable blocks.
`
`See, e.g.,
`
` FIGs. 6, 14A
`[0109]
`
`[0079]
`
`
`1
`
`Vervain Ex. 2009, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`
`
`EXHIBIT A-3
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`[1.B] at least one SLC non-
`volatile memory module
`comprising a plurality of
`individually erasable blocks;
`and
`
`[1.C] a controller coupled to
`the at least one MLC non-
`volatile memory module and
`the at least one SLC non-
`volatile memory module
`
`[1.D.i] wherein the controller
`is adapted to: (a) maintain an
`address map of at least one of
`the MLC and SLC non-
`volatile memory modules,
`the address map comprising a
`list of logical address ranges
`accessible by a computer
`
`
`
`
`
`U.S. Pat. No. 8,891,298
`
`
`Dusija discloses and/or renders obvious at least one SLC non-volatile memory module comprising a
`plurality of individually erasable blocks.
`
`See, e.g.,
`
`
`
`[0109]
`
`[0077]-[0079]
` FIGs. 6, 14A
`
`
`Dusija discloses and/or renders obvious a controller coupled to the at least one MLC non-volatile
`memory module and the at least one SLC non-volatile memory module.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0060]
`
`[0117]
`
`[0062]
`
`See also Claim limitations [1.A-B] and accompanying citations.
`
`Dusija discloses and/or renders obvious wherein the controller is adapted to maintain an address map
`of at least one of the MLC and SLC non-volatile memory modules, the address map comprising a list
`of logical address ranges accessible by a computer system.
`
`See, e.g.,
`
`
`
`
`
`[0117]
`[0129]
`
`2
`
`Vervain Ex. 2009, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`
`
`EXHIBIT A-3
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`system
`
`[1.D.ii] the list of logical
`address ranges having a
`minimum quanta of
`addresses
`
`U.S. Pat. No. 8,891,298
`
`[0138]
`[0060], [0117], [0129], [0138] (examples of mapping)
`[0164]-[0167] (example of mapping physical to “logical addresses”)
`
`
`
`
`
`Dusija discloses and/or renders obvious the list of logical address ranges having a minimum quanta of
`addresses.
`
`See, e.g.,
`
`
`
`
`
`
`[0060] (logical sector)
`[0111] (incoming “page”)
`[0166]-[0168] (logical blocks)
`[0061]
`
`[1.D.iii] wherein each entry
`in the list of logical address
`ranges maps to a similar
`range of physical addresses
`within either the at least one
`SLC non-volatile memory
`module or within the at least
`one MLC non-volatile
`memory module
`
`[1.E.i] b) determine if a
`range of addresses listed by
`an entry and mapped to a
`similar range of physical
`
`Dusija discloses and/or renders obvious wherein each entry in the list of logical address ranges maps
`to a similar range of physical addresses within either the at least one SLC non-volatile memory
`module or within the at least one MLC non-volatile memory module.
`
`See, e.g.,
`
`
`
`
`
`
`
`[0060] (mapping sectors to corresponding physical data unit)
`[0117], [0129], [0138] (examples of mapping to different physical addresses in MLC and
`SLC)
`[0164]-[0167] (noting that a “block” can correspond to a “group of logical addresses”)
`[0061]
`
`Dusija discloses and/or renders obvious wherein the controller is adapted to determine if a range of
`addresses listed by an entry and mapped to a similar range of physical addresses within the at least
`one MLC non-volatile memory module, fails a data integrity test.
`
`3
`
`Vervain Ex. 2009, p. 3
`Micron v. Vervain
`IPR2021-01547
`
`
`
`EXHIBIT A-3
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`addresses within the at least
`one MLC non-volatile
`memory module, fails a data
`integrity test
`
`See, e.g.,
`
`
`
`
`[0111]-[0117]
`[0119]-[0124]
`
`U.S. Pat. No. 8,891,298
`
`[1.E.ii] in the event of such a
`failure, the controller remaps
`the entry to the next available
`equivalent range of physical
`addresses within the at least
`one SLC non-volatile
`memory module
`
`See also Claim limitation [1.A] and accompanying citations (“second portion” is MLC)
`
`See also Claim limitation [1.D] and accompanying citations (explaining logical-to-physical mapping)
`
`Dusija discloses and/or renders obvious in the event of such a failure, the controller remaps the entry
`to the next available equivalent range of physical addresses within the at least one SLC non-volatile
`memory module.
`
`See, e.g.,
`
`[0116]
`
`[0117]
`
`[0119]-[0125]
`
`[0203]
`
` FIG. 14B
`[0153]-[0154]
`
`[0060] (controller “controls” and “manages” memory operations); [0087]-[0088] (controller
`
`performs ECC); [0117] (controller remaps); [0118] (controller includes wear-leveling module)
`
`See also Claim limitation [1.B] and accompanying citations (“first portion” is the SLC memory
`module)
`
`[1.F] c) determine which of
`the blocks of the plurality of
`the blocks in the MLC and
`
`Dusija discloses and/or renders obvious wherein the controller is adapted to determine which of the
`blocks of the plurality of the blocks in the MLC and SLC non-volatile memory modules are accessed
`most frequently by maintaining a count of the number of times each one of the blocks is accessed.
`
`4
`
`Vervain Ex. 2009, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`
`
`EXHIBIT A-3
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`SLC non-volatile memory
`modules are accessed most
`frequently by maintaining a
`count of the number of times
`each one of the blocks is
`accessed
`
`[1.G] d) allocate those blocks
`that receive the most frequent
`writes by transferring the
`respective contents of those
`blocks to the at least one
`SLC non-volatile memory
`module
`
`Claim 3
`[3] The system of claim 1,
`wherein the minimum quanta
`of addresses is equal to one
`page.
`
`
`
`
`
`U.S. Pat. No. 8,891,298
`
`
`See, e.g.,
`
`
`
`
`
`
`
`
`
`[0027]
`[0051]
`[0101]
`[0107]
`[0153]-[0159] (hot count)
`[0204]
`
`
`Dusija discloses and/or renders obvious wherein the controller is adapted to allocate those blocks that
`receive the most frequent writes by transferring the respective contents of those blocks to the at least
`one SLC non-volatile memory module.
`
`See, e.g.,
`
`
`
`
`
`
`
`
`[0027]
`[0101]
`[0153]
`[0159]
`[0204]
`
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the minimum quanta of
`addresses is equal to one page.
`
`See, e.g.,
`
`
`
`
`
`[0166]-[0168]
`[0163]
`
`5
`
`Vervain Ex. 2009, p. 5
`Micron v. Vervain
`IPR2021-01547
`
`
`
`EXHIBIT A-3
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`U.S. Pat. No. 8,891,298
`
`[0208]-[0211]
`[0154] (“programmable unit is a page”)
`
`
`
`
`
`
`
`
`
`
`Claim 4
`[4] The system of claim 1,
`wherein the MLC non-
`volatile memory module is
`NAND flash memory.
`
`Claim 5
`[5] The system of claim 1,
`wherein the SLC non-volatile
`memory module is NAND
`flash memory.
`
`Claim 11
`[11] The system of claim 1,
`wherein the controller causes
`the transfer of content on a
`periodic basis.
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the MLC non-volatile memory
`module is NAND flash memory.
`
`See, e.g.,
`
`
`
`
`[0068] (memory array 200 may be “NAND”)
`
`
`See also Claim limitation [1.A] and accompanying citations (explaining that memory array 200
`includes the MLC memory)
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the SLC non-volatile memory
`module is NAND flash memory.
`
`See, e.g.,
`
`
`
`
`[0068] (memory array 200 may be “NAND”)
`
`
`See also Claim limitation [1.B] and accompanying citations (explaining that memory array 200
`includes the MLC memory)
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the controller causes the
`transfer of content on a periodic basis.
`
`See, e.g.,
`
`6
`
`Vervain Ex. 2009, p. 6
`Micron v. Vervain
`IPR2021-01547
`
`
`
`EXHIBIT A-3
`INVALIDITY CLAIM CHART FOR THE ’298 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/0099460 (“Dusija”)
`
`U.S. Pat. No. 8,891,298
`
`
`
`
`
`
`
`[0027] (threshold)
`[0153]-[0154]
`[0159]
`[0184]
`[0204]
`
`7
`
`Vervain Ex. 2009, p. 7
`Micron v. Vervain
`IPR2021-01547
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
