US007405614B2
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`a2) United States Patent
`US 7,405,614 B2
`(0) Patent No.:
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`Jul. 29, 2008
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`Gutzkiet al. (45) Date of Patent:
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`(54) CIRCUIT ARRANGEMENT HAVING AN
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`AMPLIFIER ARRANGEMENT AND AN
`
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`OFFSET COMPENSATION ARRANGEMENT
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`6,653,895 Bl
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`7,265,615 B2*
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`7,271,649 B2*
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`11/2003 Doutsetal.
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`............
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`330/69
`9/2007 Alexander etal.
`oe
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`9/2007 Chivetal.
`330/9
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`(75)
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`Inventors: Heiko Gutzki, Grafing (DE); Marcus
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`Nuebling, Olching-Esting (DE)
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`Infineon Technologies AG, Munich
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`(DE)
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`(73) Assignee:
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`(*) Notice:
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`(22)
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`(65)
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`to any disclaimer, the term ofthis
`Subject
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`patent is extended or
`adjusted under 35
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`U.S.C. 154(b) by 90 days.
`
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`(21) Appl. No.: 11/417,495
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`May4, 2006
`Filed:
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`Prior Publication Data
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`US 2007/0013439 Al
`Jan. 18, 2007
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`Foreign Application Priority Data
`ween
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`10 2005 020 803
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`OTHER PUBLICATIONS
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`Finvers, Ivars G. and Haslett, J.W., “A High Temperature Precision
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`Amplifier.” JEEE Journal ofSolid-State Circuits, vol. 30, Feb. 1995,
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`
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`pp. 120-128. (9 Pages).
`*
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`
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`cited by examiner
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`Primary Examiner—Henry K Choe
`
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`or
`Firm—Maginot, Moore & Beck
`(74) Attorney, Agent,
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`
`ABSTRACT
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`(57)
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`an
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`A circuit arrangement is disclosed herein comprising
`
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`
`
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`to receive an
`amplifier circuit having inputs configured
`input
`
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`
`
`
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`signal, and an
`an
`to
`output configured
`outputsignal.
`provide
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`a first operational
`The circuit arrangement further comprises
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`amplifier. The first operational amplifier includes inputs
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`an
`to the inputs of the amplifier circuit,
`output
`coupled
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`to the output of the amplifier circuit, and a first
`coupled
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`to
`compensation input. The compensation inputis configured
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`feed an offset compensation signal
`to the first operational
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`a first
`amplifier. The circuit arrangement further comprises
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`provide the offset com-
`to
`compensation circuit configured
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`to
`pensation signal. Thefirst compensation circuit is coupled
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`the inputs of the first operational amplifier. The circuit
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`a deactivation circuit which is
`arrangementfurther comprises
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`to
`temporarily deactivate the first compensation
`designed
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`circuit.
`
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`(DE)
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`(30)
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`May 4, 2005
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`
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`Int. Cl.
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`HO3F 1/02
`(2006.01)
`cc ccecneseseeeecteneeerses
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`(52) US. Cd
`330/9; 330/136
`«1.000.000.0000...
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`(58) Field of Classification Search
`330/9,
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`330/129, 136; 327/124, 307
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`See application file for complete search history.
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`References Cited
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`(51)
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`(56)
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`U.S. PATENT DOCUMENTS
`*
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`5,047,727 A
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`Q/1991 Theus
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`330/9
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`17 Claims, 7 Drawing Sheets
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` Page
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`Volkswagen Exhibit 1008
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`Page 1 of 15
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`Jul. 29, 2008
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`Sheet 1 of 7
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`US 7,405,614 B2
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`R2
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`U.S. Patent
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`Jul. 29, 2008
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`US 7,405,614 B2
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`124
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`Sheet 3 of 7
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`US 7,405,614 B2
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`Jul. 29, 2008
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`Jul. 29, 2008
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`Sheet 4 of 7
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`US 7,405,614 B2
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`FIG 5
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` FIG 7
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`U.S. Patent
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`Jul. 29, 2008
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`Sheet 6 of 7
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`US 7,405,614 B2
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`Page 7 of 15
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`U.S. Patent
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`Jul. 29, 2008
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`Sheet 7 of 7
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`US 7,405,614 B2
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`FIG 9
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`Vin
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`8 of 15
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`1
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`
`
`CIRCUIT ARRANGEMENT HAVING AN
`
`
`
`AMPLIFIER ARRANGEMENT AND AN
`
`
`OFFSET COMPENSATION ARRANGEMENT
`
`
`
`
`
`US 7,405,614 B2
`
`FIELD
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`The present invention relates to a circuit arrangement hav-
`
`
`
`
`
`
`
`
`an
`amplifier arrangement, which has an
`operational
`ing
`
`
`
`
`
`
`an offset compensation arrangement
`amplifier, and having
`
`
`
`
`
`
`
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`connected to the amplifier arrangement and serving for the
`
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`
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`offset compensation of the operational amplifier.
`
`BACKGROUND
`
`
`
`
`
`
`
`Such a circuit arrangement is described for example in
`
`
`
`
`
`
`
`Finvers et al.: “A High Temperature Precision Amplifier”,
`
`
`
`
`
`
`
`
`JEEEJournal of Solid-State Circuits, Vol. 30, No. 2, February
`
`
`
`
`
`
`
`1995, pages 120-128. Operational amplifiers in amplifier cir-
`
`
`
`
`
`
`
`
`cuits are
`usually connected up in such a way
`a
`that
`voltage
`
`
`
`
`
`
`ofthe operational amplifier is ideally
`zero.
`betweenthe inputs
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`If the operational amplifier is beset with an
`offset, then an
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`to zero is established between the
`not
`offset voltage
`equal
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`inputs of said operational amplifier, which leads to a corrup-
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`tion of the measurement result. In such circuits, the offset
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`serves to detect such an offset
`compensation arrangement
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`
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`voltage present between the inputs of the operational ampli-
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`an offset compensation signal. Said com-
`fier and to generate
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`pensation signal is fed to an offset compensation input of the
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`operational amplifier in order to
`regulate the offset voltage
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`to zero.
`between the inputs of the operational amplifier
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`This offset compensation by detecting the input voltage of
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`the operational amplifier and generating the compensation
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`on the input voltage may lead to
`signal depending
`problems
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`when a
`frequently changing input signal is fed to the opera-
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`tional amplifier. This is because, in the event ofa level change
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`of the input signal, the input voltage difference of the opera-
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`not zero until the operational
`tional amplifier is initially
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`amplifier has again attained a settled state. This input voltage
`
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`to zero is registered
`as an offset by the
`difference not
`equal
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`offset compensation arrangement and incorrectly leads to a
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`or
`adaptation of the compensation signal.
`change
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`Offset compensation arrangements usually have an inte-
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`grating behavior, which hasthe effect that the offset compen-
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`sation signal increases with the numberof level changes of
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`or with the numberof
`the input signal
`settling operations of
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`the operational amplifier. The consequenceofthis is that the
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`so that precisely
`operational amplifier is “overcompensated”,
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`during the settled state of the operational amplifier there is an
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`offset present which increases as the numberoflevel changes
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`of the input signal increases or as the numberof
`settling
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`
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`operations of the operational amplifier increases.
`
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`
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`a circuit
`to
`Tt would therefore be advantageous
`provide
`
`
`
`
`an
`amplifier arrangement—which has an
`arrangement having
`
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`
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`an offset compensation
`operational amplifier—and having
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`arrangement which does not have these disadvantages.
`
`SUMMARY
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`50
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`60
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`an
`Acircuit arrangementis disclosed comprising
`amplifier
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`arrangement having inputs for feeding in an
`an
`input signal,
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`an
`output for providing
`output signal and havinga first opera-
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`tional amplifier. The operational amplifier has inputs coupled
`
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`an
`to the inputs of the amplifier arrangement,
`output coupled
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`to the output of the amplifier arrangement, and a first com-
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`pensation input for feeding in an offset compensation signal.
`65
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`The circuit arrangementadditionally has a first compensation
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`ofthefirst opera-
`to the inputs
`arrangement, which is coupled
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`2
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`tional amplifier and which provides the offset compensation
`
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`a deactivation circuit is present, which is
`signal. Moreover,
`
`
`
`
`
`
`to
`temporarily deactivate the first compensation
`designed
`
`arrangement.
`
`
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`In the case of the circuit arrangement accordingto at least
`
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`some embodiments of the invention, the temporary deactiva-
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`tion of the compensation arrangement by the deactivation
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`a situation in which, during those time dura-
`circuit prevents
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`tions during whichthefirst operational amplifier settles after
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`a level change of the input signal,
`a
`voltage difference
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`between the inputs of the first operational amplifier is
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`detected as an offset by the compensation arrangement. Such
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`detection of the input voltage difference as an offset during
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`the settling operationsofthe first operational amplifier would
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`lead to an erroneous
`generation ofthe compensation signal in
`
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`the manner
`explained above.
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`to deac-
`The deactivation circuit may suitably be designed
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`on the
`tivate the first compensation arrangement depending
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`input signal. In one
`embodiment, the deactivation circuit
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`deactivates the first compensation arrangement in each case
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`predetermined time duration after a level change of the
`for a
`
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`input signal.
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`as well as
`The above described features and advantages,
`
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`others, will become more
`readily apparent to those of ordi-
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`
`nary skill in the art
`by reference to the following detailed
`
`
`
`
`description and accompanying drawings.
`
`
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
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`FIG. 1 showsa first exemplary embodiment of a circuit
`
`
`
`
`
`to one embodimentof the invention
`arrangement according
`
`
`
`
`
`
`
`an offset compensation circuit
`an
`amplifier circuit,
`having
`
`
`
`
`
`
`
`
`and a deactivation circuit for the offset compensation circuit;
`
`
`
`
`
`
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`FIG. 2 shows, by way of example, temporal profiles for an
`
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`
`
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`input signal of the amplifier arrangement, which signal is a
`
`
`
`
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`across a
`voltage present
`measuring resistor;
`
`
`
`
`
`
`FIG. 3 shows an
`exemplary circuitry realization of an
`
`
`
`
`
`
`
`one offset compensation input;
`operational amplifier having
`
`
`
`
`
`
`FIG. 4 shows a second exemplary embodimentofa circuit
`
`
`
`
`to the invention;
`arrangementaccording
`
`
`
`
`
`
`occur-
`FIG. 5 shows temporalprofiles of selected signals
`
`
`
`
`
`to FIG. 4;
`ring in the circuit according
`
`
`
`
`
`FIG.6 showsa further exemplary embodimentofa circuit
`
`
`
`
`to the invention;
`arrangementaccording
`
`
`
`
`
`
`FIG. 7 shows an
`exemplary circuitry realization of an
`
`
`
`
`
`
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`two offset compensation inputs;
`operational amplifier having
`
`
`
`
`
`
`FIG. 8 showsa further exemplary embodimentofthecir-
`
`
`
`
`
`
`to the invention; and
`cuit arrangement according
`
`
`
`
`
`
`
`FIG. 9 shows, by way of example, temporal profiles of
`
`
`
`
`
`
`
`selected signals occurring in the circuit arrangement accord-
`
`
`to FIG.8.
`ing
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`
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`
`
`In the figures, unless specified otherwise, identical refer-
`
`
`
`
`
`
`
`and
`ence
`symbols designate identical circuit components
`sig-
`
`
`
`
`
`nals with the same
`meaning.
`
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`
`
`DESCRIPTION
`
`
`
`
`
`
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`
`
`Anexemplary circuit arrangement accordingto at least one
`embodimentof the invention as illustrated in FIG. 1 has an
`
`
`
`
`
`
`
`
`
`
`
`
`
`amplifier arrangement 10 having inputs 101, 102 for feeding
`
`
`
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`
`
`
`
`
`
`in an
`input signal Vin and having outputs 103, 104 for pro-
`
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`
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`
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`an
`output signal Vout.In the example, the input signal
`viding
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`Vin and the output signal Vout are
`voltages which are referred
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`in each case to a
`reference-ground potential GND. The input
`
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`102 and the output 104 are at said reference-ground potential
`
`
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`GND. The amplifier arrangement 10 hasa first operational
`
`
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`
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`
`
`amplifier 11 having inputs 111, 112 and an
`output 113. In the
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`example, the noninverting input 111 ofthe operational ampli-
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`fier 11 is connectedto the input 101 of the amplifier arrange-
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`ment 10 via a resistor 14, and the inverting input 112 of the
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`operational amplifier 11 is connected to the input 102 of the
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`amplifier arrangement 10 via a further input resistor 15. The
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`output 113 ofthe first operational amplifier 11 is connected to
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`the output 103 of the amplifier arrangement 10. The output
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`113 of the operational amplifier 11 is furthermore feedback-
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`connected to the inverting input 112 of said operational
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`amplifier via a feedback resistor 13. After application of an
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`a differential voltage Vdiff=0 is established
`input voltage Vin,
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`between the inputs 111, 112 of the operational amplifier 11
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`settling operation has proceeded. In the case of the
`after a
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`circuitry illustrated, the following holds true for the output
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`voltage Vout of the operational amplifier 11:
`Vout=R2/R1
`(1)
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`In this case, R1 designates the resistances of the input
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`resistors 14, 15 and R2 designates the resistance of the feed-
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`backresistor 13.
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`For example due to temperature influences or else due to
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`production-dictated variations in the parameters of the com-
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`ponents present in the operational amplifier 11 (not illustrated
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`an
`offset, that is to say an
`in greater detail),
`input difference
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`Vdiff not
`to zero, may be present in the settled state of
`equal
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`the operational amplifier 11. In order to compensate for such
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`input offset, the first operational amplifier 11 has a com-
`an
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`pensation input 114 for feeding in a
`compensation signal. In
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`is a
`voltage V12
`the example, said compensation signal
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`across a first capacitive storage element, which in the
`present
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`example is connected between the compensation input 114
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`and reference-groundpotential GND.
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`a compen-
`Said compensation signal V12 is generated by
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`sation circuit 20 connected to the inputs 111, 112 of thefirst
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`operational amplifier 11 in order to detect the input voltage
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`difference Vdiff thereof and to generate the compensation
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`on said input voltage difference Vdiff
`signal V12 depending
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`in conjunction with the capacitive storage element 12. The
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`compensation circuit 20 has a second operational amplifier
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`as a transconductance amplifier in the
`21, which is designed
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`an
`output current 120
`example and which thus generates
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`on the input voltage difference Vdiff in order to
`dependent
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`charge the capacitive storage element 12. In principle, the
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`an
`output current
`compensation arrangement 20 generates
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`as the input difference Vdiffofthe first operational
`120 as
`long
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`amplifier 11 is not equalto zero, in order thereby
`to
`change the
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`to a value
`compensation signal V12 until it has been adjusted
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`at which the offset or the input voltage difference Vdiff is
`zero.
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`Since the transconductance amplifier 21 of the compensa-
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`tion arrangement 20 may also be beset with an offset the
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`compensation arrangement 20 has a further compensation
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`arrangement serving for the offset compensation of the
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`transconductance amplifier 21. In accordance with the first
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`operational amplifier 11 of the amplifier arrangement10, the
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`transconductance amplifier 21 has a
`compensation input 214
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`for feeding in an offset compensation signal V22. A second
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`capacitive storage element 22 is connected between said com-
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`pensation input 214 and reference-ground potential GND,the
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`offset compensation signal V22 of said transconductance
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`across said second capacitive
`stor-
`amplifier 21 being present
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`age element. Said second capacitive storage element 22 is part
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`of the compensation arrangement of said transconductance
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`amplifier 21.
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`Said compensation arrangement additionally has a first
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`switch 23 for interrupting the connection betweenthefirst
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`input 211 of the transconductance amplifier 21 andthefirst
`10 of 15
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`US 7,405,614 B2
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`a second switch 24
`input 111 of the operational amplifier 11,
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`for short-circuiting the inputs 211, 212 of the transconduc-
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`a third switch 25 for connecting the output
`tance
`amplifier 21,
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`213 of the transconductance amplifier 21 to the first capaci-
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`tive storage element 12, and also a fourth switch 26 for con-
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`necting the output 213 ofthe transconductance amplifier 21 to
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`the second capacitive storage element 22. Said switches 23,
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`24, 25, 26 of the compensation arrangementofthe transcon-
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`ductance amplifier 21 are driven by switching signals p1, p2
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`a control circuit 200, which is merely illustrated
`generated by
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`are
`schematically. Said control signals p1, p2
`complementary
`to one another and chosen such that the first and fourth
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`switches 23, 25 are
`always opened and closed together and
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`that the second and fourth switches 24, 26 are
`always opened
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`and closed together. In this case, the first and third switches
`on the one
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`hand, and the second and fourth switches,
`23, 25,
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`on the other hand,
`are
`always driven complementarily
`24, 26,
`to one another.
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`The control circuit 200 controls the offset compensation of
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`the transconductance amplifier 21 by the second compensa-
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`a
`tion arrangement. During
`compensation operation in which
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`the compensation signal V22 is generated, the first and third
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`switches 23, 25 are
`opened in order to
`decouple the transcon-
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`ductance amplifier 21 from thefirst operational amplifier 11.
`The second and fourth switches 24, 26 are closed in order to
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`short-circuit the inputs 211, 212 of the transconductance
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`amplifier 21 and in order to connect the output 213 of the
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`transconductance amplifier 21 to the second capacitive
`stor-
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`age element 22. If the transconductance amplifier 21 has an
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`offset, then there is available at its output 213 despite short-
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`an
`output current which chargesthe
`circuited inputs 211, 212,
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`capacitor 22 via the fourth switch 26 in order to increase the
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`second compensation signal V22. Said compensation signal
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`V22 serves for offset compensation internally in the transcon-
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`ductance amplifier 21.
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`The offset of the transconductance amplifier 21 is com-
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`pletely compensated for when the output current of said
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`transconductance amplifier becomeszero
`as a
`result, the
`and,
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`compensation signal V22 does notrise any further. After the
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`conclusion of the compensation operation, the second and
`fourth switches 24, 26 are
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`opened and the first and third
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`switches 23, 25 of the compensation arrangement of the
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`transconductance amplifier 21 are closed.
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`The compensation operation explained above for the
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`at
`transconductance amplifier 21 may suitably be repeated
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`regular time intervals, in which case, during the compensa-
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`tion operation, in the manner
`explained, the second and fourth
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`switches 24, 26 are for example closedfor a
`fixedly predeter-
`mined time duration and the other two switches 23, 25 are
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`opened for this time duration. In a mannerthat is not illus-
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`trated in more
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`specific detail, there is in this connection also
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`a
`the possibility of providing
`discharge circuit for the capaci-
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`tive storage element 22 which completely discharges the
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`capacitive storage element 22 in each case before the begin-
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`ning of a
`to
`compensation operation, in order subsequently
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`a second compensation signal V22 again with the
`generate
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`second and fourth switches 24, 26 closed. It should be pointed
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`out in this connection that the compensation signal V22 is
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`so that
`maintained after the opening of the fourth switch 26,
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`only the first compensation signal V12 is changed during the
`
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`compensation operation.
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`state of the transconductance amplifier in
`An operating
`which the second and fourth switches 24, 26 are closed is
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`referred to below as
`“compensation operating state”, while an
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`state in which said switches 24, 26 are open and the
`operating
`other two switches 23, 25 are closedis referred to as “normal
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`operating state’.
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`20
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`30
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`40
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`5
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`The task of the first compensation arrangement 20 is, in
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`conjunction with the first capacitive storage element 12 con-
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`nected to the offset compensation input 114 ofthe operational
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`an offset compensation signal V12
`amplifier 11, to generate
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`for the operational amplifier 11.
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`In order to generate the first offset compensation signal
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`V12, the transconductance amplifier 21 is operated in the
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`normal operating mode. The transconductance amplifier 21
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`then detects the voltage Vdiffpresent between the inputs 111,
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`an
`112 of the operational amplifier 11 and generates
`output
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`current [20 at its output 213, said output current
`being depen-
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`dent on said voltage difference Vdiff. In the ideal situation,if
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`the operational amplifier 11 is not beset with an
`offset, this
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`input voltage difference Vdiffis zero in the settled state of the
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`operational amplifier 11. In this case,
`the output current 120 of
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`the transconductance amplifier 21 is likewise zero
`provided
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`that the transconductance amplifier 21 is notitself beset with
`an
`
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`offset, which is assumed below.
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`If the first operational amplifier 11 is beset with an
`offset,
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`to zero and
`thenthe inputvoltage difference Vdiffis not
`equal
`
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`
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`an
`output current
`the transconductance amplifier 21 supplies
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`120 not
`to zero, which charges the capacitive storage
`equal
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`to increase the offset compensa-
`element 12 in order thereby
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`tion voltage V12. In this case, the compensation voltage V12
`
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`is increased until the input voltage Vdiff of the first opera-
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`tional amplifier is zero and the offset of the first operational
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`amplifier 11 has thus been compensated for. The first com-
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`pensation signal V12 is maintained if the transconductance
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`amplifier 21 undergoestransition from the normal operating
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`state to the compensation operating
`state and the third switch
`
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`25 is opened.
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`Asalready explained, the input voltage difference Vdiff of
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`zero. In particular
`the operational amplifier 11 is normally
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`
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`settling phase after a
`a
`change in the input signal Vin,
`during
`
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`
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`however, said input voltage difference Vdiff may assume a
`to zero. Unless additional measuresare
`
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`
`
`
`value not
`taken,
`equal
`
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`said input voltage difference Vdiff, during thesettling phase,
`
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`as an offset by the compensation
`would be interpreted
`
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`
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`arrangement 20, which wouldleadto an increasein the offset
`
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`
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`compensation signal V12 of the operational amplifier 11.
`
`
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`
`
`stor-
`The compensation arrangement20 with the capacitive
`
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`
`
`
`age element 12 has an
`integrating behavior, which equiva-
`
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`
`
`meansthat those input voltage differences Vdiff which
`lently
`
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`
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`are not
`to zero would be integrated during thesettling
`45
`equal
`
`
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`
`
`
`
`operations explained and would lead to a continuousincrease
`
`
`
`
`
`
`
`
`
`in the offset compensation signal V12 unless additional mea-
`
`
`
`sures are
`implemented.
`
`
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`
`
`
`
`
`to zero can fur-
`Input voltage differences Vdiff not
`equal
`
`
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`
`
`
`
`source that
`thermore also be generated by the input voltage
`
`
`
`
`
`
`
`
`as is explained below with
`generates the input voltage Vin,
`
`
`reference to FIG.2.
`
`
`
`
`
`
`
`
`a device for generating
`FIG.2 shows, in the left-hand part,
`
`
`
`
`
`
`
`
`an
`input voltage Vin of the amplifier arrangement 20. This
`
`
`
`
`
`
`a measuringresistor
`or shuntresis-
`arrangement 50 comprises
`tor, through which a measurement current 150 flows. It shall
`
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`
`
`be assumed that said measurement current 150 is a
`
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`
`
`pulsed
`
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`
`
`current that is switched on andoff. The amplifier arrangement
`
`
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`
`
`
`
`an
`on said mea-
`10 generates
`output signal Vout dependent
`
`
`
`
`
`
`
`surementcurrent 150 by
`means of the measuringresistor 50.
`
`
`
`
`
`
`a nonreactive resistance
`The measuring resistor 50 comprises
`
`
`
`
`
`
`
`component R50 and a
`parasitic inductance component L50.
`
`
`
`
`
`
`
`
`Asis illustrated in the right-handpart of FIG.2, said parasitic
`
`
`
`
`
`
`
`inductance component leads to
`voltage spikes in the input
`
`
`
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`
`
`
`
`voltage Vin both when the measurement current I50 is
`switched on and when the measurement current I50 is
`
`
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`
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`
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`switched off. Said voltage spikes likewise lead to an
`input
`11 of 15
`
`
`
`
`
`
`6
`
`
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`
`
`
`
`to zero and would beinte-
`voltage difference Vdiff not
`equal
`
`
`
`
`
`
`grated by the compensation arrangement 20 unless further
`
`
`
`measures are
`implemented.
`
`
`
`
`
`
`
`
`In order to avoid a situation in which inputvoltage differ-
`
`
`
`
`
`
`
`
`ences Vdiffnot equal
`to zero which are causedbythe parasitic
`
`
`
`
`
`or
`effects explained
`by settling operations of the operational
`
`
`
`
`
`amplifier 11 lead to a
`corruption of the offset compensation
`
`
`
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`signal V12, the circuit arrangement has, accordingtoat least
`one embodimentof the invention,
`a deactivation circuit 30,
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`to
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`temporarily deactivate the first compen-
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`sation circuit 20. In the example, said deactivation circuit 30
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`has a switch 31, which is connected downstream of an
`output
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`of the compensation arrangement 20 and which prevents, in
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`the open state, a
`changing of the offset compensation signal
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`V12 by the compensation arrangement20. A drive circuit 32
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`is present for driving said switch 31, which drive circuitis
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`to open the switch 31 temporarily, such as
`designed
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`settling operations of the operational amplifier 11 or
`during
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`predetermined time durationsafter changes in the inputsignal
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`to zero which
`Vin. Input voltage differences Vdiff not
`equal
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`occur
`during these time durations thus cannotaffect the offset
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`compensation signal V12 of the operational amplifier 11.
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`In the example, the compensation arrangement20 is deac-
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`output signal which can
`an
`tivated when it does not
`supply
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`change the compensation signal V21 generated up to that
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`point.
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`ofthe function of
`In orderto afford a better understanding
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`the offset compensation signal V12, FIG. 3 shows a
`simple
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`exemplary circuitry realization of an
`operational amplifier
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`an offset compensation input 114. This operational
`having
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`amplifier has a differential amplifier stage having first and
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`second input transistors 121, 122, the control terminals of
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`which form the inputs 111, 112 ofthe operational amplifier. In
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`the example, said transistors 121, 122 are formed as n-chan-
`nel MOSFETs whose source terminals are connected to one
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`another and are connected to
`reference-ground potential
`GNDvia a current source 126 serving
`as a load. The drain
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`terminals of said MOSFETs 121, 122 are connected to a
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`supply potential Vbb via a current mirror having
`two further
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`transistors 124, 125. Said current mirror 124, 125 comprises
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`a first current mirror transistor 124
`two
`p-channeltransistors,
`of which is connected up as a diode. The current mirror 124,
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`125 maps a current
`flowing throughthe first input transistor
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`121 onto a current
`flowing through the second current mirror
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`transistor 125. An outputstage of this operational amplifier is
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`a further n-channel
`formed bya series circuit comprising
`MOSFET123 and a further current source 127. In this case,
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`a
`the output 113 of the operational amplifier 11 is formed by
`node commonto the further transistor 123 and the current
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`source 127. A control terminalof said further n-channeltran-
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`sistor 123 is connected to a node common to the second
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`current mirror transistor 125 and the second inputtransistor
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`122.
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`The operational amplifier has a
`compensation stage having
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`a first compensation transistor 126, which is formed as a
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`p-channel transistor 126 in the example, and a second com-
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`pensation transistor 127, which is formed as an n-channel
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`transistor in the example. The two
`compensationtransistors
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`126, 127 are
`jointly driven by the compensation signal V12
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`present at the compensation input 114. For this purpose, the
`gate terminals of these twotransistors 126, 127 are connected
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`to the compensation input 114. The task of the compensation
`transistors 126, 127 is to reduce or increase the cur