US006049246A
`
`
`
`
`United States Patent 55
`
`
`
`[11] Patent Number:
`6,049,246
`
`
`
`
`
`
`
`
`Kozisek et al.
`Apr. 11, 2000
`[45] Date of Patent:
`
`
`
`
`
`[54] AMPLIFIER OFFSET CANCELLATION
`
`
`
`USING CURRENT COPIER
`
`
`
`
`
`
`
`[75]
`
`Inventors: James R. Kozisek, Chandler; Thomas
`
`
`
`
`W. Ciccone, Tempe, both of Ariz.
`
`
`
`
`
`[73] Assignee: Vivid Semiconductor, Inc., Chandler,
`
`
`
`
`
`Ariz.
`
`
`
`
`
`
`
`
`
`
`
`Allen—Holberg, “CMOS Analog Circuit Design,’ Holt,
`Rinehart & Winston, 1987 pp. 357-360.
`
`
`
`
`
`
`
`
`
`Franca—Tsividis, “Design of Analog—Digital VLSI Circuits
`
`
`
`
`
`for Telecommunications and Signal Processing”; Prentice
`
`
`
`
`
`
`Hall 1994
`(2”@ Edition) pp. 108-112.
`
`
`
`
`
`Gregorain—Temes, “Analog MOSIntegrated Circuits,” John
`Wiley & Sons, 1986, p. 416.
`
`
`
`
`
`
`
`
`
`
`
`
`[21] Appl. No.: 09/210,494
`
`
`
`
`Filed:
`Dec. 11, 1998
`
`
`
`
`
`[22]
`
`
`
`
`Primary Examiner—Michael B Shingleton
`oceccecessssesssseesssssesssseesssseesssseeessseess
`
`
`
`
`Int. C1
`HO3F 1/02
`or
`Firm—Cahill, Sutton & Thomas
`
`
`
`
`
`[51]
`oe
`Attorney, Agent,
`[52] U.S. Che
`
`
`
`
`
`
`
`
`330/9; 330/253; 330/257
`0. eee
`[58] Field of Search
`330/9, 253, 257
`ABSTRACT
`
`
`
`
`
`
`
`References Cited
`
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`wees ceeeeeccneeeteeecneeeeecne ees
`9/1972 LO€SSL
`330/9
`
`
`
`
`....
`7/1973 Aumiaux..
`330/9
`
`
`
`
`
`occ cececestesesteseseseeens
`330/9
`5/1974 Poujois
`
`
`
`
`eee ceecteeeeeeneee’
`10/1976 Ochi et al.
`330/9
`
`
`
`
`
`ww.
`etal.
`1/1978 Dingwall
`330/9
`
`
`
`
`
`ou... eee eeeee
`...
`
`5/1979 Gordon
`330/9
`
`
`
`
`
`.
`...
`12/1981 Dwarakanath et al.
`330/9
`
`
`
`
`
`11/1983 Schade, In ow.
`
`307/353
`
`
`
`
`wee
`ceesceseseeees
`330/51
`1/1985) Miyata
`
`
`
`
`
`...
`...
`etal.
`330/9
`11/1985 Gregorian
`
`
`
`
`
`
`...
`.............
`
`9/1987 Westwick
`330/9
`
`
`
`
`
`1/1996 Genest oe.
`we
`330/253
`
`
`
`
`
`...
`..
`6/1996 Chambersetal.
`327/561
`
`
`
`
`
`
`eee
`2/1997 Hwanget al.
`330/253
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`et al. “A Micropower CMOS-Instrumentation
`
`
`
`
`
`Degrauwe,
`Amplifier”, JEEE J. Solid-State Circuits, Jun. 1985, vol.
`
`
`
`
`
`
`
`SC-20, No. 3, pp. 805-807.
`
`
`
`
`
`[56]
`
`
`3,694,760
`
`3,748,587
`
`3,810,031
`
`3,988,689
`
`4,068,182
`
`4,152,659
`
`4,306,196
`
`4,417,160
`
`4,491,800
`
`4,555,668
`
`4,697,152
`
`5,483,194
`
`5,530,399
`
`5,604,464
`
`
`
`
`[57]
`
`
`
`A differential amplifier circuit achieves offset cancellation
`
`
`
`
`
`
`
`an offset correction current from a current
`
`
`
`
`
`
`
`
`by supplying
`copier circuit to the output of the differential amplifier. The
`
`
`
`
`
`
`
`
`current
`first switch to
`
`
`
`
`
`
`copier is programmed by closing
`
`
`
`
`
`
`
`
`
`short the differential input terminals of the amplifier, by
`a second switch to break the feedback loop of the
`
`
`
`
`
`
`
`
`opening
`a third switch to allow the current
`
`
`
`
`
`
`
`
`amplifier, and by closing
`to sense the offset output voltage
`at the output of the
`
`
`
`
`
`
`
`
`
`copier
`an
`amplifier. The current
`
`
`
`
`
`
`
`
`equal and opposite
`copier generates
`offset cancellation current which is summed with the offset
`
`
`
`
`
`
`
`
`current
`from the amplifier. The current
`
`
`
`
`
`
`
`
`copier circuit
`includes a
`a
`to
`
`
`
`
`
`
`
`storage capacitor for storing
`voltage required
`suchoffset cancellation current. After programming
`
`
`
`
`
`
`
`produce
`
`
`
`
`
`
`
`
`
`the storage capacitor, the third switch is opened, the first
`switch is opened, and the second switch is closed for normal
`
`
`
`
`
`
`
`
`
`operation.
`
`6 Claims, 4 Drawing Sheets
`
`
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`
`
`
`
`
`
`20
`
`
`
`VDD
`
`
`
`1 of 11
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`Page
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`Volkswagen Exhibit 1006
`
`Page 1 of 11
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`Volkswagen Exhibit 1006
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`

`

`
`U.S. Patent
`
`
`
`Apr.11, 2000
`
`
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`
`Sheet 1 of 4
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`6,049,246
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`
`1
`AMPLIFIER OFFSET CANCELLATION
`
`
`USING CURRENT COPIER
`
`
`
`BACKGROUND OF THE INVENTION
`
`
`1. Field of the Invention
`
`
`
`
`to differential
`
`
`
`
`
`
`The present
`invention relates generally
`a differential input
`amplifiers of the type used to
`
`
`
`
`
`
`
`amplify
`an
`a
`
`
`
`
`
`
`
`
`voltage and provide
`output voltage for driving
`load, and
`to an
`more
`
`
`
`
`
`apparatus and method for canceling
`particularly,
`
`
`
`
`
`
`any offsets inherent in such differential amplifier.
`2. Description of the Relevant Art
`
`
`
`
`
`are
`
`
`
`
`
`
`
`
`Differential amplifiers
`widely used within the elec-
`a differential input signal and
`
`
`
`
`
`
`
`
`tronics industry for receiving
`an
`
`
`
`
`
`
`amplified output voltage derived therefrom.
`producing
`Often, such differential amplifiers includea
`or
`
`
`
`
`
`
`
`first,
`positive,
`input terminal and a
`or
`
`
`
`
`
`
`
`
`second,
`negative, input terminal,
`along with a third output terminal. The differential input
`
`
`
`
`
`
`
`
`across the first and second input
`
`
`
`
`
`
`
`
`
`voltage is presented
`terminals, and the output voltage is a function of the
`
`
`
`
`
`
`
`
`
`at the
`
`
`
`
`
`
`
`difference between the absolute voltages presented
`a feedback
`
`
`
`
`
`
`
`positive and negative input terminals. Typically,
`terminal back to the
`
`
`
`
`
`
`
`
`path is provided from the output
`or
`inverting, input terminal to establish the amount
`
`
`
`
`
`
`
`negative,
`of amplification provided by the differential amplifier and to
`
`
`
`
`
`
`
`
`
`
`increase the stability thereof
`a
`or
`
`
`
`
`
`
`
`A perfect differential amplifier would provide
`null,
`
`
`
`
`
`
`mid-range, zeroed output voltage when the magnitudeof the
`input differential voltage is zero.
`However, due to transistor
`
`
`
`
`
`
`
`mismatches, current source
`mismatches, current mirror
`
`
`
`
`
`
`an
`
`
`
`
`
`
`
`
`
`errors, and other imperfections, there is usually
`input
`voltage offset inherently present in most differential ampli-
`
`
`
`
`
`
`
`fiers when used in a feedback configuration. Thisoffset error
`
`
`
`
`
`
`
`
`means that
`must be
`the differential
`
`
`
`
`
`
`
`
`input voltage signal
`non-zero
`or
`
`
`
`
`
`
`
`
`in
`(either slightly positive
`slightly negative)
`to be brought
`to the null voltage.
`
`
`
`
`
`
`
`
`
`order for the output voltage
`This offset error must be compensated if the output voltage
`
`
`
`
`
`
`
`
`is to maintain an accurate linear relationship with the
`
`
`
`
`
`
`
`
`
`
`
`
`
`differential input voltage signal.
`In the past, the most common method of compensating for
`
`
`
`
`
`
`
`
`the aforementioned offset error is to determine the differen-
`
`
`
`
`
`
`
`tial input voltage offset error, and to add or subtract such
`
`
`
`
`
`
`
`
`
`voltage offset error from one of the differential input termi-
`
`
`
`
`
`
`
`
`
`nals. For example, U.S. Pat. No. 4,306,196 to Dwarakanath
`
`
`
`
`
`
`
`
`et al. discloses such circuitry wherein a
`
`
`
`
`
`
`
`
`capacitor is pre-
`
`
`
`
`
`
`
`
`
`charged with the offset voltage and is disposed in series with
`the input signal path. One of the disadvantages of such an
`
`
`
`
`
`
`
`
`approachis the need to insert a
`capacitor within one of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`input signal paths, thereby relying upon AC coupling of
`or the feedback signal
`to the input
`
`
`
`
`
`
`
`
`
`either the input signal
`terminal of the differential amplifier.
`
`
`
`
`Somecancellation circuits require dual or
`
`
`
`
`
`
`
`multiple ampli-
`
`
`
`
`
`
`
`fier stages; obviously, such offset compensation circuits do
`not lend themselves to use within a
`
`
`
`
`
`
`
`
`single stage amplifier.
`Other cancellation circuits require the feedback loop of the
`
`
`
`
`
`
`
`
`to be closed when detecting the offset
`differential amplifier
`
`
`
`
`
`
`
`error; in such instances, significant stabilization time may be
`
`
`
`
`
`
`
`required during the offset detection mode while the feedback
`
`
`
`
`
`
`
`
`
`loop stabilizes.
`
`
`a virtual
`Some known offset correction circuits require
`
`
`
`
`
`
`
`one
`ground circuit in order to
`
`
`
`
`
`
`
`accomplish cancellation, i.e.,
`of the input terminals to the differential amplifier
`must be
`
`
`
`
`
`
`
`
`connected to a reference voltage. However, such circuits do
`
`
`
`
`
`
`not allow the common modeinput
`to the amplifier
`to
`
`
`
`
`
`
`
`
`
`change
`after the offset error cancellation has been performed.
`
`
`
`
`
`
`
`
`Offset cancellation circuits are known wherein the feed-
`
`
`
`
`
`
`
`
`back loop is broken when deriving the offset correction
`
`
`
`
`
`
`
`
`
`10
`
`15
`
`
`
`20
`
`25
`
`
`
`30
`
`35
`
`
`
`40
`
`
`
`45
`
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`
`Page 6 of 11
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`6,049,246
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`
`
`2
`voltage; U.S. Pat. No. 3,694,760 to Loessi is an
`
`
`
`
`
`
`
`example of
`such a circuit. Other cancellation circuits are known wherein
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`offset correction is achieved by generating offset correcting
`
`
`
`
`
`
`
`
`currents, rather than offset correcting voltages; for example,
`in U.S. Pat. No. 3,988,689 to Ochi et al., differential drain
`
`
`
`
`
`
`
`
`
`currents are
`generated and directed back to the positive and
`
`
`
`
`
`
`
`
`
`to
`
`
`
`
`
`
`
`
`terminals of the differential amplifier
`negative input
`achieve offset error
`none of such
`
`
`
`
`
`
`
`compensation. However,
`offset cancellation circuits are believed to
`provide the advan-
`
`
`
`
`
`
`
`
`
`
`
`
`
`tages obtained by the present invention.
`Accordingly, it is an
`object of the present invention to
`
`
`
`
`
`
`
`a
`
`
`
`
`
`
`
`simple and inexpensive differential amplifier cir-
`provide
`cuit which effectively cancels offset error within the differ-
`
`
`
`
`
`
`
`
`
`
`
`ential amplifier.
`It is another object of the present invention to
`
`
`
`
`
`
`
`
`
`provide
`such a differential amplifier circuit wherein both the differ-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ential input signal and the feedback path signal may be
`to the input terminals of the differential
`
`
`
`
`
`
`
`
`directly coupled
`amplifier without the use of any AC coupling.
`
`
`
`
`
`
`It is still another object of the present invention to
`
`
`
`
`
`
`provide
`such a differential amplifier circuit wherein the feedback
`
`
`
`
`
`
`loop settling time of the differential amplifier is not a factor
`
`
`
`
`
`
`
`when detecting the offset error.
`
`
`
`
`
`A further object of the present invention is to
`
`
`
`
`
`
`
`provide such
`a differential amplifier wherein the common mode level of
`
`
`
`
`
`
`
`
`changeafter the offset error
`can
`
`
`
`
`
`
`
`
`
`
`the differential input signal
`
`
`
`
`
`
`
`
`
`has been detected without requiring any resetting of the
`
`
`
`cancellation offset circuitry.
`Astill further object of the present invention is to
`
`
`
`
`
`
`provide
`such a differential amplifier circuit which can be imple-
`
`
`
`
`
`
`mented with a
`relatively small numberoftransistors.
`
`
`
`
`
`
`Yet another object of the present invention is to
`
`
`
`
`
`
`
`provide
`such a differential amplifier circuit that can achieve offset
`
`
`
`
`
`
`
`cancellation with a
`
`
`
`
`
`single-stage differential amplifier.
`Still another object of the present invention is to
`
`
`
`
`
`
`provide
`a method for compensating the offset error of a differential
`
`
`
`
`
`
`amplifier which can be implemented without unduly
`com-
`
`
`
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`or
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`plicating the differential amplifier
`degrading its perfor-
`mance.
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`These and other objects of the invention will become
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`apparent to those skilled in the art as the description of
`more
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`the present invention proceeds.
`SUMMARYOF THE INVENTION
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`Briefly described, and in accordance with a
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`preferred
`a dif-
`embodiment thereof, the present invention provides
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`ferential amplifier circuit incorporating offset cancellation,
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`the differential amplifier including positive and negative
`an
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`input terminals for receiving
`input differential signal, and
`an
`an
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`output terminal for producing
`outputsignal.
`including
`The differential input signal is typically in the form of a
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`differential
`input voltage, and the output signal may be
`viewed as an
`a
`output current for driving
`load, wherein the
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`output current is derived from the input differential voltage.
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`Offset cancellation is accomplished with the aid of
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`a first switch that selectively
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`switching devices, including
`shorts together the positive and negative input terminals to
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`null any input differential voltage thereacross. A second
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`switch selectively couples the output terminal of the differ-
`ential amplifier back to the negative input terminal to open
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`or close the feedback loop of the differential amplifier; the
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`or selec-
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`second switch is closed for closed-loop operation,
`tively opened for open-loop operation. A third switch, to be
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`a role in the offset compensa-
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`described shortly, also plays
`tion scheme.
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`Page 6 of 11
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`6,049,246
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`3
`copier circuit is also included as
`A current
`part of the
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`offset cancellation circuitry and includes an
`input terminal
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`at the output
`for selectively receiving the output voltage
`terminal of the differential amplifier. The current
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`copier
`circuit also includes an
`to the output
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`output terminal coupled
`terminal of the aforementioned differential amplifier for
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`an offset current
`or
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`supplying, 1.e., sourcing
`sinking,
`having
`a
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`magnitude based upon the voltage received by the input
`terminal of the current
`copier circuit. The third switch
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`selectively couples the input terminal of the current
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`copier
`circuit to the output terminal of the differential amplifier
`to
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`“program” the current
`copier circuit. In response to the
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`on the output terminal of the differential
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`voltage present
`a current
`amplifier, the current
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`copier circuit supplies
`equal
`to the offset current
`to the output
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`and opposite
`supplied
`terminal by the differential amplifier. The current
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`copier
`circuit also includes a
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`storage device for storing the voltage
`received at the input terminal thereof
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`The differential amplifier circuit and current
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`copier circuit
`are controlled by
`a control circuit for selecting between a
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`cancellation mode and an
`operating modeofthe differential
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`amplifier. During the cancellation mode, the control circuit
`causesthe first switch to be closed, the second switch to be
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`opened, and the third switch to be closed, for allowing the
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`copier circuit to sense any outputoffset current at the
`current
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`terminal of the differential amplifier with a null
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`output
`differential input voltage during open-loop operation, and to
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`an
`equal and opposite offset current to the output
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`supply
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`terminal of the differential amplifier. During the normal
`operation mode, the control circuit causes the first switch to
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`be opened, the second switch to be closed, and the third
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`switch to be opened, for allowing the differential amplifier
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`to operate in closed loop feedback mode and to
`to
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`respond
`to
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`the differential input voltage while continuing
`supply the
`amountofoffset current to the output terminal
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`programmed
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`of the differential amplifier, thereby canceling any output
`current offset inherent in the differential amplifier.
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`When switching from the cancellation mode to the normal
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`operation mode, the control circuit opens the third switch
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`before openingthefirst switch and before closing the second
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`switch. This causes the input terminal of the current
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`copier
`circuit to be decoupled from the output terminal of the
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`differential amplifier, and allows the current
`copier circuit to
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`sample and store the voltage required
`to
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`produce the desired
`amount of offset compensation current, before returning
`to
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`the normal operating mode of the differential amplifier.
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`the storage device within the current
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`Preferably,
`copier
`circuit is a
`to the input terminal of
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`storage capacitor coupled
`the current
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`copier circuit for sampling the voltage received
`thereby whensaid third switch is closed. The current
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`copier
`circuit includes a current source that is coupled
`to the output
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`terminal thereof, and which is controlled by the voltage
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`sampled by the storage capacitor for supplying the desired
`current.
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`offset compensation
`Another aspect of the present invention is a method for
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`canceling offset current inherent in such a differential ampli-
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`fier. The method of the present invention includesthe step of
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`temporarily shorting together the positive and negative input
`to null any input
`terminals of the differential amplifier
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`differential voltage thereacross. The method also includes
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`the step of temporarily opening the feedback path of the
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`differential amplifier for decoupling the output terminal of
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`the differential amplifier from the negative input terminal
`to
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`thereof, allowing the differential amplifier
`temporarily
`operate in an
`open-loop mode. The method further includes
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`the step of sensing and recording any offset current at the
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`output terminal of the differential amplifier, and providing
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`7 of 11
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`4
`an
`equal and opposite offset cancellation current thereto.
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`Once the desired amount of offset cancellation current is
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`determined, the sensing/recording step is terminated, while
`allowing the recorded offset cancellation current
`to be
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`to the output terminalof the differential amplifier
`to
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`supplied
`cancel any output current offset inherent in the differential
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`amplifier. The differential amplifier is then returned to a
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`normal mode of operation by discontinuing the shorting of
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`the positive and negative input terminals of the differential
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`amplifier, and by reconnecting the feedback path for allow-
`to operate in a closed loop
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`ing the differential amplifier
`manner once
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`again.
`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a circuit schematic of a
`typical differential
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`amplifier circuit constructed from CMOStransistors, before
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`the addition of the offset cancellation circuitry of the present
`invention.
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`FIG. 2 is a
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`conceptual schematic drawing showing the
`addition of three switches and a current
`copier circuit being
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`an offset cancellation current to the
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`programmedto supply
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`output of the differential amplifier.
`FIG. 3 is a
`conceptual schematic drawing similar to that
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`of FIG. 2 but showing the normal modeof operation of the
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`compensated differential amplifier.
`FIG. 4 is a
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`timing waveform showing control signals in
`a control circuit
`the form of clock waveforms generated by
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`in order to
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`properly sequence the opening and closing of the
`three switches shown in FIGS. 2 and 3.
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`FIG. 5 is a circuit schematic showing the differential
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`copier circuit, and a bias circuit for imple-
`current
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`amplifier,
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`menting the offset compensation scheme shown conceptu-
`ally in FIGS. 2 and 3.
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`FIG. 6 is a circuit schematic similar to that of FIG. 5 but
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`with a reduced transistor count achieved by combining
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`together certain transistors.
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`FIG. 7 is a circuit schematic showing the application of
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`the offset cancellation method to a two stage differential
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`amplifier circuit.
`DETAILED DESCRIPTION OF THE
`
`
`PREFERRED EMBODIMENT
`
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`The circuit schematic of FIG. 1 shows a
`typical CMOS
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`or
`folded cascode operational transconductance amplifier,
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`OTA,designated generally by reference numeral 20. OTA 20
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`is a form of a differential amplifier and includes a
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`positive
`terminal 22 and a
`terminal 24 for
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`input
`negative input
`an
`input differential voltage. OTA 20 also includes
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`receiving
`an
`an
`output current and
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`output terminal 26 for producing
`a load
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`resulting output voltage for driving
`(not shown)
`at output
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`connected thereto. The output signal produced
`terminal 26 is derived from the input differential voltage
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`across
`input terminals 22 and 24.
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`applied
`transistors 28 and 30, both shown as
`Differential
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`p-channel devices, share a common node 3 1 and receive a
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`current from current source 32 coupled between common
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`node 31 and positive power supply voltage VDD 34. Ideally,
`input terminals 22 and 24 are
`at
`whenthe voltages
`equal, the
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`current source 32 is divided equally
`current
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`supplied by
`con-
`between transistors 28 and 30, half flowing through
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`ductor 36 and half flowing through conductor 38. OTA 20
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`includes a
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`pair of output legs, the first output leg including
`n-channeltransistor 40, p-channel transistor 42, and current
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`source 44. Output terminal 26 is provided
`at the common
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`node 46 betweentransistors 40 and 42. The second output
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`Page 7 of 11
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`5
`leg includes n-channel transistor 48, p-channeltransistor 50,
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`a
`and current source 52. Bias voltage circuit 54 applies
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`to node 56 to maintain transistors 40 and 48
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`biasing voltage
`in operation. Current sources 44 and 52 sink equal currents,
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`and the sum of the currents conducted by
`current sources 44
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`and 52 is greater than the amount of current sourced by
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`current source 32. Transistors 50 and 42 are
`as a
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`configured
`current mirror, with transistor 42 mirroring the current
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`flowing through transistor 50.
`When the circuit of FIG. 1 is in balance, the currents
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`are in balance; all of the
`flowing through the two output legs
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`current sourced by p-channeltransistor 42 is sunk by
`tran-
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`sistor 40, and the current available to flow out of output
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`terminal 26 is zero.
`across
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`Any differential voltage placed
`input terminals 22 and 24 will steer a controlled amountof
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`current
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`terminal 26. For relatively small
`through output
`differential voltages, OTA 20 behaves very muchlike a
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`current source, or
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`transconductance
`voltage-controlled
`device. Ideally, there is no
`flowing into or out
`output current
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`of output terminal 26 when the differential input voltage
`input terminals 22 and 24 is zero.
`across
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`However,
`applied
`mismatch between current sources
`52/44, current mirror
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`50/42, and the differential pair 28/30 often contribute to a
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`non-zero
`output offset current. This output offset current
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`effectively results in an
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`input offset voltage when OTA 20is
`used in a feedback configuration.
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`This input offset voltage problem may be fundamentally
`viewed as an offseterror in the output current. If one cancels
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`the offset error in the output current, then the input offset
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`one may compensate for any
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`voltage is eliminated. Thus,
`a zero
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`input offset voltage of OTA 20 by first forcing
`across
`mea-
`differential voltage
`input terminals 22 and 24,
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`suring the output offset current
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`produced by such condition
`a copy of such
`at output terminal 26, and then subtracting
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`output offset current from the output of OTA 20. This is
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`35
`essentially the basis of the present invention, and is dem-
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`onstrated conceptually in FIGS. 2 and 3.
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`Within FIGS. 2 and 3, OTA 20 is shown having input
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`to output
`terminals 22 and 24 and output terminal 26 coupled
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`node 46. A feedback path extends between output node 46
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`and negative input terminal 24. A first switch 56 extends
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`ter-
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`between positive input terminal 22 and negative input
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`minal 24 for selectively shorting such input
`terminals
`together in order to null any input differential voltage
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`thereacross. A second switch 58 is inserted within the
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`or
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`aforementioned feedback path for selectively opening
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`closing the feedback path that couples output node 46 back
`to
`negative input terminal 24 of OTA 20. When switch 58 is
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`as shown in FIG. 3, OTA 20 operates in closed-loop
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`closed,
`as shownin FIG. 2, OTA
`50
`fashion; when switch 58 is opened,
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`20 operates in open-loop fashion.
`a current
`to FIGS. 2 and 3,
`Still referring
`copier circuit is
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`current source
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`60, transistor 62,
`conceptually represented by
`copiercircuit hasa first
`and storage capacitor 64. The current
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`terminal 66 for selectively allowing storage capacitor 64 to
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`be connected to output node 46 of OTA 20. The current
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`copier circuit also includes a second terminal 68 coupled
`to
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`output node 46, and to output terminal 26, of OTA 20. The
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`an offset
`function of this current
`copier circuit is to
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`“supply”
`a
`current
`to the
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`magnitude that is equal and opposite
`having
`output offset current of OTA 20. As used herein, the term
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`“supply” could mean either sourcing
`current or
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`sinking
`a third switch 70 is
`current. As shown in FIGS. 2 and 3,
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`provided for selectively coupling first terminal 66 of the
`copier circuit to output node 46 of OTA 20, thereby
`current
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`allowing the current
`copier circuit to
`to the voltage
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`respond
`on
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`output node 46.
`present
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`6
`Current source 60 sources a fixed amount of current.
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`Transistor 62 can be biased to sink an amountof currentthat
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`is either greater than, equal to, or less than, the amount of
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`current source 60. If the output offset
`current sourced by
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`current were zero, then transistor 62 would sink exactly the
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`amountof current sourced by
`current source 60. The voltage
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`at first terminal 66 of the current
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`copier circuit is charged
`across
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`storage capacitor 64. This voltage controls the bias
`across transistor 62, and hence determines the degree
`to
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`which transistor 62 conducts current. Thus,
`the current
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`supplied by the current
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`copier circuit is based upon the
`atfirst terminal 66 thereof After switch 70 is opened,
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`voltage
`capacitor 64 stores the last voltage value present at first
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`terminal 66; in this manner, transistor 62 continues to sink
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`a desired amount of current after switch 70 is opened.
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`FIG. 2 demonstrates the first phase of the offset current
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`In this phase, also known as the
`cancellation scheme.
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`cancellation mode, first switch 56 is closed to null
`the
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`to
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`differential input voltage, second switch 58 is opened
`disconnect the feedback loop, and third switch 70 is closed
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`for allowing the current
`copier circuit to sense, and null out,
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`any output current offset at output node 46. The voltage
`at
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`atfirst terminal 66, will drift
`node 46, and hencethe voltage
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`until transistor 62 is biased in such a mannerthat the net
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`current
`to second terminal 68 of the current
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`supplied
`copier
`the net difference between the amountof current
`circuit
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`(i.e.,
`current source 60 and sunk by transistor
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`sourced by
`62)
`exactly balances any output offset current
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`provided by
`output node 46 of OTA 20. In this manner, the current
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`copier
`an
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`circuit supplies
`equal and opposite offset compensation
`current to output node 46 of OTA 20. This cancellation mode
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`can be performedrelatively quickly because the
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`of operation
`settling time of OTA 20 is not a
`factor, since the feedback
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`loop of OTA 20 has been broken temporarily. The current
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`or program-
`copier needs to be in this cancellation mode,
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`ming mode, only long enough for the currents in the circuit
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`to stabilize.
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`Oncethe cancellation or
`programming mode of FIG. 2 is
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`performed, the circuitry is switched to the normal mode of
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`operation shownin FIG. 3. First, third switch 70 is opened,
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`causing capacitor 64 to maintain the voltage needed to create
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`the offset cancellation current. Next,
`first switch 56 is
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`opened and second switch 58 is closed. Openingfirst switch
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`56 terminates the shorting together of differential
`input
`terminals to
`terminals 22 and 24, allowing such input
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`to the differential input voltage presented
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`respond normally
`thereacross. Closing second switch 58 reconnects the feed-
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`back loop for operating OTA 20 in closed-loop fashion.
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`on
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`Meanwhile, the voltage programmed
`storage capacitor 64
`causes transistor 62 to continue to draw the desired amount
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`of current such that the current
`copier circuit supplies the
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`desired offset cancellation current to output node 46 of OTA
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`20 to cancel the output offset current inherent therein.
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`FIG. 4 showsa series of timing waveformsusedto control
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