(12) United States Patent
`Prohaska et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,289,082 B2
`Oct. 16, 2012
`
`USOO8289082B2
`
`(54)
`
`(75)
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`(73)
`(*)
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`(21)
`(22)
`(65)
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`(60)
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`CIRCUIT AND METHOD FOR ADUSTING
`AN OFFSET OUTPUTCURRENT FOR AN
`INPUT CURRENT AMPLIFER
`
`Inventors: Armin Prohaska, Ulm-Ermingen (DE);
`Terje Saether, Trondheim (NO); Holger
`Vogelmann, Schwendi (DE)
`Assignee: Atmel Corporation, San Jose, CA (US)
`Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`Appl. No.: 12/977,034
`
`Filed:
`
`Dec. 22, 2010
`
`Prior Publication Data
`US 2011 FO148380 A1
`Jun. 23, 2011
`
`Related U.S. Application Data
`Provisional application No. 61/289,846, filed on Dec.
`23, 2009.
`Foreign Application Priority Data
`
`(30)
`Dec. 23, 2009
`
`(DE) ......................... 10 2009 O60.504
`
`(51)
`
`(52)
`(58)
`
`Int. C.
`(2006.01)
`HO3F 3/04
`U.S. Cl. ............................................ 330/288; 330/9
`Field of Classification Search ................ 330/9, 51,
`330/263,265,267, 288
`See application file for complete search history.
`
`
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,410,274 A * 4/1995 Birdsall et al. ................ 330,265
`5,565,813 A 10, 1996 Connell et al.
`6,281,730 B1* 8/2001 Vu ................................ 330,288
`6,819, 182 B2 * 1 1/2004 Sibrai ................
`... 330,288
`8,044,719 B2 * 10/2011 Norimatsu et al. ........... 330,251
`2003/0210092 A1 11/2003 Mehr et al.
`* cited by examiner
`Primary Examiner — Khanh V Nguyen
`(74) Attorney, Agent, or Firm — Baker Botts L.L.P.
`
`ABSTRACT
`(57)
`A circuit and a method for correcting an offset is provided that
`includes a current amplifier and an adjusting circuit for cor
`recting an offset of an output current of the current amplifier.
`Wherein the adjusting circuit has a controlled current source,
`an output of the controlled current Source is connected to the
`current amplifier for impressing an output current of the con
`trolled current source in the current amplifier, an input of the
`controlled current source to form a regulation element of a
`control loop is connected by a first switching device of the
`adjusting circuit to an output of the current amplifier and to
`form a holding element is disconnected from the output of the
`current amplifier by the first switching device. The controlled
`current Source, acting as a regulation element in the control
`loop, is set up to regulate the offset to a minimum by setting
`of a current value of the output current, and the controlled
`current source, acting as a holding element, is set up to hold
`the current value, associated with the minimum, of the output
`Current.
`
`32 Claims, 3 Drawing Sheets
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`Page 1 of 10
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`U.S. Patent
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`Oct. 16, 2012
`Oct. 16, 2012
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`US 8,289,082 B2
`
`1.
`CIRCUIT AND METHOD FOR ADUSTING
`AN OFFSET OUTPUT CURRENT FOR AN
`INPUT CURRENT AMPLIFER
`
`This nonprovisional application claims priority to German
`Patent Application No. DE 10 2009 060 504.4, which was
`filed in Germany on Dec. 23, 2009, and to U.S. Provisional
`Application No. 61/289,846, which was filed on Dec. 23.
`2009, and which are both herein incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a circuit and method for
`setting an offset output current for an input current amplifier.
`2. Description of the Background Art
`A current amplifier (CC-OPV) is known, for example,
`from “Halbleiterschaltungstechnik” (Semiconductor Tech
`nology), Tietze, Schenk, 12" edition, 2002, pages 563-565.
`
`10
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`SUMMARY OF THE INVENTION
`
`2
`The controlled current source, acting as a regulation ele
`ment in the control loop, is set up to regulate the offset to a
`minimum by setting a current value of the output current. The
`minimum offset is achieved when the output current from a
`current amplifier has reached a steady state; therefore it is
`Substantially constant, ideally Zero.
`The regulation function is ended when the steady state is
`attained. The controlled current source, now acting as a hold
`ing element, is set up to hold the output current value associ
`ated with the offset minimum. The controlled current source
`acting as a holding element holds the output current Substan
`tially constant in this regard at least for the duration of an
`amplification of input signals of the current amplifier.
`The object of the invention further is to provide a method
`for correcting an offset of a current amplifier. Accordingly, a
`method is provided for correcting an offset of an output
`current of a current amplifier of a circuit. In this regard, the
`method can be carried out by a control device.
`In the method, a controlled current Source, to form a regu
`lation element of a control loop, is connected by a first Switch
`ing device to an output of the current amplifier. The control
`loop in this case is formed to regulate to a steady state.
`The offset is regulated to a minimum by setting a current
`value of the output current of the controlled current source,
`acting as a regulation element. The current value in a regu
`lated State belongs to the minimum offset. The regulation
`occurs when an input signal of the current amplifier has a
`constant value. Therefore, only a direct current value but not
`an alternating current is present at the input of the current
`amplifier during the regulation. Ideally, the direct current
`value, present at the input of the current amplifier, of the input
`signal is Zero.
`The controlled current source, to form a holding element
`for holding the output current value, associated with the mini
`mum, of the controlled current source, is disconnected by the
`first switching device from the output of the current amplifier.
`In this regard, the current value is held by the controlled
`current source until amplification, following the regulation,
`of a time-variant input signal has occurred at the input of the
`current amplifier.
`The embodiments described hereinafter relate to the circuit
`and to the adjusting method. The functional features of the
`circuit in this regard emerge from the method features.
`Method features can be derived from the functions of the
`circuit.
`In an embodiment, the controlled current source of the
`circuit has a capacitor. The capacitor in this case can be
`formed by an integrated capacitor, for example, a MIM
`capacitor, or by a capacitor of an active component, such as
`the gate-source capacitor of a field-effect transistor. Prefer
`ably, the first Switching device is connected to the capacitor.
`Preferably, a current can be connected for charging the
`capacitor by the first Switching device.
`An embodiment provides that it is possible to control the
`controlled current source by a control Voltage. In this regard,
`the control Voltage can be generated by an element of the
`controlled current source itself.
`According to an refinement, the controlled current source
`has a transistor. The transistor is preferably a field-effect
`transistor. The transistor controls the output current of the
`controlled current Source by a control Voltage at the control
`input of the transistor.
`In another embodiment, it is provided that the controlled
`current Source has a storage device. Such as a capacitor, for
`storing the control Voltage. The output current of the con
`trolled current source can be kept constant in its function as a
`holding element by means of the stored control Voltage. Alter
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`It is an object of the present invention to improve a circuit
`with a current amplifier as much as possible. Accordingly, a
`circuit is provided which can be monolithically integrated on
`a semiconductor chip.
`The circuit can have a current amplifier and an adjusting
`circuit. The current amplifier has a current input and at a
`current output outputs the amplified input current as an output
`current at a current output of the current amplifier. A current
`amplifier for amplifying small input currents can also be
`called an input current amplifier. The adjusting circuit is set
`up to correct an offset of the output current of the current
`amplifier.
`The adjusting circuit can have a controlled current source.
`The controlled current source provides an output current,
`which depends on a control variable, particularly a control
`voltage. The output current of the controlled current source is
`also constant with a constant control variable.
`40
`The output of the controlled current source can be con
`nected to the current amplifier for impressing the output cur
`rent of the controlled current source in the current amplifier.
`Preferably, the controlled current source is connected to an
`output of the current amplifier. Alternatively, the controlled
`current Source can also be connected to an input of the current
`amplifier.
`An input of the controlled current Source, to form a regu
`lation element of a control loop, can be connected by a first
`Switching device of the adjusting circuit to the output of the
`current amplifier. The first Switching device is, for example, a
`semiconductor Switch, particularly a transmission gate or a
`field-effect transistor.
`The input of the controlled current source, to form a hold
`ing element, moreover, is disconnected from the output of the
`current amplifier by the first switching device. The controlled
`current source in the closed switch position of the first switch
`ing device as a first function therefore has a regulation func
`tion as a regulation element of the control loop and in Synergy
`in the open Switch position of the first Switching device as a
`second function has a holding function as a holding element.
`The control loop in this regard can be closed by the first
`Switching device. The control loop is disconnected by open
`ing of the first Switching device. In the disconnected State, the
`output current of the controlled current source acting as a
`holding element for the amplification of a temporally suc
`ceeding input signal is Substantially constant.
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`natively, in a more elaborate embodiment, a digital value as
`well for controlling the controlled current source could be
`stored.
`According to an embodiment, the capacitor of the con
`trolled current source, acting as a regulation element, can be
`connected to the output of the input current amplifier. The
`connection can occur by means of the first Switching device
`for charging the capacitor until a steady state is attained for
`the minimum offset. In the steady state, the charging current
`is reduced to a minimum by the capacitor.
`According to another embodiment, the adjusting circuit
`can have a constant current source, which is connected to the
`current amplifier for impressing a constant current. The con
`stant current source can be connected to an output of the
`current amplifier. Alternatively, the constant current Source
`can also be connected to an input of the current amplifier. In
`this case, the constant current of the constant current source is
`also amplified by the current amplifier. Preferably, the current
`flow, produced by the constant current at the output of the
`current amplifier, is greater than the maximum offset of the
`current amplifier. The maximum offset can be determined, for
`example, by means of a simulation.
`It is provided in an embodiment that an output current of
`the controlled current source, said current which is impressed
`in the current amplifier, at the output of the current amplifier
`causes a current flow that is directed opposite to a current flow
`of the constant current. In this case, the constant current
`together with the offset can be compensated predominantly
`by the current flow caused by the controlled current source.
`The output current of the controlled current source is
`impressed in the output of the current amplifier. Both the
`constant current of the constant current source and the output
`current of the controlled current source are impressed in the
`output of the current amplifier and have an opposite current
`direction. Alternatively, one of the two or both currents of the
`constant current source and the controlled current source can
`be impressed in an input in the amplification path of the
`current amplifier and act according to the amplification in an
`opposite current direction at the output of the current ampli
`fier.
`In an embodiment, it is provided that the current amplifier
`has a first current mirror and a second current mirror for
`current amplification. The outputs of the current mirrors are
`connected to the current output of the current amplifier and
`therefore to the output of the circuit. The first current mirror of
`45
`an amplification can be assigned a positive signal current at
`the current input of the current amplifier and the second
`current mirror of an amplification a negative signal current at
`the current input of the current amplifier. Preferably, the con
`stant current source and/or the controlled current Source are
`connected to the first and/or second current mirror.
`The current amplifier can have a current Summing node
`connected to the output of the current amplifier. Preferably, a
`first current and a second current are Summed in the current
`Summing node. The second current is the constant current of
`the constant current source or is based on the constant current
`of the constant current source. The second current is the
`output current of the controlled current source or is based on
`the output current of the controlled current source.
`The constant current source can be connected to the output
`of the current amplifier directly or via a component, such as a
`field-effect transistor. Preferably, the controlled current
`Source is connected to the output of the current amplifier
`directly or via a component, Such as a field-effect transistor.
`The first current or the second current enters the summation
`with a negative sign. If the constant current Source and the
`controlled current source are connected to the output of the
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`current amplifier, the constant current of the constant current
`source or the output current of the controlled current source
`enters the Summation with a negative sign.
`In an embodiment, the adjusting circuit has a second
`Switching device. The second Switching device is connected
`via an input of the adjusting circuit to the output of the current
`amplifier and to the circuit output. The output of the circuit
`can be disconnected from the output of the current amplifier
`and can be connected to the output of the current amplifier by
`means of the second Switching device. The second Switching
`device is, for example, a semiconductor Switch, particularly a
`transmission gate or a field-effect transistor.
`According to an embodiment, it is provided that the adjust
`ing circuit has a third Switching device. The third Switching
`device is connected to the capacitor of the controlled current
`Source and is formed to discharge the capacitor in the closed
`State.
`In an embodiment, the circuit has a control circuit which is
`connected to the adjusting circuit.
`The control circuit, to control the first switching device,
`can be connected to a first control terminal of the first switch
`ing device. The control circuit, to control the second Switch
`ing device, is preferably connected to a second control termi
`nal of the second switching device. The control circuit, to
`control the third switching device, is preferably connected to
`a third control terminal of the third switching device. The
`control circuit preferably has a number of delay elements for
`a time-dependent control.
`The control circuit can be set up in a first step to disconnect
`the output of the current amplifier from the circuit output by
`opening the second switching device. Preferably, the control
`circuit is set up in a second step to connect the capacitor of the
`controlled current source to the output of the current amplifier
`by closing the first switching device, whereby after the sec
`ond step the capacitor is charged by a charging current and by
`the charging of the capacitor an output current of the con
`trolled current source is increased until a minimum is attained
`at a current value of the steady state of the charging current.
`Preferably, the control circuit is set up in a third step to
`disconnect the charged capacitor of the controlled current
`Source from the output of the current amplifier by opening the
`first Switching device.
`The control circuit can be set up in a fourth step to connect
`the output of the current amplifier to the circuit output by
`closing the second Switching device.
`According to an embodiment, the method has several pro
`cess steps, which are carried out, for example, by a state
`machine or a program sequence in an arithmetic unit. First,
`the third Switching device can be temporarily closed, so that
`the capacitor is discharged via the third Switching device.
`Then, the third Switching device is opened again.
`Next, in a process step the capacitor of the controlled
`current Source is connected to the output of the current ampli
`fier by closing the first switching device. Moreover, an output
`of the current amplifier is disconnected from a circuit output
`by opening of the second Switching device, so that the regu
`lation process produces no desirable output signal. After this
`process step, the capacitor is charged by the charging current.
`An output current of the controlled current Source is increased
`by the charging of the capacitor until the charging current
`attains a minimum.
`In a Subsequent process step, the charged capacitor of the
`controlled current source is disconnected from the output of
`the current amplifier by opening of the first Switching device.
`In a Subsequent process step, the output of the current ampli
`fier is connected to the circuit output by closing of the second
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`US 8,289,082 B2
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`5
`Switching device in order to output a signal, amplified by the
`current amplifier, as an output signal.
`Further scope of applicability of the present invention will
`become apparent from the detailed description given herein
`after. However, it should be understood that the detailed
`description and specific examples, while indicating preferred
`embodiments of the invention, are given by way of illustration
`only, since various changes and modifications within the
`spirit and scope of the invention will become apparent to
`those skilled in the art from this detailed description.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention will become more fully understood
`from the detailed description given hereinbelow and the
`accompanying drawings which are given by way of illustra
`tion only, and thus, are not limitive of the present invention,
`and wherein:
`FIG. 1a shows a schematic illustration of an input current
`amplifier,
`FIG. 1b shows a schematic illustration of an input current
`amplifier with an adjusting circuit for adjusting the offset
`output current;
`FIG. 2a shows a circuit diagram of a first exemplary
`embodiment;
`FIG.2b shows a schematic diagram; and
`FIG. 3 shows a circuit diagram of another exemplary
`embodiment.
`
`DETAILED DESCRIPTION
`
`6
`sistor 111, connected to input 101 of input current amplifier
`100, are used to adjust the voltage at input 101 by means of the
`gate Voltages Vn and Vp. For example, the Voltage at input
`101 is adjusted to half the operating voltage V+/2 by means of
`gate Voltages Vn and Vp.
`Output transistor 124 of the first current mirror is con
`nected via PMOS transistor 131 to a current summing node
`105 and an output 102 of input current amplifier 100. Output
`transistor 126 of the second current mirror is connected via
`NMOS transistor 132 to current summing node 105 and out
`put 102 of input current amplifier 100. Transistors 131 and
`132 are controlled by the gate voltages Vcp and Vcnand cause
`an increase in the output resistance of input current amplifier
`100 (cascode current mirror).
`Further, adjusting circuit 200, which is connected to input
`current amplifier 100 for adjusting and therefore for correct
`ing the offset Ioff, is shown in FIG.2a. Preferably, adjusting
`circuit 200 is formed to adjust the offset Ioff to a minimum,
`preferably to the value of Zero. Adjusting circuit 200 has two
`current Sources, a controlled current source 210 and a con
`stant current source 220, which in the exemplary embodiment
`of FIG. 2a are connected to output 102 of input current
`amplifier 100.
`Constant current source 220 generates a constant current
`I2. Constant current I2 is greater in terms of value than the
`maximum expected offset Ioff. The maximum expected off
`set Ioff can be determined, for example, by simulating pro
`cess deviations. Constant current source 220 in the exemplary
`embodiment of FIG. 2a is connected to PMOS output tran
`sistor 124 of the first current mirror via terminal 203 of
`adjusting circuit 200 and terminal 103 of input current ampli
`fier 100. The output current of output transistor 124 of the first
`current mirror and the constant current I2 are Summed in the
`terminal node. Constant current source 220 is therefore con
`nected via PMOS transistor 131 to output 102 of input current
`amplifier 100. It would also be possible to connect constant
`current source 220 directly to output 102 of input amplifier
`100. In the exemplary embodiment of FIG. 2a, constant cur
`rent source 220 has a current source 224 and a current mirror
`comprising PMOS transistors 225, 226 to generate constant
`current I2.
`Controlled current source 210 generates a controlled cur
`rent I1 as the output current. The controlled current source
`210 in the exemplary embodiment of FIG.2a is connected to
`NMOS output transistor 126 of the second current mirror via
`terminal 204 of adjusting circuit 200 and via terminal 104 of
`input current amplifier 100. The output current of NMOS
`output transistor 126 of the second current mirror and output
`current I1 of controlled current source 210 are summed in the
`terminal node. Controlled current source 210 is therefore
`connected via NMOS transistor 132 to output 102 of input
`current amplifier 100. It would also be possible to connect
`controlled current source 210 directly to output 102 of input
`amplifier 100.
`Controlled current source 210 has a capacitor 212. A volt
`age Uc dropping across capacitor 212 controls output current
`I1 of controlled current source 210. In the exemplary embodi
`ment of FIG. 2a, an NMOS transistor 213 is provided as an
`element for Voltage-current conversion. The Voltage Uc drop
`ping across capacitor 212 in this case is present as gate-source
`voltage at NMOS transistor 213. If the voltage Uc dropping
`across capacitor 212 is Zero, NMOS transistor 213 blocks.
`With an increasing Voltage Uc, the gate-source Voltage
`increases and turns on NMOS transistor 213, so that output
`current I1 also increases. Output current I1 increases until the
`sum of the amplifier-intrinsic offset Ioff, constant current I2.
`and output current I1 of controlled current source 210 reaches
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`A current amplifier 100 with a low input impedance is
`shown schematically in FIG. 1, which is also called an input
`current amplifier below. Current amplifier 100 has a current
`input and a current output. The input current through the
`current input in this case is output at the output amplified by
`the current amplification of the current amplifier. In this case,
`a signal output current Ioat the circuit output is Superposed by
`an undesirable offset Ioff at the output. The offset Ioff is
`caused by process variations during the production of ampli
`fier transistors of input current amplifier 100 and is shown
`schematically in FIG.1a as current source Ioff. The amplifier
`inherent offset Ioff in this case can be positive or negative in
`regard to the current direction at the circuit output.
`To correct the offset Ioff at the circuit output, an adjusting
`circuit 200, which compensates at least predominantly the
`Offset Ioff at the output of the circuit and in the ideal case
`subtracts completely the amplifier-intrinsic offset Ioff, is pro
`vided in FIG. 1b.
`An example for an input current amplifier 100 with a low
`ohmic input impedance at the current input of current ampli
`fier 100 is shown in FIG.2a as a circuit diagram. Further, an
`exemplary embodiment of an adjusting circuit 200 for adjust
`ing the offset Ioff of input current amplifier 100 is shown in
`FIG. 2a. PMOS transistors 123 and 124 form a first current
`mirror of input current amplifier 100 with a first transforma
`tion ratio. The first current mirror 123,124 is connected to the
`supply voltage V+. NMOS transistors 125 and 126 form a
`second current mirror of input current amplifier 100 with a
`second transformation ratio. The second current mirror 125,
`126 is connected to ground. In the ideal case, the first trans
`formation ratio and the second transformation ratio would be
`precisely the same. Because of process deviations during
`production, the first transformation ratio and the second trans
`formation ratio, however, do not turn out precisely the same
`and therefore cause the offset Ioff at the current output of
`current amplifier 100. PMOS transistor 112 and NMOS tran
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`7
`a minimum. Capacitor 212 is no longer charged and the
`Voltage Uc is constant. An especially rapid adjustment of the
`steady state is achieved in this way, so that the time during
`which the input current amplifier is not available for current
`amplification of the input signal Isig is minimized.
`Constant current source 220 and controlled current source
`210 in this regard are connected to output 102 of the input
`current amplifier 100 in such a way that the constant current
`I2 and output current I1 of controlled current source 210 are
`Summed, whereby one of the two currents enters the Summa
`tion with a negative sign. The current direction, acting in node
`105 and therefore at output 102, of the constant current I2 and
`the current direction, acting in node 105 and therefore at
`output 102, of the output current I1 of the controlled current
`source 210 are therefore opposite. If the technical current
`direction in FIG. 2a is considered, constant current I2 flows
`into summing node 105. In contrast, output current I1 of
`controlled current source 210 flows out of summing node
`105, therefore enters the summation as negative.
`As an alternative to the exemplary embodiment of FIG.2a,
`constant current source 220 and/or controlled current source
`210 can be connected to current input 101 of current amplifier
`100. If constant current source 220 is connected to input 101,
`constant current I2 is amplified by current amplifier 100. If
`controlled current source 210 is connected to input 101, the
`output current I1 thereof is amplified by current amplifier
`100. If both constant current source 220 and controlled cur
`rent source 210 are connected to current input 101, a differ
`ence current (I1-I2) between constant current I2 and output
`current I1 of controlled current source 210 is amplified
`accordingly by current amplifier 100. In these three embodi
`ment variants as well, a regulation of the offset Ioff to a
`minimum is possible, so that in the case of amplification of an
`input current signal Isig no or only a negligible offset Ioff
`interferes with the output signal Io of the circuit.
`Constant current I2, which is greater than the offset Ioffin
`value, is impressed on output 102 of input current amplifier
`100 by adjusting circuit 200, shown in FIG. 2a, for adjusting
`the offset (Ioff. Likewise at output 102 of current amplifier
`100, output current I1 of controlled current source 210 is
`impressed with the current direction opposite to I2. Adjusting
`circuit 200, moreover, has a first switching device S1 and a
`second switching device S2. First switching device S1 in this
`regard is connected to output 102 of adjusting circuit 200 and
`to an input 219 of controlled current source 210. In the closed
`state, first switching device S1 connects output 102 of adjust
`ing circuit 200 to input 219 of controlled current source 210
`and forms a control loop, whereby controlled current Source
`210 acts as a regulation element of this control loop. In said
`control loop, the actual value is the current Ic through termi
`nal 102, which also charges capacitor 212. Current Ic is the
`same as the current through current output 102 of current
`amplifier 100 and therefore the same as the resulting offset
`Ioff, which is minimized by the regulation. The actual value is
`compared with the target value Zero, the generation of which
`requires no component. The control variable of the control
`loop is output current I1 of controlled current 210.
`For regulation, second Switching device S2 is open and
`disconnects output 202 of the circuit from output 102 of
`adjusting circuit 200. The input signal current Isig is Zero in
`this case. As a result, the resulting current, which results from
`the summation of the output current of first current mirror
`123, 124, of the output current of second current mirror 125,
`126, and of constant current I2, flows out at output 102 of
`input current amplifier 100. Output current I1 of controlled
`current source 210 is equal to zero because of the initially still
`discharged capacitor 212.
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`By charging capacitor 212 by charging current Ic, the gate
`of NMOS transistor 213 is controlled so that the controlled
`current source 210 as a regulation element sets a current value
`of output current I1 of controlled current source 210, so that
`the current through output 102 is regulated to a steady state,
`whereby output current I1 of controlled current source 210
`again draws off specifically the Sum of constant current I2 and
`the amplifier-intrinsic offset Ioff. In this case, the offset Ioff
`active at output 102 is regulated to a minimum and thereby to
`a constant value, ideally Zero. In the steady state, the current
`value of output current I1 of controlled current source 210 is
`COnStant.
`The amplifier-intrinsic offset Ioff can be positive or nega
`tive. Capacitor 212 and NMOS transistor 213 form the regu
`lation element of the control loop. In the steady state, output
`current I1 is equal to the (signed) sum of the constant current
`I2 and amplifier-intrinsic offset Ioff. In the steady state case,
`therefore, a constant current no longer flows out of output 102
`of input current amplifier 100, so that charging current Ic as
`well is zero.
`A diagram for the control signals of Switching devices S1,
`S2, and S3 of adjusting circuit 200 is shown schematically in
`FIG. 2b. Between time points t1 and tak, second switching
`device S2 is opened and disconnects circuit output 202 from
`output 102 of input current amplifier 100. Before, during, or
`after the opening of second Switching device S2, a third
`switching device S3 is closed, which in the closed state short
`circuits capacitor 212, so that capacitor 212 discharges via
`third switching device S3 between time points t2 and t3.
`At time point t5, both second switching device S2 and third
`switching device S3 are in the switch position open “0” In
`contrast, first switching device S1 between time points t5 and
`t6 is controlled into the switch position closed “1. Between
`time points t5 and to, capacitor 212 is connected via first
`switching device S1 to output 102 of input current amplifier
`100. Between the time points t5 and to, therefore, as previ
`ously described, capacitor 212 is charged until the steady
`state is attained.
`At time t0, first Switching device S1 is opened and again
`disconnects capacitor 212 from output 102 of input current
`amplifier 100. Only a very low leakage current thereby flows
`through capacitor 212, the gate of transistor 213 and first and
`third Switching device S1,