_j··
`
`·eESl. COP:·'
`
`r
`
`Boutidary�Scan.Test·
`
`Appro�ch·
`A �racticcil
`
`. .
`
`·.
`
`.
`
`'I
`
`by
`
`Harry Bleeker
`
`Eijnden
`Peter van den
`
`FlulcelP/iili
`Measurement,
`ps Test·&
`TIie Ne1herlands ·.
`Eindlioven,
`
`Frans de Jong
`
`Philips Research Laboratoriq, ·
`TIU! Netherlands
`Eindlwven,
`
`,·
`
`j
`
`I·· .
`
`KLUWER ACADEMIC PUBLISHERS.·
`
`OORDRECHT I BOSTON I LONDON
`
`IPR2021-01488
`Apple EX1003 Page 1
`
`

`

`0-7923-9296-5
`
`. J
`
`,· Published-by Kluwer A�emic Publishers,
`
`
`P.O. Box 17, 3300 AA Dordrecht, The.Netherlands.
`Kluwer Academic Publishers incorporates
`
`the publishing programmes of ·
`.
`.
`. · D. Reidel, Maninus Nijhoff'. Dr W. Junk and MI'P Press. _
`
`Sold and distributed in the U.S.A. and Caruiaa
`· by Kluwer Academic.Publisliers, ·
`101 Philip Drive, Norwell'. MA 02061,.U.S.A.
`
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`In allother' countties. sol_d and disttibuted
`
`. by Kluwer Acadcmfc Publishers Group,
`-P.O. Box 322, 3300 AH Dordrecht;.Th � Netb_er1ands.
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`· Printe.d on t/cid-free pape;
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`· © I 99 3 Kluwer Academic-Publisilcrs and copyright, holders
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`·as specified on appropri:11e pages within:
`or may be reproduced No part of the material protected by this copyright notice
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`.- . . . l .
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`.I !­
`
`i
`
`I
`. I
`
`·r
`
`UST OF FIGURJ
`
`PR.EFACE
`
`·,
`
`I-. .. , I
`
`-1-
`
`·PCB TESTING
`· l'vllN1A TURIZA'
`ROAD BLOOO
`THE SOLUTIOt
`Test Control
`
`. Example. Bou
`
`·"constituent E.
`
`THE BO_UNDARY-�
`THE BST ARCHJ.
`TEST ACCESS pr
`TAP CONTROLL
`State Descripci,
`THE INSTRUCT!
`TEST DATA REC
`.The Bypass R�
`Tlfe Boundary­
`A Bound.,ry-S,
`Sys11:m Pin Rt:
`
`IPR2021-01488
`Apple EX1003 Page 2
`
`

`

`/
`
`f
`
`Chapter
`l
`
`,·
`
`PCB TESTING
`
`Pntdic:al Approach
`
`l.e for small' volume
`. he whole PCB· life
`.!chnology.
`it is an' . ·
`lobaJ strategy
`of. a
`
`has lead to a world
`I� designs allows
`epare StafJdard test.
`duct.
`
`MINIATURIZATION IN ELECTRONICS
`
`Primed Circuit Boards (PCBs) add the most valu�-to
`electronics
`hardware.
`Over the
`PCBs have become loaded with more components
`years.
`and hence have become
`increasingly
`complex and expensive.
`This -is main'ly caused by the ongoing·
`miniaturization in electronics.
`
`', .
`
`.
`
`.
`
`er 1 states the PCB
`the standard for the
`, the innovations
`for
`Jpments in BST are·
`have been obtained :,
`5 describes
`various
`·;tion fauJts are met, ·
`ed. Chapter
`6 gives:
`trod.ucing
`BST in a
`g aspects:
`The _book
`UJck reference.
`
`;tanding o'f ICs and
`
`- 1.'
`
`·. t technological
`level
`ussions
`and positive'
`hould be mentioned
`1d_. h� conscientious
`1 to Rien van Erk for
`cl probably
`l)Ot have
`
`, .
`
`I
`
`Fig. 1�1 . A printed circuit ��d containing ASICs
`
`, / To start· with, the miniaturization within integrated
`circuits (ICs)'
`themselves
`has
`progressed into the sub-micron
`technology. Th.is has led to an increased number of
`gates and a very large number of functions per chip. Consequently,
`many more pins
`per IC are needed and hence ICs come in bigger packages with more leads (>500
`· pins) at smaller
`pitches
`(0.3 m�). Thi:refore. the di�tance between the foot prints ·
`·
`·
`of the I
`Cs on the PCB is becoming
`eqtially small.
`
`. .
`
`:
`
`.
`
`.
`
`I
`
`IPR2021-01488
`Apple EX1003 Page 3
`
`

`

`.
`
`.
`
`Bound.'iry-Sc� Test: A
`: 2.
`Practitai
`Approach.
`mounting of c�ips on both sides of the PCB. using Tape Automated
`. · Dtrect
`Bondine
`' (TAB). Chip On Board (COB) etc .. have caused further miniaturizatio
`n· of th�
`·
`·
`·
`· · ·
`hardware i_mplc;:mentation.
`·' · ·
`To_ even further· increase
`the number ofelectronic
`.furictions
`p�r unit of surfac;,
`are becoming available: Multi Chip Modules (M
`CMs). These are
`· · other technologies
`
`built up of d.ies.d.irec�y mounted on top of se..imtl dielectric and
`. functional inodules
`
`
`layers supponed by_ a,.ceramic multi_�layer substrate.
`metalli_zatiQn
`The component
`is very high and accessibility
`other than via the input and output pins of the
`density
`MCM is non-existent. . . . . . .
`
`...
`. Figure 1-2 shows the. �uction of �ce distances �n PCBs and in res. ·
`
`.
`
`.
`
`'
`
`.
`
`. .
`
`Trace distance
`
`1 mm----------------- ---.
`
`'- -- ------
`1970
`
`---------
`
`--'--'-►Time
`1990
`
`of trace dist.artce� on PCBs and in res
`Fig. 1-2 Reduction
`
`Sub-micron
`region
`
`/(
`
`.
`
`. . .,. \·
`
`' . . .
`
`.
`
`.
`
`�
`
`y, a part ·of a PCB and a part or' ari IC which
`· Figures 1-3 and 14 show� respectivel
`
`
`is · soldered onto � PCB. Th�e 'picrur\:S are: taken with a Scanning· Electron
`Microscope an� th�itch of the JC�s �on tact pins is 25 _inil (= ¼o inch ;= 0.63_ mm).
`The <ingoing minia�ion has made it more and more difficult to ac6ess these
`
`
`
`
`
`. · "highly loadeq" PCBs mechanica).ly;,wilh fi,:tures, for in-circuit testing. Moreover.
`
`
`the test equipment became so expensive in the 1980s that it severely
`affects the
`
`
`
`
`profitability of producing PCBs. Electronic companies were: therefore, looking for
`
`
`
`
`low�cost test methods based on the sofar haid.ly·explored design for-testability .
`. ·. .
`
`..
`
`C
`
`IPR2021-01488
`Apple EX1003 Page 4
`
`

`

`· '
`
`_A Practical Approach
`Bonding
`� Automated
`1iniaturization
`of the
`
`; per Wiit of surface, •
`:s (MCMs). These•are'
`·.
`and ·_
`seve� dielectric
`·u-ate. The· component
`ind 9utput pins of the
`
`nd in ICs ..
`
`'·
`
`\..
`
`Sub-micron
`region
`
`---►-Time
`
`, part of an IC which
`·i Scanning Electron
`1/4-0 inch = 0.63 mm).
`
`·icult to access ·these'
`·
`Moreover,
`. !i� testing.
`severely affects the·
`here fore, looking for
`ign f�r:_testabilit
`y.
`
`. I
`
`·PCB Testin'g
`
`,..
`
`3
`
`picture of part of a PCB · · ·
`micr9scope
`Fig. 1-3 Electron
`
`,.,.. - ..
`
`JC on. a PCB.
`micro�cope picture of._a soldered
`Fig. l-4 Electron
`
`·'
`
`,I
`
`i.
`
`IPR2021-01488
`Apple EX1003 Page 5
`
`

`

`. : r
`
`.J
`
`
`
`.r
`.....
`
`' '
`
`Bou .....
`,y-Scan Test: A Practical Approach ·
`. -. .
`Figure· 1.:5 · show.s. a' �wing of some different test:
`pin� used in a bed-9f-n;:uls
`test pins is 1/,i." and they have a diameter of about 0.8 m·m.
`fixture .. Tiie pitch of-the
`
`'4
`
`.
`
`.'
`,. • ,,...
`
`·
`
`.
`
`: '
`
`. .
`
`.
`
`j
`
`I·
`
`.
`:
`'
`
`·-
`
`testing,
`
`Fig. 1-5 . ConvenµonaJ test pins for. a bed-of-nails fixture
`
`
`
`riot be used (oqesting
`plll,'poses at the re· connections
`
`
`-_--_ It is clear.that these pins:can
`_.·in figure ·1-4, where _the pitch,
`was 0.63·mm...
`
`ROAD Bl:.OC�S FOR CONVENTIONAL PCB TEST METHODS.
`
`I _ With in-circuit physical cont.-ict is .made
`
`to the ·components (for ex�ple
`·-·IC.s) and the copper tracks on _the PGB (test pads} by .mean� of probes_ or bed-of­
`, nails t�hnology.
`
`Input'signals are applied to the component's input pins via probes
`
`
`· � examined through the probes or or needles. 0�d the respon�e _ a� ,the output pi_ns
`
`
`
`needies. For the plated thro.ugh' hole (PTH) ·technology this method was easy to
`
`
`
`-perform. But the continual miniatwi�-ition cn�med the first obst.icle to in-circuit
`· · ·
`·
`· tes.ting. ·
`
`
`
`- . ·.The PCB technology with surface m·ounted d�vices (S"iVIDs}" on· both si4es of the _
`
`
`probing be5=omes pmctically impossible.
`
`
`
`:; :PCB,is another· reaso_rqvhy mechanical
`
`
`cuit ·testing (IC·�. th�· use -�f stait�d-'test �att�m sets
`-�ext. .the.advruH����,u\.-di
`
`
`have evaporated . ,for ICs. from which a-test progr.lJ'T! could e;isily be :\SSemblecl'
`due
`
`
`
`
`
`·a Each' ASIC •requires Specific !Cs (ASI<;:s). to the increasing use of Application
`separate .test-set wt:iich· is not con�'lined -in the -ii�rary of Sf:lllldard tcisf se!5:
`The
`
`
`
`vendor of the •in-circuit._test library is unable to supply these tests: Test sets for
`av�lable or' very
`
`
`are· not ·complex standard � SI devices· (.e.g. ·microprocessors)'
`ex(ll!nsive.·-
`
`i
`
`.• I
`
`IPR2021-01488
`Apple EX1003 Page 6
`
`

`

`. .
`
`l
`
`
`: A Practic;al Approach
`used in a bed-of-nails
`meter of about 0.8 mm.
`
`.. -: PCB Testing
`. Finally, VLSis require long test sequences. for instance,' for in.itialization'. If outputs:.
`
`
`
`
`
`
`of .I Cs are forced (back�driven)' during such a sequence, there may be an impact on .
`
`
`
`the overall reliability of the PCBs.
`
`Summarizing, the'prqpming ofautomiuii:: test equipment (ATE), the mechanicai
`
`
`
`
`
`
`test access· and the quality of testing in the conventional way are reaching th�ir
`· · ·
`
`
`limits of feasibility. ·
`
`. The solution to these problems aris es from the IC test technofogy.
`
`To overcome the
`technology in the
`
`test p�ep:iration and fault coverage problems· faced in the IC-test
`
`
`70's, the scan test technology evolved and became a good solution for digital
`
`
`
`The enormous increase in:observabiljtyand conircillability achieved by
`electronics.
`
`
`
`scan technology forms the base f�r Boundary-Scan Test technology for PCBs. •
`
`i
`
`THE SOLUTION FOR PCB TESTING
`
`:s at the IC connections
`
`METJ-JODS
`
`·. mponents (for example
`
`ns of probes or bed..:of-.
`:·s input p�s via probes .
`.1 through the probes or
`;is _method was easy to
`
`·,t obstacle to· in-circuit
`
`
`itli sid�.s of the
`is) on bc
`!y impossib,le.
`iractical
`. ;tandard test pattern sets ·
`. !d. have ev.aporated due ·
`; . Each ASiC requires a.
`. · st,aridard test sets. The
`tests. Test sets for.
`. i�se
`
`e not �vailable or very
`
`The main ·pqint'to ensure while manufacturing a PCB is to make sure that all
`
`
`. properly at the right place. on the . board and that the
`
`components are mouitted
`
`
`
`
`interconnections between the components are as prescribed in µte design. So, after
`
`
`
`production. one of the main items toJ,e ·tested·.is whether or not the connections·
`between the_ components (for �xample !Cs) _are. 100% correct
`.
`
`The basic idea to circumvent the above mel)tioried access problem for test purposes'
`(i/0) pin of. the component.
`
`was• to. add a shift register cell next to each inputioutput
`
`
`During _test mode these cells are used �o control the status of an output pin (high· or
`low) and read tile smtes of an input pin (high or· low). Tbis allows for testing the
`
`-the board interconnections. puring nonnal mode the cells are 'transparent'.
`cei�s. Figure 1-6·Figures l-6 and 1-7 show the id� of adding the shift regi$ter
`
`
`
`
`'depicts three ICs with ··manY:'intercon�ctions. 'I)te input signals (I) and the Qutput
`
`at the board. edge connector .. ·
`
`
`signals (Q). are the I/0 signals present
`
`In figure 1-7 s�ift registb· �ells have been added between the IC;s 'core logic' and•·
`
`. the I/0 l)ins to prc,:,vide a serial test dati'path through all !Cs;
`
`
`Since the shift �gister cells _are located at the IC;s. boundary (I/0 pins) ,these cells
`
`to � Boundary:s�an CJlls (BSCs) and the comp�ed shift register is
`are referred
`
`
`
`
`called the I3oilndary-Scru1 Register (BSR): According oo· the IE:Eµ:.Std 1149.1. [l], ·
`
`the input to the serial test dam path is called Test Data Input'('I:1>1) and the· output
`.· . ·· · ·
`. . ..
`.
`. '. · .
`is called T�t Da�-i.Output·(TDO).
`
`
`
`To pennit testing of the f?CB's connecting copp�r �ks. the intetconnections, the
`test �tion5..
`
`cells must support tJte followi�g.
`
`IPR2021-01488
`Apple EX1003 Page 7
`
`

`

`.. 6
`
`Bot.. .y-Scan
`Tesc A.Practical Approach
`.
`
`- .
`
`I.
`
`..........
`
`. .eor.
`
`/ - '
`: .,_
`. '� .IC.
`
`'
`
`Core
`laQic
`
`0
`
`'
`
`I
`l,, . '
`0
`Cora
`,___.,_-t l.OQC I---+--(, ..
`
`Fig. 1-6 Many interconnectio·ns
`three ICs
`between
`101_
`� A . ...:IJt-+--...,....-1-
`-- ---f
`)Cor e
`0
`--➔ )H � Core. 1--E· H---r--+--t-
`.... -C
`J,..
`--� _);_ logic 1-,...1)1-+- __ -t--t--+----f
`l�
`L.oQic .)
`�=
`I
`
`... . ...-+:--
`
`,,
`
`Bou,mmv-5can
`Cal
`
`1-'"'LHt--,--
`t-
`,__ __ J ,_H �-1-)1 J-tl-- -0
`-y )
`'-
`�,,
`L-.---...-�� � :)
`Added sllift registers provide
`scan path ·
`
`Ji'.ig. 1-7
`
`.
`
`f·
`
`.
`
`.
`
`TD[ through the regi�teh to the
`dfil.'l in froni.'
`sllift stimulus
`Action: l. ·. :shift-DR:
`cells related with. the outp�t pins of the IC(s).
`Update�DR: update these ourput1cells and apply t�e stimuli to the board.
`· Action 2. .
`interconnections.
`of the board's _interconnections
`at the
`caprure the status
`Action 3. Capture-DR:
`input pins of-the receiving
`IC(s).
`the' BSR towards TDO for
`out the• �esults. thro-�gh
`Action 4. Shift-DR: shif�·
`examination.
`
`<
`.···
`
`IPR2021-01488
`Apple EX1003 Page 8
`
`

`

`
`
`: .� Practical Approacfr·
`
`PCB Testing
`
`.( ,•
`
`7
`
`TOI
`
`BS Call IC
`
`TOO.
`
`-]
`
`.
`0,
`--
`
`J
`
`. Interconnection·
`· to be tested.
`Action .1,: shift test d.-ita to output cell
`Fig. 1-:8
`
`TOI
`
`TOO
`
`Actions 2+3:. apply test data and capture result
`Fig. 1-9
`
`
`
`..
`
`,.·
`
`• I
`
`
`
`h .. the registers to the
`
`e stin:t uiito the b9ard
`
`i
`
`. terconnections at the
`
`t towards TDO for
`
`Fig. 1�10 Action 4: shift captured results out ·
`
`IPR2021-01488
`Apple EX1003 Page 9
`
`

`

`. Boundary-.,..:an
`Test: A Practical Approach
`
`I
`
`1-8, 1,9. and 1-W depict the r�spective
`Figures
`test actions.
`The test stimulus .is
`· ·
`
`
`indicated here as a ·bit of. value .'O' in the �oundruy-Scan path.
`
`Note that the actions 2 and 3 perfonn the acu.ial
`test: apply test data to the PCB
`tracks between the res and capture the status ·of these tracks. The two shift actions
`
`(I and 4) do not in fact contribute to the test results.
`
`ction between· the res is ·referred-to as external test or .
`Testing
`of the in_terconne
`EXTEST. The circuit diagram in figure l�ll supports these functions.
`�
`.
`. "",. I
`r ----; -,. "';."' •"' "'•
`•"' •"' • ',,°
`, .. r '
`.
`·, '
`
`. . .
`
`.
`
`I
`
`l�ul
`
`,·
`'
`'
`
`'
`
`MUX
`
`MUX '
`,0
`
`'
`
`!Outcut
`
`---------------------------
`----------------
`---·
`-------
`·-----·---------
`
`Fig. 1-11 Components of a Boundary-Scan Cell in an IC
`
`� . - . . . =
`
`Figure 1-12 shows the data flow during the first test action, shift the.stimuli (data)
`
`
`
`
`
`through the registers. from input TDI to the output TOO. This action is called Shift­
`
`DR. The �mboldened lines between TDr and TDO plus the shaded Boundary-Scan
`the signal· path.·
`depict_
`(BS) registers.
`
`lrcM
`
`,----.---
`
`�---.. ;'! MUX
`
`
`
`Fig. 1-12 ShiftDR state
`
`Ooci<
`
`TOO
`
`.1
`l
`
`IPR2021-01488
`Apple EX1003 Page 10
`
`

`

`'
`·•
`
`.(
`
`PCB. Testing
`A Practical App�oa��
`Notice tha� in figure 1-12 ,the Boundary-Scan· qesign · comprises,,.
`a p�el .hltch
`;, The test stimulus
`·is
`r stages. The
`(MUX) in addition to the shift-registe
`(flip-flop) and a multiplexer
`1th.
`to �sure ·a stable signal at the parallel outputs while data
`latches have been included
`(test stimuli and test results)
`the scan path (8,SR). The pµrpose
`are shifted through
`. . .
`is discussed later: ·, . .
`of the multiplexer
`The figuresl-13 and 1-14 show the si��a.l flows fo
`r Update-DR (abov� Actio� 2)
`. and Capeilre-DR (above Action �) respectively. ·
`
`·test data to the PCB
`. The two shtft a�tjons.:
`
`. to .as· external test or
`:·unctions.
`
`.
`
`._
`
`•
`
`.,
`
`.
`
`MUX
`
`·: Ouo.,1
`
`TOI
`
`Upill,lte-DR state for EXTEST
`.. Fig� 1-13
`
`lift the stimuli .(data)
`is called Shift•
`tctioil
`aded Boundary-/kan
`
`Iron
`
`,----,-----'-
`
`--,, ,1 MUX
`
`--:.......11MUX
`
`Pa,al,
`l.a1cn
`
`Cloct
`
`11)1
`
`state for EXTEST
`. Fig. 1-14 Captur�-DR
`
`Remember that these test steps �till concern the EXTEST. ·Th� shift state for Action
`4,js the sam� as for Step· l of course. .
`in these figures are triggered by. the indicat�d Clo�k signals.
`··The actions' indicated
`The clock signal
`cells, 'In the Update-DR _
`triggers the actions in t,he Boundary-Scan
`track on the ·.
`�
`to 1\ ,copper
`is. then applied
`stage of the EXTEST an electrical signal
`
`.
`
`.
`
`!•
`
`•.
`
`IPR2021-01488
`Apple EX1003 Page 11
`
`

`

`\ .
`
`-r
`
`. \
`
`-Boui , .Scan Test A Practical-Approach
`10
`P.CB, which. arrives yjrrually at the srune' tiine -at. the receiving
`input of the' ..
`
`
`
`appropri;tte IC(s), ·see figure 1 �9 .. Here the Capture-DR action is also triggerecl by
`
`that ttie Update�DR ac·tion must be triggered . the clock pulse. It is prescribed
`
`at the
`slope). of the clock
`falling edge (negative
`pulse.
`whilst the Capture�DR
`action is .
`edge (positive
`·s�ope)
`of the clock pulse. Note in the l�vthr�e ·
`.at the rising
`trigger�d
`
`H4Hhat Uie EXTEST does not in any way interfere
`, figures (l':.12 through
`with the
`the core logic. , . · · .
`functioning-of
`· · .- .
`t�st can be performed with.
`
`
`. In. conclusion i( can be sta.ted·:that a board i'nterconnec;
`· th.e aid of Bounciar.Y.:Scan Registers usihg the described
`procedure. It .has also been ·
`
`shown that _.this can 'be done without interfering with, the core logic;'s •operation.
`
`
`
`Given the registers at iheI/O pins of the IGs, it.can be seen that an internal test of ·
`
`the IC logic (core logic) c�-,�o easily be realized� T�� testing of the inte1;11a1 Iogic .
`·or an IC is referred to. as interrial test or / NTEST. For the INTEST .the· same .rest
`
`
`�ctions as des.cribed for the E� �T � applicable.
`only· the Update-DR and
`
`
`
`Capture�DR actions concern. now the Boundary-Scan cells at the input and _output'
`·· .
`
`
`
`
`
`.... describes the actions.· test sequ.ence pinS of.the IC respectively .. _'IJle following
`
`
`
`
`Action I. .' Shift�DR: shift the :·data (test stim�i) through the registers to th�· cells
`
`d wi�h. the input· pins of the IC(s). . , · ·
`
`associate
`'·.·. .',: ..
`up�te �hese input �ells 'and apply the stimuli t� 'the core,
`Action 2 ... /1�daie-bR:·
`·•
`·logic.
`\
`
`
`Action 3. · · Capture-DR: _capture. the starus of the core logic outpu� .in the output
`
`cells of ttie IC(s). · ·
`·
`· · ·
`· . :····
`
`
`
`examination.
`The siinaI tio� dtirhlg t,he sh�ft aciio��-is the same iis i� figure i12. The signal:
`
`
`·flows for the ·t�st actions 4 and 3 ·;ire shown-in figure� 1-15 and 1-16 (s�aded).
`. . .
`
`.
`
`
`
`Action 4. . S1!1ft.-OR: .:shift out the re��lts through the BSR of th� IC(s).· for
`
`.
`
`. \
`
`Test Control Logic
`: ·, . ' '
`As dis�ussed abov�. several test ·control_ .signals are used· tp contt:ol the. Boundary�
`
`
`
`
`
`
`Scan. shift-registers, the parallel · latches and the t'!lultiplexers. It would be
`
`unacc�ptable to define an IC. package pin for each controi signal. Therefore, a.
`
`
`consisting of a ·sequencer that catr be controlled by
`controi logic has been ·design��
`
`Register a. serial. protocol: In i,.�dition to. this _s�quencer an !�struction
`
`(IR) is ·
`
`
`
`
`example INTEST andrequired to select the different tests to be p�rformed;Jor
`
`
`
`
`EXTE ST. The combinations of the sequencer states arid the IR instructions are used
`
`
`
`to generate the internal control signals' for the various test operations ..
`
`.
`
`.
`
`.
`
`.
`
`.
`
`. . .. . . .
`
`.
`
`•.
`
`-· . .
`
`1
`
`.
`
`. ) .
`
`. • , 1 ,
`
`l
`
`r, i
`
`.·'
`
`.·
`
`'
`
`..
`
`\
`
`.
`
`I
`
`.
`
`• .
`
`•· .
`
`,
`
`.,
`
`'
`
`IPR2021-01488
`Apple EX1003 Page 12
`
`

`

`PCB Testing .
`
`11
`
`,-,-�
`
`--
`
`,--
`
`-
`
`---,, 11 MUX.
`
`Fig_; 1-15 Update-DR state for INTEST.
`
`9
`
`Input
`
`,..... --,
`
`,---
`
`--
`
`--, ✓I MUX
`
`.----,..,.-----vi
`
`MUX
`
`TOI
`
`Fig. 1-16 Capture-DR s�te for INTEST
`
`{TMS) and Te�t
`by two signal li_nes: Test Mod� Select
`The s�quencer
`is controlied
`The whole Boundary-Scan test logic ·requires at least four.dedicated
`Clock·(TCK).
`thus additional to its other functional pins.-The
`four pins .
`test pins at the IC package�
`to as the T�t Access Porr or ,T A.f. The
`·(TMS� TCK, TD.I and TDO) are referred
`the TAP Controller,.
`·.
`entire test control logic is cqnsequently
`called
`have b�n standardized in the IEEE Std
`Remark. Since :ill these test provisions
`names for the signals and.the IC pins are used
`. . . '1149.1 [1], the,'standard.'
`·
`An overview of .the birth of the Boundary-Scan
`funher in this -book;
`standard is given in ch�pter 6.
`
`TMS :and TCK have
`refer back t� figure 1-7. the test con;ol- lines
`At b�ard level,
`for a·sT. Figure 1-17
`on the board that are suited
`to all components
`to be applied
`the infrastructure for the TMS _and TCK signals.
`includes
`
`.t: A
`Pnlc tical Approach.
`input of the
`receiving
`tion is also ·triggered
`by
`·must be triggered
`at the
`action· is
`e Capture-DR
`se. Note 'in the last three
`. . ' . .
`· .\y way, interfer
`e with the
`
`.!
`
`.
`
`. I ..
`
`· : c.ari be perfo.rined
`with
`It has· also been.
`. ,cedure.
`• core logic's operation;
`·
`l.hat an internal test of
`, :ing of the internal logic
`INTEST the same test
`Jy' the Update-DR and·
`at the input and output
`the actions.
`:scribes
`
`to the cells
`. ?e registers
`
`the stimuli �o the core·
`
`c outputs in tt:ie output
`
`3SR of ttie IC(s) for
`
`igure l �12. ·.Toe signal
`. i and 1-16 (shc!,9ed).
`
`control the Boun·dary­
`It would · be
`plexers.
`. >I signal .. Therefore, a
`. at can be controlled
`by_
`(IR) is
`. .dion Register
`. example �ST and
`s are used
`· R instruction
`·1perations.
`
`. .,
`
`IPR2021-01488
`Apple EX1003 Page 13
`
`

`

`j
`
`12
`
`
`
`, Boundary-S�an Test::·A �tical Approach
`
`,....,:..
`
`l,.
`
`TMS. TCIC
`
`TOI­
`,,,+-..,__--+.._�
`
`
`
`--'- car
`
`e
`L011�.
`
`J
`�
`�
`;(
`✓ I
`
`. ·�
`. TOO
`
`
`
`. Fig. 1-17 BST infrnstructui"e on P;CB
`
`Figure 1-17 shows that the. TMS and· TCK.signals· are applied to all relevant
`
`
`
`
`. components in parallel (thus all TAP. Controllers are always· in the �rune state),
`
`
`
`,, . whereas the test path, TDI to TDO. is.a serial path all over the printed circuit board .
`
`. ,,;
`
`-_--vl•�MUX
`-..,,..-_-_-_-_-_-_-_-_
`
`--
`
`-
`
`--r-
`
`\
`
`,SNftOR
`
`Ca,on{)R
`
`IIITUT
`
`·EXTUI'
`
`-
`
`TOI
`
`-
`
`TAP
`
`C:0..-
`
`3
`
`Slil!.OR
`C.OU.OR
`
`e-
`
`T'00
`
`�·
`
`--·
`
`_fig. 1-18 Test control logic for BST
`. The way that these .signal� ,control 'the Boundary-Scan Test logic is depicted in
`
`
`of the State Dec.oder, either the
`· figure 1�18. Here it can be seen that. under control
`
`/
`
`IPR2021-01488
`Apple EX1003 Page 14
`
`

`

`Practical Approach
`" · .. <\
`
`·PCB Testing
`
`II!
`
`i- ...
`
`13
`
`.
`'
`
`. . .
`
`.
`
`Instruction
`Reg_ist�r•s
`serial ·path or the Boundary-Scan
`shift register
`stages can be'.
`connected
`between
`the !C's TOI an_d TDO pins.:Figure·
`1-19 shows �t IC level the
`tC?5f control logic and the· serially connected
`Boundary-Scan
`·cells:
`In practice also
`as drawi:i, � figure 1-19. : . .
`�e present
`the IC input and �utput buffers
`
`.
`
`.
`
`.
`
`.
`
`I 0-.
`
`. ! . �-
`
`a.
`
`· ­
`
`-· o
`
`.j
`
`le; input
`buffer
`
`Boundary-Scan
`:
`Cell.
`IC Pin.
`
`. .
`
`. IC output.
`buffer ·
`
`to' all relevant
`..
`·',plied
`s in the sanie state).
`board.
`.. circuit
`pri,nted
`
`TDI
`
`· .. TDO
`
`0uuM
`
`Fig. I-I
`�cf Tes't·Control
`Register
`Boimdary-Scan
`? IC includ.ing
`
`TMS TCK
`
`l:XltST
`--
`
`....
`
`Figure 1-20 shows an example of :i board level B9undary-Scan
`test configuration
`· ·
`of one serial test path.
`consisting
`
`circuit board concc::rns .. the
`th� actual testing of the printed
`Remember. that
`as netl. net? ... netn (EXTES1); bu't the test
`the !Cs; denoted·
`between
`· · connections
`core
`of the chip's
`can also be used °ror checking the internal operation
`architecture
`· · ·
`·
`·
`·iogic (INTES1)_.
`
`Circuits
`Example Boundary-Scan
`
`should have . three
`registers
`the. Boundary-Scan
`. For a· board level test procedure
`·
`·
`importwit properties:
`I.. they must be 'invisible'
`dQring riorrnal operat�on ·of the IC's core logic.
`
`.
`
`.
`
`.
`
`·logic is depictc;d_
`in.
`either the
`·. ,e Decoder,
`
`IPR2021-01488
`Apple EX1003 Page 15
`
`

`

`14 ..
`
`.· ·.Boundazy-Scan Test: A PrActical App;oach
`
`TOI.
`
`Fig. 1-i0 PCB c;:onfiguration with all iC BSRs connected
`in series •
`
`.
`
`'
`
`. . .
`
`.
`
`.
`
`I
`
`.
`
`.
`
`2.they must .. be able to isolate the IC interconnections· on. the board frorfi the IC
`
`
`
`
`cores tQ allow testing the extemai IC co�nections. and _ .
`
`. i
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`
`3 .. they should be, able to isoiate the I<;:: from its s�oundings on the PCB to also
`·
`allow testing of the internal core logic. ·
`design is g1ven in figure 1-21.
`used,cell
`An example of a commonly,
`\ .
`
`The _ tes� properties are . obtained as follows. To support normal operation
`
`
`The control signal(Test/Nonnal) the inultipl.exer 2 (MUX2) is kept at. logical' ·o•.
`of MUXl can re kept.at
`T or .·o·.
`·(Shift/Load)
`· · ·
`
`The BS cell depicted in figure 1-21 can be 1,1Sed both. at the input anq at the output
`for'an INTE�T of the core logic (see figure 1-19) the
`related IC pins;· For. example.
`via TDI witff. MlJX 1 set to. 'l'
`data shifted-in
`BS cells at the IC input receive
`CT�st). At the core
`to tpe core logic with Ml]X2 set to • 1 •
`(Shift) and. clocked
`tor which MlJXl is set
`signal
`output
`output the BS cells must capture the resulting.
`
`
`to 'O'. (Data from system). These signals are clocked towards TOO for examination.
`·
`· ·
`for which MlJX2 is kept at • 1. · -
`
`�ote that the 'above depicted Boundary-Scrui cell is ju·st one sam.ple repres�ntation.
`
`
`Other circuits and test fearures are discussed
`n chapter
`2.
`
`.i
`
`·'
`
`IPR2021-01488
`Apple EX1003 Page 16
`
`

`

`
`
`
`
`A Practical Approach· .
`
`PCB -Testing·
`
`Mode
`Shift/Load . mo Serial Out
`
`
`
`�S .... vst_em--.- -+- -- - ----- - __,;;.- - - -1- -- -- ---' 0 . . Sy
`ste
`ata
`1 MUX2 Data
`
`�
`
`,J
`
`a 1----.110
`-----.110
`1 MUX1
`ci
`Cl
`
`· ,
`
`in series
`
`:he board from the IC
`
`gs on the PCB to also
`
`lll'e 1-21.
`
`3rt normal operatioir
`·o•. The control signa,I.
`
`_;.nput and at the output
`
`: c,(see figure 1-19) the
`vith MUXl .ser: .to .' 1' ·
`l' (Test). At the core.
`·or which MUXl is set'
`( mo for examination,
`
`Clock Update . .
`TDI Serial In· .
`
`
`
`Fig. 1-21 -Example ofa commonly used Boundary-Scan cell · .
`
`. ·.
`
`. \
`
`'
`
`. During tes�g; an IC's Boundary-Scan Register can also stay ·idle,. thus without .
`
`
`
`
`
`
`interfering with the in-core logic. For example, when the IC is not' ·used in a board . ·
`
`
`test it is senseless to include· the IC's BS Register (BSR) in th� PCB Boundary-Scan
`path. In such cases the BSR is short cut by the so called Bypass register,
`a one-bit
`
`
`faster, thus ·more register befween the .ml and mo pins to make the board te.st
`
`·
`·
`effic��
`
`' .,..
`
`1
`
`•
`
`The Bypass Register may be ·selected by loading the appropriate i11struction into the
`
`
`
`
`
`
`
`Instruction Register.· The presence !Jf instructions opens a wide variety of test
`
`
`.tance it is possible to have a Device Identification· Register
`
`possibilities. For ins
`
`
`
`·implemented in the component (IC); by means of which it can. be tesu;d whether the .
`
`
`
`the nght place on'the PCR Or, it is possible right component is mounted.on to !lave \
`
`
`
`
`
`
`manufacturer specific instructions for several purpose�; e.g. emulation, self-test, test
`
`·access to. internal scan ·registers. etc. Figure: 1-22 shows. an· eitrunple of .an
`·
`
`
`Instruction Register cell.
`• .
`, ·,. ;
`.
`. \ . •
`l
`. ,
`2. .
`are. detailed in chapter
`and applications
`The IR operation
`
`.
`
`The TAP Controller (see figure 1-18)· is a 16-state sequen�al·· rnac:hine operating
`
`
`
`
`
`with the TCK and responding· to the TMS signal. Under control of
`synchronously
`and. test data are shifted froin the. TD I, through
`
`• th� TAP Co11troller the instruction
`.
`. . .
`
`the registers and out again towards the .. TDO pin.
`. . . .
`
`· · A Bljundary�Scan test' consis� of four steps:
`
`
`
`
`
`
`sample representation. • ·
`
`\...
`
`/.
`
`./
`
`IPR2021-01488
`Apple EX1003 Page 17
`
`

`

`.....
`
`J·.
`
`. Boundary-Scai:i Test: A �ctical ,4.pproach:
`16
`·
`
`
`. 1.. shift in and decode instructions. i.l!. sdt!ct a particular data register,
`
`2.shi(t in -test cL-l.ta,
`
`3 .. execute the test and
`
`.1 .
`f
`
`Data
`
`. · From last cell
`
`t--r-------· To.next
`cell
`Instruction
`ait
`
`Clock-IA.,__......., _ __,... _ _.
`10 .·
`'Update-IA
`� ---- --.-- --- ----,. ....... -- -f">C1
`
`TRST�►-____ ...,.._ __ -f
`Reset• ---------1
`
`&
`
`
`_Fig. 1-i2
`
`
`
`Anexample of an Instruction Register cell
`
`, •
`
`I •
`
`All the actions d�··be
`
`.controlled' by the T A
`
`"
`�
`
`
`
`i Con\n;iller and are described in chapter
`
`.
`
`.
`
`C. .•
`
`(
`
`' ,',
`
`physical
`
`C��titueot Elem�ots of �e BST Paih: ·
`
`. . : •� .. .
`g· Boundru;:-Scan 'Test. (BS'D on a PCB implies' that
`
`
`As. menrion�d above, appiyir'
`
`
`Boundary-Scan (BS)" ceiis are .placed along· the I C's input/output pin� .. For test
`
`
`
`
`purposes, these BS ·cells replac.e· the conventional test pins ·(which can be
`
`
`
`
`placed on the IC contact pins during testing). by_ '.vir(ual' test pins·· inside the IC ..
`
`
`
`between the In the conve,_uional �ay_ an 'interconnecting copper tr�k (or--·�en
`
`
`output of IC 1 and the input -of' IC:2 is tested by placing t'.YO test pins on the net
`
`. nodes and applying test signa,ls to one nod� while measuring the responses at the
`
`
`
`. other node. These nodes (measuring points) could be.physically located at the PCB
`
`
`soldering joints"of_ �e IC pins.
`· ·
`· · ·
`In the -case ,of. BST. thitconvention� nodes become 'vfrrual' nodes located inside
`
`
`
`
`part.of the IC itself in the test path ineans that the test path
`
`the BS c�lls. Including
`
`
`
`
`
`. _becomes longer, so more· possible connection points are to be considered when a
`Figure 't-23 (introduced in [2]) gives an idea of the whole BST
`°fault-is detected.
`ICs. . . . . . . ,
`. .
`test paih between �o ..
`. The signal test path betw��n t\Vo;. '.,virtual'' test pins now includes:
`
`
`. . · \.
`
`IPR2021-01488
`Apple EX1003 Page 18
`
`

`

`t: A ·Practical Approach
`
`data register,
`
`PCB Testing
`
`,
`
`17
`
`__., __ ..., To next.
`·cell
`
`)
`
`
`
`Fig. l'-73 BST path between. two ICs
`
`Instruction
`Bit
`
`·are described_in chapter
`
`i.
`
`. the Output and Input Boundar.y-Scan cells, , ' _-
`
`.. the Output and· Input buffers.
`_ the Bonding pads, four in total:
`
`the Bondin_g wires. two in total.
`
`
`
`the IC pin 59ldering· joints, two in total; .
`
`the PCB copper track.
`Obviously a11 · these points, c� give rise to faults. Aithou'gh the ICs are tested
`
`
`
`
`usually before leaving the supplier's factory, the !Cs c_an, once mounted on the
`
`
`PCB, show faults. This .can be caused ,by component handling durjng loading the
`· '· ·
`
`··PCB, for example due to ·_mechanical or thermal shocks.
`
`
`
`
`
`
`It should be noted that a deduced 'open' fault (path interrupted) does· from a BS.test
`
`
`not. indicate on which of the above mentioned points the interruption occurs,. For
`
`on a PCB ;imp{ies that ·
`; . . 'i .·
`
`
`
`. example the connections of the two soldering points arid the PCB copper track in
`
`· · JI/output pins. For test
`
`
`between c� be faultless while the iriput buffer·ofIC2 .is bl<;>wn up du� to electro
`
`test pins (which c_an· be ·
`
`
`
`· . static discharge. which then may cause the ·open· error. If one output is connected
`
`<<!st pins inside the iC.
`
`
`
`
`·to ·several input pins, then further location of such: a .fault can .be deduced with
`
`
`·S) ..tor all i�put pins involved (for det.'lils see chapter
`proper test patterns
`
`
`(or 'net') between the
`
`· . wo test pins on the net
`,., '·�·•··: -�-"'�,/};�\
`
`:ng the respo"ses at the
`
`:ally locmed at,the f>CB
`
`J
`
`.
`
`'
`
`. . . .. · . . .
`
`11' nodes located.inside
`means that the test ·path
`
`, be considered wtit:n a
`
`
`i_dea of. the whole. BST:
`
`)
`
`eludes:
`
`i_.
`
`·'
`
`\.
`
`I .
`
`IPR2021-01488
`Apple EX1003 Page 19
`
`