[19J
`
`United States Patent
`Hong
`
`[11]
`
`4,241,307
`. Dec. 23, 1980
`[45]
`
`
`
`[54]MODULE INTERCONNECTION TESTING
`1974, pp. 152, 153.
`
`
`SCHEME
`
`tern, IBM Tech. Discl. Bulletin, vol. 17, No. 1, Jun.
`
`[21]Appl. No.: 934,936
`
`[22]Filed:Aug. 18, 1978
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`R. Strecker
`
`Se June Hong, Poughkeepsie, N.Y.
`[75]Inventor:
`Primary Examiner-Gerard
`E. Murray
`
`
`Attorney, Agent, or Firm-James,
`s Machines[73] Assignee: International Busines
`
`
`
`[57]
`ABSTRACT
`
`
`Corporation, Armonk, N.Y.
`
`
`
`This Specification describes the testing of interconnec­
`
`
`tions between modules mounted on a card and between
`
`
`
`the modules and the input and output terminals of the
`
`
`card. Each of the modules has a11 Exclusive-OR circuit
`
`
`[51]Int. Cl,3 ...................... GOlR 31/02; GOlR 31/28
`
`which receives an input from each of the input pins of
`
`[52]U.S. CI ..................................... 324/73 R; 324/51;
`
`
`the module and has a single output which is taken off an
`371/25
`
`
`
`output pin of the module. Also, each of the modules has
`
`
`324/51, 73 R, 73 PC, [58]Field of Search ..................
`
`
`
`
`a test input circuit for accessing all of the output pins of
`
`
`
`324/158 P, 158 F; 235/302.3; 371/15, 21, 24, 25
`
`
`
`the module in parallel from a single input terminal. The
`
`
`test input circuits are used to apply a binary O followed
`
`
`
`by a binary 1 to all the outputs of all the modules. The
`
`
`Exclusive-OR circuits are used to monitor the response
`
`
`McMahon ..................... 324/73 R X
`3,746,973
`7/1973
`
`
`
`to those signals. By testing in this manner, all the con­
`
`
`Freed ............................. 324/73 R X
`3,781,683
`12/1973
`
`
`
`nections between the modules and also between the
`
`
`James ............................. 324/73 R X
`1/1974
`3,789,205
`
`
`
`modules and the card terminals can be checked for
`
`McMahon .............................. 324/51
`4/1974
`3,803,483
`
`
`
`stuck ones and zeros. In the preferred embodiment a
`
`
`
`Jordan ............................... 324/73 R
`3,815,025
`6/1974
`
`
`
`
`more complex but still relatively simple bit pattern can
`
`
`
`Chesley ......................... 324/73 R X
`10/1977
`4,055,754
`
`
`test all the interconnection nets to determine if there are
`
`
`
`Balasubamanian et al. ....... 324/73 R
`2/1979
`4,140,967
`
`shorts between any of the nets.
`
`OTHER PUBLICATIONS
`
`
`
`
`Chao et al., Online Minimum Probing LSI Testing Sys-
`
`
`
`
`
`6 Claims, 4 Drawing Figures
`
`10
`
`11
`
`18
`
`12 /
`
`16
`
`20
`
`LOGIC
`S
`CIRCUIT
`
`26
`
`13
`
`EX OR TREE
`
`13
`
`IPR2021-01488
`Apple EX1006 Page 1
`
`

`

`Sheet 1 of 2 4,241,307
`u .. s. PatentDec. 23, 1980
`
`
`
`FIG. 1
`
`10
`
`11
`
`13
`
`18
`
`16
`
`24 14
`
`12
`
`20
`
`13
`
`LOGIC
`CIRCUITS
`
`26
`
`13
`
`13
`
`13
`
`FIG. 2
`
`IPR2021-01488
`Apple EX1006 Page 2
`
`

`

`U.S. Patent Dec. 23, 1980
`Sheet 2 of 2.
`
`4,.241,307
`
`10
`
`13
`FIG. 3
`
`12
`
`25
`
`11
`
`I
`I I
`
`,I
`I
`
`I
`
`13
`
`LOGIC
`CIRCUITS
`I
`I 30
`I
`I.
`I
`
`I 13
`
`I
`I
`
`I 13 I
`
`14
`26
`
`21
`
`I
`
`I
`_______ _J I
`I
`I 12a
`------;
`,,...--13 a
`
`22
`
`10
`
`FIG. 4
`
`11 11
`010 A
`B
`
`C
`
`010,
`iQ
`100
`+001.G
`
`11
`011 F
`010 N
`p
`
`mo
`OH
`100 J
`011 K
`20
`
`010
`
`H M100[ l00
`01
`
`011 t 0
`
`01 10
`
`IPR2021-01488
`Apple EX1006 Page 3
`
`

`

`4,241,307
`2
`1
`It is another object to simplify the testing of assem­
`
`
`
`
`
`
`
`blies. where subassemblies have been previously tested.
`MODULE INTERCONNECTION TESTING
`
`..
`SCHEME
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`These and other objects and advantages of the inven­
`BACKGROUND OF THE INVENTl():N
`5
`
`
`tion can be understood from the drawings of which:
`
`
`
`
`The present invention relates to the testing of connec­
`
`
`FIG. 1 is a schematic view of a portion of a card
`
`
`
`tions between modules mounted on cards and more
`
`
`
`embodying a form of the present invention that permits
`
`
`
`
`particularly to,circuitry in the modules to provide sim-
`
`testing of the module pin to card wiring connections
`
`ple testing of such connections. 10
`
`
`without probing the cards or modules;
`
`
`Before modules are mounted on a card, the modules
`
`
`FIG, 2 is a schematic view of a portion of a card
`
`
`
`are each thoroughly tested and the wiring of the card is
`
`
`showing a modification to be made in the embodiment
`
`
`
`tested. The faults introduced by the assemblying of the
`of FIG. 1 when two input pins of a module are con­
`
`
`modules on the card generally stem .from defective
`
`
`nected to a single input line;
`
`
`connections to the pins of the modules which do not 15
`
`
`FIG. 3 is a schematic view of a portion of a card
`
`
`
`
`destroy the internal circuits on the modules: Therefore
`
`
`
`showing a form of the invention which permits the
`
`
`
`
`what really needs to be tested, after. the assembly of the
`
`
`testing of interconnection nets om the cards along with
`
`
`
`
`circuits on the .cards is the connections between the
`
`
`the connections between the module pins and the card
`
`
`
`modules and the card. Howeverin the past the layout of
`
`wiring; and
`
`the modules has been such that this test -can not be 20
`
`
`FIG. 4 is a schematic view of a card containing the
`
`
`
`
`accomplished without taking into account th!! already
`
`
`embodiment of FIG. 3 with test signals superimposed
`
`
`
`
`
`tested cir�uitry on the module. Since this. circuitry is
`
`on the terminals and pins of the card.
`
`
`rich in interconnections, generating tests for defective
`
`an .enormous task. Speaking
`THE INVENTION
`
`pin connections becomes
`
`more specifically, when the card 1/0 pins are the only 25
`
`In the embodiment shown in FIG. 1, each of the
`
`
`
`accessible points for testing the test generation process
`
`
`
`modules 11 mounted on the card 10 contains a plurality
`
`
`must deal with the whole card full of logic circuits, that
`
`of both input pins 12 and output pins 14. These pins 12
`
`
`
`is, all the logic circuits on each of the modules mounted
`
`
`and 14 are connected by conductors 13 on the card 10 to
`
`
`on the card. The fact that the fault sites .are only at the
`
`
`output and input pins of other modules on the card and
`
`module boundary, that is, at the pins of the module,
`30
`
`
`to the input and output terminals. of the card.
`
`does not make the job any easier. Even. when the mod­
`
`
`The circuits 16 on each of the modules are connected
`
`
`
`ule pins are observable at the card testing one still has to
`
`to the input pins 12 by input lines 18 and the output pins
`
`
`
`find test inputs that will deliver sensitizing logic values
`
`
`
`
`14 by output lines 21. There are additional circuits pro­
`to the module inputs.
`
`
`vided on each of the modules by this invention. These
`35
`
`
`
`fa co-pending application Ser. No. 929,480 filed July
`
`
`
`include an Exclusive-OR tree 22 which receives an
`
`
`31, 1978, and entitled Chip Test Circuitry for Module .
`
`input from each of the input pins. 12 and has a single
`
`
`Final Test a testing method and apparatus is described
`
`output which is taken off the module on pin 14a. Fur­
`
`
`which could be used to test the connections between the
`
`
`
`
`thermore, each output line 21 is connected through a
`
`
`
`modules and the cards using circuits on the modules in 40
`
`
`
`half-select circuit 24 to the output pins 14 of the module.
`
`
`
`combination with mechanical probing of the cards.
`
`
`
`The half-select circuits have two inputs. One of the
`
`
`
`inputs is from one of the output lines 21. The other input
`·iNJ'RODUCTION
`
`is from line 26 connected to input pin 12a. The outputs
`
`
`
`
`
`
`
`circuits each go to one of the output In accordance with the present invention circuitry is of the select pins 14
`the testing
`that permits
`provided
`of interconnecti
`�ns 45 while the control
`terminals
`for each of the circuits
`is
`
`
`
`with a very simple electrical test that does not requ1re connected to input pin 12b.
`Each of the modules
`has an Exclu-The card must have 2 plus number of modules
`mechanical
`probing.
`addi-
`
`
`
`
`
`
`sive-OR circuit which receives an input from each of tional input and output terminals to perform tests in
`the input pins of the module and has a single
`output accordance
`invention
`and each module
`with the present
`is taken off an output
`pin of the module.
`Also, 50 must have three additional
`w.hich
`input and output pins as
`
`
`each of the modules has a test input circuit for accessing
`
`
`contemplated by the embodiment shown in FIG. 1.
`
`
`
`
`all of the output pins of the module in parallel. The test During normal operation, that is, operation when the
`
`
`
`
`
`
`
`are not being tested, input circuits are used to apply a binary O followed by a modules a binary 1 is applied to
`
`
`
`
`
`
`binary 1 to all the outputs of all the modules while the each of the terminals 12b. This connects the output lines
`for response
`outputs
`Exclusive-OR
`to 55 21 of the logic circuits
`are monitored
`to the output
`terminals
`14 so the
`
`
`
`those signals. Doing this checks the connections be-circuits 16 on the cards can perform in their intended
`
`
`
`
`
`
`
`When the circuits tween the modules and between the modules and the manner. are to be tested a binary O is
`
`
`card terminals for stuck ones and zeros. In the preferred
`
`
`
`applied to terminals 12b on all the modules. This un-
`
`
`
`
`
`
`
`embodiment, a more complex but still relatively simple gates the connection between the output lines 21 of the
`
`
`logic circuits nets to deter-60 original bit pattern can test all the interconnection
`
`
`and the terminals and instead
`
`
`
`
`mine if there are any shorts between the nets. connects all the terminals to line 26 so that test signals
`
`
`
`
`
`
`Therefore it is an object of the present invention to can be applied to the .output terminals by their applica-
`
`
`
`
`
`
`simplify testing of connections between modules tion to the card terminal connected to terminals 12a on
`
`
`
`
`
`
`mounted on cards after the modules have been so all the modules. The test signals are a binary O followed
`mounted.
`
`
`65 by a binary 1. The first signal tests for any pin stuck at
`
`
`
`
`
`
`It is another object of the invention to simplify the 1.If the card tests good, a binary O will appear at the
`
`
`
`to module terminals 14a, if not testing of connections between module p\ns and con-card terminal connected
`
`
`
`· · · a binary 1 appears at this terminal.
`
`ductors on the cards.
`
`IPR2021-01488
`Apple EX1006 Page 4
`
`

`

`4,241,307
`
`4
`
`
`
`(2)generate minimal number, k, of covering compati­
`
`
`
`3
`The second signal tests for any pin stuck at binary 0.
`
`
`
`
`If the card tests good a binary 1 will appear in response
`This works as follows:
`
`
`
`to the test, while a bad card will produce a binary 0 in
`(i)To test every pin stuck at 0 and 1, each net should
`
`
`
`
`response thereto. This would give an indication as to
`
`have at least one 0 value and at least one 1 value in
`
`where the bad connection occurred.
`the test.
`5
`
`In making the above test two presumptions were
`(ii)When two nets short together, the value of one
`
`
`made. One is that there are an odd number of inputs to
`
`
`
`dominates the other, therefore any net that may
`each card. The other is that one source does not go to
`
`
`short (adjacent somewhere in the card) must have
`
`
`
`two inputs on a single module. If the first presumption
`
`at least one opposing value pair in the test.
`is not true for any module 11 a dummy input can be 10
`(iii)If the Exclusive-OR output value is observed not
`
`
`
`
`
`provided to the Exclusive-OR circuit of that module
`
`
`
`
`
`through a shift register, but through a separate pin,
`
`from an additional input pin. If the second presumption
`
`
`
`the test inputs arriving at each module must have at
`
`
`is not true, the problem can be overcome by the modifi­
`least one odd parity case and at least one even
`
`cation shown in FIG. 2.
`parity case to test the stuck faults of the Exclusive­
`A simple embodiment of the invention has been de-15
`
`
`OR output pin itself.
`
`
`
`scribed above. What follows is a description of a more
`A simple approach to (i) and (ii) is to assign to each
`
`
`
`
`
`
`
`complex embodiment which permits testing for shorts
`
`
`
`net a unique non-zero binary ID of length 1 + log2N,
`
`
`
`
`between the different interconnection networks on the
`
`
`
`When each source produces its own ID, all single stuck
`
`
`card in addition to testing for simple stuck l's or O's in
`
`
`or short faults are sensitized through at least one Exclu­
`
`those networks. This eliminates the need for a card 20
`
`
`sive-OR gate.
`
`wiring test.
`The total number of tests required in this method is
`
`
`As shown in FIG. 3, each module includes an Exclu­
`
`
`
`already very small, however, if not all nets can short,
`
`
`sive-OR circuit 22 with an input coupled to each of the
`
`
`
`one can derive a shorter test by non-unique ID assign­
`
`
`module input pins 12 and output connected to a stage 22
`
`
`ment, i.e., the nets that never cross or parallel each
`
`
`
`in a shift register of the type described in U.S. Pat. No. 25
`
`other can have the same ID. This kind of analysis is
`
`
`
`3,993,919. In addition the output pins 14 are each con­
`
`
`
`
`probably not very important in a practical sense. The
`
`
`nected to a stage 26 of the same shift register. Data can
`
`
`general method of doing this can be summarized as:
`
`
`be loaded into the first stage of this shift register at input
`
`
`(1)Construct compatibility table of non-adjacent
`
`
`
`
`terminal 12a, stepped through all stages of the shift
`nets,
`
`register with clock signals and removed from the last 30
`
`
`
`
`
`
`
`stage of the shift register at output terminal 14a. Data
`bles,
`
`
`
`
`can also enter all shift register stages in parallel from the
`
`
`
`
`logic circuits 25 and from the output of the Exclusive­
`the compatibles.
`OR tree 21.
`The condition (iii) for testing the Exclusive-OR out­
`
`
`
`
`How data is entered into the shift register is deter-35
`
`
`
`
`put pin, if necessary, can be satisfied easily by a simple
`
`
`mined by the timing, set and reset signals described in
`
`
`trial and error process as follows:
`
`the last mentioned patent and represented.symbolically
`
`(1)Check all module inputs to see if there at least one
`
`
`by line 30 coupled in input terminal 12b. Thus the stages
`
`even parity input and one odd parity input in the
`26 could each be loaded with a "1" or a "0" through
`
`
`terminal 12a while the shift register is in serial mode, 40
`tests,
`
`(2)if some modules have test inputs entirely of the
`
`
`
`
`
`thereafter the shift register could be changed to parallel
`
`
`data mode and the response of Exclusive-OR tree cap­
`
`
`same parity, permute some ID's one at a time and
`
`tured in stage 22 and then the shift register could be
`check again.
`
`
`
`returned to serial data mode to read the response in
`The above juggling produces good assignments in a
`
`
`
`
`stage 22 out of terminal 14a. This process can be re-45
`
`
`
`few trials. An example of reduced tests for module pins
`
`peated any number of times so that a whole series of bits
`
`and card wiring is shown in FIG. 4 and the following
`
`
`can be loaded into each of the stages and each time the
`table.
`
`
`
`
`stages are loaded the response of the Exclusive-OR tree
`22 can be taken off the module.
`
`The shift registers of all the modules 11 on the card 50
`
`
`
`
`
`can be arranged in series and data shifted through all
`
`
`
`
`shift registers. If the shift registers are arranged in series
`
`
`
`only one input terminal and one output terminal of the
`
`card are needed for all the shift registers. If the shift
`
`
`
`registers are not so arranged a separate set of input and 55
`
`output terminals are needed for each shift register.
`
`To use the circuitry shown in FIG. 3 to check the
`
`
`
`interconnections on the card for shorts between the nets
`
`
`
`the number of separate interconnecting nets on the card
`60
`must be determined.
`The number of nets on the card is equal to the number
`
`
`of source pins for the nets which include all the module
`
`
`output pins and the card primary input pins. Let us say
`
`there are N nets on a card. Typically the number of nets
`n, for the compre-65
`is less than 1000. The number of tests,
`hensive method can be given as
`
`BCFGH
`AC
`AB
`EF
`DFL
`ADEGN
`AFQ
`Al
`HJQ
`IK
`J
`EM
`L
`FPQ
`NQ
`DFGINP
`
`
`
`(3)assign 1 + log2k bit long non-zero unique ID's to
`
`
`
`INCOMPATIBILITY TABLE
`
`NET
`
`
`
`ADJACENT TO
`
`A
`B
`C
`D
`E
`F
`G
`H
`I
`J
`K
`L
`M
`N
`p
`Q
`
`n�[l+log2N] for,N>2
`
`One minimal covering compatibles has 4 compatibles
`
`
`
`
`
`as follows:
`
`IPR2021-01488
`Apple EX1006 Page 5
`
`

`

`4,241,307
`
`5
`
`Oil
`
`6
`whereby the network of the electronic circuit
`
`
`
`
`
`package can be tested with simple binary signal
`{B,E,H,J,M,Q
`{A,D,N},
`{C,F,I,K,L,P},
`}
`{G,L},
`combinations.
`ID
`assigned
`
`
`
`2.The electronic circuit package of claim 1 including
`010
`()()!
`
`5 control terminal means on each of said subassembly
`
`
`
`
`
`packages for controlling the masking and testing circuit
`
`The card in FIG. 4 has three input terminals and
`means.
`
`of the pins on the modules there are a total of 13 output
`
`
`
`3.The electronic circuit package of claim 2 wherein
`
`
`
`
`card. Therefore there is a total of 16 nets on the card.
`
`
`
`
`the masking and testing circuits are a plurality of shift
`
`
`However as can be seen by the above analysis three test 10
`
`
`register stages in which each stage of the shift register is
`
`
`are all that is needed when non-adjacent nets are ex­
`
`
`
`coupled to one of the output terminals of the subassem­
`
`cluded. Two embodiments of an invention have been
`
`
`
`
`
`
`bly packages whereby a sequence of signals can be
`
`
`described. Both embodiments dealth with modules
`
`
`
`
`applied to the output terminals by shifting them one
`
`mounted on a card. However, it should be understood
`
`after another to the output stages.
`
`
`
`that the invention could be applied to chips mounted on 15
`
`
`4.The electronic circuit package of claim 3 wherein
`
`
`modules or to any subassembly-assembly combination.
`
`Therefore, it should be understood that this and other
`
`
`
`
`
`said circuit means on said. base includes means for the
`
`changes can be made in the two disclosed embodiments
`
`
`
`simultaneous application of different input signal combi­
`
`
`without departing from the spirit and scope of the in-
`
`
`
`
`nations to different output terminals of said subassembly
`vention.
`
`
`
`
`
`whereby shorts between different interconnection net­
`20
`
`
`Having thus described my invention, what I claim as
`works in the assembly can be detected.
`
`
`
`
`new, and desire to secure by Letters Patent is:
`
`
`
`S.The electronic circuit package of claim 2 wherein
`
`
`
`1.In an electronic circuit package in which a plural­
`
`
`
`said maskin& and test input circuit means is a plurality of
`
`
`ity of subassembly circuit packages with logic circuitry
`
`
`
`
`
`half-select circuits each with its output connected to
`
`
`
`thereon are mounted on a insulative base with an inter-25
`
`
`one of the output te1minals of the subassembly and one
`
`
`
`connecting network for interconnecting the input and
`
`
`input connected to an output line of the logic circuits
`
`output terminals of the subassembly circuit packages
`
`
`
`and the other input connected to the test input terminal
`
`with each other and with terminals of the electronic
`
`
`
`
`of the subassembly package and a control terminal con­
`
`
`
`circuit package the improvement comprising:
`
`
`
`nected to the control terminal means of the subassembly
`
`
`
`
`a separate Exclusive-OR circuit tree means included
`30
`package.
`
`
`
`in each of the subassembly circuit packages, which
`6.The electronic circuit package of claim S wherein
`
`
`
`
`
`is connected to the input terminals of that subas­
`
`said circuit means on said base couples all the test out­
`
`
`
`
`sembly circuit package in which it is included to
`
`
`
`put terminals of the subassembly packages together to
`
`
`
`test connections to output terminals of the subas-
`
`
`
`an output pin of the electronic circuit package and con­
`
`sembly packages;
`35
`
`nects all the test input terminals of the subassembly
`
`
`half select input circuit means on each of subassembly
`
`
`packages together to an input pin of the test package
`
`
`
`
`packages for coupling the output terminals of the
`
`
`and connects all the control terminals of the subassem­
`
`
`
`subassembly packages to a test input terminal of ihe
`
`
`bly packages together to a control pin of said electronic
`
`
`subassembly package for application of test signals
`
`
`
`circuit package whereby all the interconnection net­
`
`
`
`to the output terminals of the subassembly pack-40
`
`
`works can be tested for opens and shorts by application
`
`
`ages while the output of said logic circuits are
`
`
`
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`of a single binary O and a single binary 1 to the single
`
`ungated from said output terminals and;
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`
`
`
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`test input pin while monitoring the single output test
`
`
`circuit means on said base for activating said masking
`pin.
`
`
`and supplying said test signals to the test
`circuits
`
`
`input terminals of said subassembly packages
`45
`
`* * * * *
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`50
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`55
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`60
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`65
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`IPR2021-01488
`Apple EX1006 Page 6
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`