UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.
`Petitioner
`
`v.
`
`FUTURE LINK SYSTEMS, LLC
`Patent Owner
`_________________
`
`Inter Partes Review Case No. IPR2021-01488
`U.S. Patent No. 6,807,505
`
`DECLARATION OF DR. DAVID KUAN-YU LIU
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`IPR2021-01488
`Apple EX1004 Page 1
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.
`Petitioner
`
`v.
`
`FUTURE LINK SYSTEMS, LLC
`Patent Owner
`_________________
`
`Inter Partes Review Case No. IPR2021-01488
`U.S. Patent No. 6,807,505
`
`DECLARATION OF DR. DAVID KUAN-YU LIU
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`IPR2021-01488
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`I, David Kuan-Yu Liu, hereby declare the following:
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`I.
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`BACKGROUND AND QUALIFICATIONS
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`1. My name is David Kuan-Yu Liu, Ph.D and I am over 21 years of age
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`and otherwise competent to make this Declaration. I make this Declaration based on
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`facts and matters within my own knowledge and on information provided to me by
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`others.
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`2.
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`I have been retained by counsel for Petitioner as a technical expert in the
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`above-captioned case. Specifically, I have been asked to render certain opinions in
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`regard to the IPR petition with respect to U.S. Patent No. 6,807,505 (the “’505
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`Patent”). I understand that the Challenged Claims are claims 1, 6, and 8. My opinions
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`are limited to those Challenged Claims.
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`3. My compensation in this matter is not based on the substance of my
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`opinions or the outcome of this matter. I have no financial interest in Petitioner.
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`4.
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`In writing this declaration, I have considered my own knowledge and
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`experience, including my work experience in the field of electrical and computer
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`engineering and my experience working with others involved in this field, including
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`in the design and analysis of integrated circuit systems and subsystems. In reaching
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`my opinions in this matter, I have also reviewed the following references and
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`materials:
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`• The ’505 Patent (Ex. 1001)
`• Article on JTAG Boundary Scan IEEE Standard (Ex. 1002)
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`• Inventor Article on Boundary Scan Testing Standard (Ex. 1003)
`• Prosecution History for the ’505 Patent (Ex. 1005)
`• U.S. Patent No. 4,241,307 (“Hong”) (Ex. 1006)
`• Any additional background materials cited below
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`
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`A. Educational Background
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`5.
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`I received a Bachelor of Science degree in Electrical Engineering from
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`the University of California, Berkeley, in 1983. I received a Master of Science and
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`Ph.D. degrees in Electrical Engineering from Stanford University in 1985 and 1989,
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`respectively.
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`B.
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`6.
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`Professional Experience
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`From 1989 to 1992, I was a member of technical staff at Texas
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`Instruments, Inc. At Texas Instruments, my job responsibilities included process
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`integration, device modeling, high-voltage CMOS process integration, and
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`investigating novel source-side injection mechanisms for Flash EPROM channel
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`hot-electron programming.
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`7.
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`From 1992 to 1995, I was a member of the technical staff at Advanced
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`Micro Devices, Inc. (AMD) where I was a key contributor in optimizing Flash cell
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`and periphery devices in AMD’s CMOS-based 0.5um and 0.35um Flash EPROM
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`technology. My job responsibilities at AMD also included process integration,
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`device modeling, and development of triple-well process
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`technology for
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`accommodate x-decoder transistors and high voltage transistors for negative gate
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`erase operation. While at AMD, I was awarded a Spotlight Award for developing a
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`method of manufacturing a self-aligned source (SAS) etch for a NOR flash memory.
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`8.
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`I spent the next five years of my career in managerial and director roles
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`at several California-based semiconductor companies. I was responsible for
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`increasing yield and for leading teams of engineers working to develop next-
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`generation memory devices.
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`9.
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`In 2000, I co-founded Progressant Technologies in Fremont, California.
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`Progressant Technologies developed IP for negative differential resistance transistor
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`technology and was eventually acquired by Synopsys, Inc.
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`10. From 2000 to 2004, I was a Senior Manager at Xilinx, Incorporated,
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`where I was responsible for developing nonvolatile memory process technology for
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`flash and CPLD product applications, as well as advanced CMOS process
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`technology (specifically 75nm CMOS technology node, a half node version between
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`90nm and 65nm). The flash memory products I developed at Xilinx are used as the
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`configuration memory for the FPGA, with the configuration interface between them
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`being the JTAG interface.
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`11. From 2004 to 2007, I was a Senior Scientist at Maxim Integrated
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`Products where I was responsible for developing Embedded Non-volatile Memory
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`process technology for Power Management product applications.
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`12. Since 2007, I have served as a technical consultant where I have
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`provided expert advice regarding Flash memory technology, CMOS process
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`technology, and semiconductor device physics.
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`13.
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`I have 20 years of experience as an engineer and engineering
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`manager/director of Complementary Metal Oxide Semiconductor (CMOS)
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`technology development. During my career, I have worked at some of the leading
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`technology companies in the world, such as Texas Instruments, Advanced Micro
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`Devices, Altera Corporation (now a subsidiary of Intel Corp.), and Xilinx. At these
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`companies, my work focused on various aspects of CMOS and semiconductor
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`technology.
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`14.
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`I hold over 95 U.S. patents, a large number of which are directed to logic
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`CMOS processes technology and high voltage CMOS process technology. The vast
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`majority of my patents are in the area of CMOS process technology and memory
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`architecture. As such, I am intimately familiar with the implementation of integrated
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`process flows that essentially are repetitive sequences of modules, each composed
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`of a layer patterning step followed by selective deposition and etching of various
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`semiconductor materials, with the area of selectivity dictated by the layer patterning.
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`15.
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`I have also authored several technical papers that have been published
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`in well-respected, peer-reviewed journals, such as the IEEE Electron Device Letters,
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`the IEEE Journal of Solid-State Circuits, and the IEEE Transactions on Electron
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`Devices. As an example, I worked on a new conductivity-modulated Power
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`MOSFET that features a buried minority-carrier injector to enhance the current
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`conduction capability of the Power MOSFET. This work was published in the IEEE
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`Transactions on Electron Devices. In my experience, typical Power MOSFET
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`devices are fabricated on an epitaxial silicon layer grown on top of the silicon
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`substrate.
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`16. Taken as a whole, my academic and practical experience have given me
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`a substantial basis upon which to evaluate the technology that is in question in the
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`claims of the ’505 Patent. Based on my experience and education, and the acceptance
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`of my publications and professional recognition by peers in my field, I believe that
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`I am qualified to opine as to the knowledge and level of skill of one of ordinary skill
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`in the art at the time of the alleged invention of the ’505 patent (which I further
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`describe below) and what such a person would have understood at that time, and the
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`state of the art during that time.
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`17. My curriculum vitae, which includes a more detailed summary of my
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`background, experience, and publications, is attached as Appendix A.
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`II. LEGAL FRAMEWORK
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`A. Obviousness
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`18.
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`I am a technical expert and do not offer any legal opinions. However,
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`counsel has informed me as to certain legal principles regarding patentability and
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`related matters under United States patent law, which I have applied in performing
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`my analysis and arriving at my technical opinions in this matter.
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`19.
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`I have been informed that the Patent Trial and Appeal Board (“PTAB”)
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`now applies the claim construction standard applied by Article III courts (i.e., the
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`Phillips standard) regardless of whether a patent has expired. I have been informed
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`that under the Phillips standard, claim terms are to be given the meaning they would
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`have to a person having ordinary skill in the art at the time of the invention, taking
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`into consideration the patent, its file history, and, secondarily, any applicable
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`extrinsic evidence (e.g., dictionary definitions). In my analyses below, I have applied
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`the express construction discussed in the petition, and I have applied the plain and
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`ordinary meaning pursuant to the Phillips standard for all other claim language.
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`20.
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`I have also been informed that a person cannot obtain a patent on an
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`invention if the differences between the invention and the prior art are such that the
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`subject matter as a whole would have been obvious at the time the invention was
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`made to a person having ordinary skill in the art. I have been informed that a
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`conclusion of obviousness may be founded upon more than a single item of prior art.
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`I have been further informed that obviousness is determined by evaluating the
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`following factors: (1) the scope and content of the prior art, (2) the differences
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`between the prior art and the claim at issue, (3) the level of ordinary skill in the
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`pertinent art, and (4) secondary considerations of non-obviousness. In addition, the
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`obviousness inquiry should not be done in hindsight. Instead, the obviousness
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`inquiry should be done through the eyes of a person having ordinary skill in the
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`relevant art at the time the patent was filed.
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`21.
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`In considering whether certain prior art renders a particular patent claim
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`obvious, counsel has informed me that I can consider the scope and content of the
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`prior art, including the fact that one of skill in the art would regularly look to the
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`disclosures in patents, trade publications, journal articles, industry standards,
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`product literature and documentation, texts describing competitive technologies,
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`requests for comment published by standard setting organizations, and materials
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`from industry conferences, as examples. I have been informed that for a prior art
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`reference to be proper for use in an obviousness analysis, the reference must be
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`“analogous art” to the claimed invention. I have been informed that a reference is
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`analogous art to the claimed invention if: (1) the reference is from the same field of
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`endeavor as the claimed invention (even if it addresses a different problem); or (2)
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`the reference is reasonably pertinent to the problem faced by the inventor (even if it
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`is not in the same field of endeavor as the claimed invention). In order for a reference
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`to be “reasonably pertinent” to the problem, it must logically have commended itself
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`to an inventor’s attention in considering his problem. In determining whether a
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`reference is reasonably pertinent, one should consider the problem faced by the
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`inventor, as reflected either explicitly or implicitly, in the specification. I believe that
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`all of the references that my opinions in this IPR are based upon are well within the
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`range of references a person having ordinary skill in the art would consult to address
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`the type of problems described in the Challenged Claims.
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`22.
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`I have been informed that, in order to establish that a claimed invention
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`was obvious based on a combination of prior art elements, a clear articulation of the
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`reason(s) why a claimed invention would have been obvious must be provided.
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`Specifically, I am informed that, under the U.S. Supreme Court’s KSR decision, a
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`combination of multiple items of prior art renders a patent claim obvious when there
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`was an apparent reason for one of ordinary skill in the art, at the time of the invention,
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`to combine the prior art, which can include, but is not limited to, any of the following
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`rationales: (A) combining prior art methods according to known methods to yield
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`predictable results; (B) substituting one known element for another to obtain
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`predictable results; (C) using a known technique to improve a similar device in the
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`same way; (D) applying a known technique to a known device ready for
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`improvement to yield predictable results; (E) trying a finite number of identified,
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`predictable potential solutions, with a reasonable expectation of success; (F)
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`identifying that known work in one field of endeavor may prompt variations of it for
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`use in either the same field or a different one based on design incentives or other
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`market forces if the variations are predictable to one of ordinary skill in the art; or
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`(G) identifying an explicit teaching, suggestion, or motivation in the prior art that
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`would have led one of ordinary skill to modify the prior art reference or to combine
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`the prior art references to arrive at the claimed invention.
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`23.
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`I am informed that the existence of an explicit teaching, suggestion, or
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`motivation to combine known elements of the prior art is a sufficient, but not a
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`necessary, condition to a finding of obviousness. This so-called “teaching
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`suggestion-motivation” test is not the exclusive test and is not to be applied rigidly
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`in an obviousness analysis. In determining whether the subject matter of a patent
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`claim is obvious, neither the particular motivation nor the avowed purpose of the
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`patentee controls. Instead, the important consideration is the objective reach of the
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`claim. In other words, if the claim extends to what is obvious, then the claim is
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`invalid. I am further informed that the obviousness analysis often necessitates
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`consideration of the interrelated teachings of multiple patents, the effects of demands
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`known to the technological community or present in the marketplace, and the
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`background knowledge possessed by a person having ordinary skill in the art. All of
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`these issues may be considered to determine whether there was an apparent reason
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`to combine the known elements in the fashion claimed by the patent.
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`24.
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`I also am informed that in conducting an obviousness analysis, a precise
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`teaching directed to the specific subject matter of the challenged claim need not be
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`sought out because it is appropriate to take account of the inferences and creative
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`steps that a person of ordinary skill in the art would employ. The prior art considered
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`can be directed to any need or problem known in the field of endeavor at the time of
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`invention and can provide a reason for combining the elements of the prior art in the
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`manner claimed. In other words, the prior art need not be directed towards solving
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`the same specific problem as the problem addressed by the patent. Further, the
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`individual prior art references themselves need not all be directed towards solving
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`the same problem. I am informed that, under the KSR obviousness standard, common
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`sense is important and should be considered. Common sense teaches that familiar
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`items may have obvious uses beyond their primary purposes.
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`25.
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`I also am informed that the fact that a particular combination of prior art
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`elements was “obvious to try” may indicate that the combination was obvious even
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`if no one attempted the combination. If the combination was obvious to try
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`(regardless of whether it was actually tried) or leads to anticipated success, then it is
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`likely the result of ordinary skill and common sense rather than innovation. I am
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`further informed that in many fields it may be that there is little discussion of obvious
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`techniques or combinations, and it often may be the case that market demand, rather
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`than scientific literature or knowledge, will drive the design of an invention. I am
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`informed that an invention that is a combination of prior art must do more than yield
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`predictable results to be non-obvious.
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`26.
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`I am informed that for a patent claim to be obvious, the claim must be
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`obvious to a person of ordinary skill in the art at the time of the invention. I am
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`informed that the factors to consider in determining the level of ordinary skill in the
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`art include (1) the educational level and experience of people working in the field at
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`the time the invention was made, (2) the types of problems faced in the art and the
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`solutions found to those problems, and (3) the sophistication of the technology in the
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`field.
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`27.
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`I am informed that it is improper to combine references where the
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`references teach away from their combination. I am informed that a reference may
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`be said to teach away when a person of ordinary skill in the relevant art, upon reading
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`the reference, would be discouraged from following the path set out in the reference,
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`or would be led in a direction divergent from the path that was taken by the patent
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`applicant. In general, a reference will teach away if it suggests that the line of
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`development flowing from the reference’s disclosure is unlikely to be productive of
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`the result sought by the patentee. I am informed that a reference teaches away, for
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`example, if (1) the combination would produce a seemingly inoperative device, or
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`(2) the references leave the impression that the product would not have the property
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`sought by the patentee. I also am informed, however, that a reference does not teach
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`away if it merely expresses a general preference for an alternative invention but does
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`not criticize, discredit, or otherwise discourage investigation into the invention
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`claimed.
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`28.
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`I am informed that even if a prima facie case of obviousness is
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`established, the final determination of obviousness must also consider “secondary
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`considerations” if presented. In most instances, the patentee raises these secondary
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`considerations of non-obviousness. In that context, the patentee argues an invention
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`would not have been obvious in view of these considerations, which include: (a)
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`commercial success of a product due to the merits of the claimed invention; (b) a
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`long-felt, but unsatisfied need for the invention; (c) failure of others to find the
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`solution provided by the claimed invention; (d) deliberate copying of the invention
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`by others; (e) unexpected results achieved by the invention; (f) praise of the
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`invention by others skilled in the art; (g) lack of independent simultaneous invention
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`within a comparatively short space of time; (h) teaching away from the invention in
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`the prior art.
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`29.
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`I am further informed that secondary considerations evidence is only
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`relevant if the offering party establishes a connection, or nexus, between the
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`evidence and the claimed invention. The nexus cannot be based on prior art features.
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`The establishment of a nexus is a question of fact. While I understand that the Patent
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`Owner here has not offered any secondary considerations at this time, I will
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`supplement my opinions in the event that the Patent Owner raises secondary
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`considerations during the course of this proceeding.
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`III. OPINION
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`A. Level of a Person of Ordinary Skill in the Art
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`30.
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`I was asked to provide my opinion as to the level of skill of a person of
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`ordinary skill in the art (“POSITA”) of the ’505 Patent at the time of the claimed
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`invention, which counsel has told me to assume is February 22, 1998. In determining
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`the characteristics of a hypothetical person of ordinary skill in the art of the ’505
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`Patent, I considered several factors, including the type of problems encountered in
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`the art, the solutions to those problems, the rapidity with which innovations are made
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`in the field, the sophistication of the technology, and the education level of active
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`workers in the field. I also placed myself back in the time frame of the claimed
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`invention and considered the colleagues with whom I had worked at that time.
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`31.
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`In my opinion, a POSITA at the time of the claimed invention of the
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`’505 Patent would have had at least a bachelor’s degree in electrical engineering or
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`equivalent with at least one year of experience in the field of circuit design or circuit
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`testing. Additional education or experience might substitute for the above
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`requirements. Such a POSITA would have been capable of understanding the ’505
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`Patent and the prior art references discussed herein.
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`32. Based on my education, training, and professional experience in the field
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`of the claimed invention, I am familiar with the level and abilities of a person of
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`ordinary skill in the art at the time of the claimed invention. Additionally, I met at
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`least these minimum qualifications to be a person having ordinary skill in the art as
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`of the time of the claimed invention of the ’505 Patent.
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`B. Description of the Alleged Invention of the ’505 Patent
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`33. The ’505 Patent describes an alleged improvement to existing boundary
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`scan circuit testing. ’505 Patent (Ex. 1001), 2:17-24. Boundary scan circuit testing
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`was developed in the 1980s by a group of manufacturers called the “Joint Test
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`Action Group,” or JTAG, who in 1990 codified a testing technique in Institute of
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`Electrical and Electronics Engineers (“IEEE”) Standard 1149.1 that has since
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`evolved into a family of related standards published as recently as 2013. See JTAG
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`boundary-scan, firmly based on IEEE standards,” JTAG Technologies, (last visited
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`Sep. 3, 2021), https://www.jtag.com/jtag-boundary-scan-firmly-based-on-ieee-
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`standards/ (explaining the history and evolution of the original IEEE 1149.1
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`standard) (Ex. 1002). The ’505 Patent describes the standard by citing to an article
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`co-authored by inventor Franciscus G. M . De Jong (“De Jong Article”). ’505 Patent
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`(Ex. 1001), 1:24-28. Figure 1-19 of that article depicts the IEEE standard for
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`boundary scan circuitry on an integrated circuit (“IC”):
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`De Jong Article (Ex. 1003), 13 (annotated). As depicted in the figure, the typical
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`boundary scan circuity is designed to test interconnects that feed information to and
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`from a circuit using four dedicated testing pins collectively referred to as the Test
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`Access Port to the circuit and a test controller (also called a state machine) that
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`controls the serial shift of test data through boundary-scan cells connected to the
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`input and output (“I/O”) nodes of a circuit. ’505 Patent (Ex. 1001), 1:28-61. A
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`POSITA would have recognized the interconnects as buses because the ’505 Patent
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`describes grouping the interconnects into address and data buses that connect
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`multiple circuits for a two-part test. Id. at 1:7-15, 2:25-49 (describing testing
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`interconnects between electronic circuits), 6:18-7:25 (describing a first part of the
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`interconnect test for testing the circuit’s address bus), 7:26-54 (describing the second
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`part of the interconnect test for testing the circuit’s data bus).
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`34. According to the ’505 Patent, synchronous dynamic random access
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`memory (“SDRAM”) devices had “highly standardised pin lay-out[s]” incompatible
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`with the dedicated TDI, TDO, TMS, and TCK test pins required in a conventional
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`boundary scan architecture. Id. at 5:46-59 (describing the structured pin layout of an
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`SDRAM device obstructed by typical boundary scan test pins); see also id. at 4:19-
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`24 (describing pin count and compatibility constraints). A POSITA would have
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`recognized the ’505 Patent refers to circuit pins and I/O nodes interchangeably
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`because it depicts circuit pins around the periphery of the SDRAM device in Figure
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`1 and further discloses the “pin lay-out . . . schematically shows which I/O nodes
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`are generally present on the SDRAM device.” Id. at 5:56-6:1 (emphases added).
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`35. To avoid needing additional test pins, the ’505 Patent proposes an
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`“alternative” to the traditional boundary scan testing standard that replaces its state
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`machine and dedicated test pins for a “low complexity memory” that can be used to
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`accomplish much of the same interconnect testing. Id. at 2:25-44 (describing
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`interacting with such
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`low-complexity memory
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`to
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`test address and data
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`interconnects), 6:5-9 (describing the low-complexity memory as an alternative to an
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`“ordinary boundary-scan test unit”).
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`36.
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`In one example, interconnects are tested by sending a unique
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`combination of address bits over an address bus to a location in the low-complexity
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`memory, writing known test data bits previously stored at that address to a data bus,
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`such that both the address and data bus operations are tested when the test pattern
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`written to the data bus matches the expected response. Id. at 6:18-7:25 (describing
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`address bus testing), 7:26-54 (describing data bus testing), 8:31-55 (describing the
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`configuration of circuitry in the testing embodiment of Figure 2). According to the
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`’505 Patent, low-complexity memories avoid complicated access protocols, lengthy
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`initialization procedures, and dynamic restrictions of high complexity memories
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`such as SDRAM. Id. at 3:56-4:18. Such low complexity memories can be traditional
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`memory structures such as SRAM or ROM, but may also be even simpler structures
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`such as data registers. Id. at 4:57-63 (describing SRAM and ROM low complexity
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`memories), 12:51-52 (claiming a test unit that “comprises a read/write register”).
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`37. Annotated Figure 1 depicts one layout of address, data, and control
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`interconnects (nodes) connected to a test unit 120 that is operable as a low-
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`complexity memory, which internally interfaces with the core logic unit 110 (e.g.,
`
`an SDRAM circuit):
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`Id. at Fig. 1 (annotated to show circuit components and functions), 5:56-65. “In a
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`normal mode of the circuit 100, the test unit 120 is transparent, and signals can pass
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`freely between the I/O nodes 130 and the main unit 110. In a test mode of the circuit
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`100, the main unit 110 is logically disconnected from the I/O nodes 130 and the test
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`
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`unit 120 is in control.” Id. at 5:46-50.
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`38. Annotated Figure 2, below, illustrates how such a device may interact
`
`with an external testing device in the “test mode”:
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`Id. at Fig. 2 (annotated to show circuit components and functions). As an alternative
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`to memory structures, the test unit may instead comprise a simple combinatorial
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`logic circuit with “Exclusive-OR” (or “XOR”) gates like the ones depicted by Figure
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`6:
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`Id. at Fig. 6 (annotated), 11:62-12:2. Because each known set of input bits will
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`correspond to a known output from the logic gates, this combinatorial circuit
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`“implements the functionality of a ROM table,” allowing the system to input known
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`patterns of bits and confirm the outputs match the expected responses. Id. at 9:57-67
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`(describing the operation of the combinatorial implementation), 2:35-54 (“It is
`
`important that particular input data for the test unit, i.e., the address, result in output
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`data from the test unit that are [sic] known a priori, i.e.[,] the stored data.”). The
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`following table illustrates twelve patterns of five bits that can be used to confirm the
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`proper operation of five input and two outputs using combinatorial logic circuits:
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`Id. at 11:7-24. The Challenged Claims focus on this combinatorial embodiment in
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`which the test unit comprises XOR logic gates.
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`C. Opinions Related to Hong
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`i. Overview of Hong (Ex. 1006)
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`39.
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`In the subsequent paragraphs, I address the purpose, structure, and
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`operating modes of Hong’s invention particularly relevant to my opinions below.
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`Hong’s Purpose and Problem to Solve
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`40. Hong discloses a “module interconnection testing scheme.” Hong (Ex.
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`1006), Title. This scheme “relates to the testing of connections between modules
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`mounted on cards and more particularly to circuitry in the modules to provide simple
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`testing of such connections.” Id. at 1:7-10. Hong explains a typical problem in testing
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`card-mounted modules:
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`[F]aults introduced by the assemblying [sic] of the modules on the card
`generally stem from defective connections to the pins of the modules
`which do not destroy the internal circuits on the modules. Therefore
`what really needs to be tested after the assembly of the circuits on the
`cards [are] the connections between the modules and the cards . . . when
`the card I/O pins are the only accessible points for testing . . . [given
`t]he fact that the fault sites are only at the module boundary, that is, at
`the pins of the module[.]
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`Id. at 1:13-30. Hong’s modules mounted on a card are depicted in annotated Figures
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`3 and 4 below:
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`Id. at Figs. 3-4 (annotated to show card-mounted modules). In particular, Hong’s
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`invention “test[s] for shorts between different interconnection networks” and “for
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`simple stuck 1’s or 0’s in those networks” described at 3:15-21 (emphasis added).
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`Accordingly, a POSITA would have recognized Hong’s “interconnections” as
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`identical in circuit structure and function to the ’505 Patent’s “interconnects”
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`because, like Hong, the ’505 Patent discloses test circuitry that tests for short circuits
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`and “stuck-at 1” and “stuck-at 0” faults between address and data bus
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`“interconnects” as a common problem tested in synonymous circuitry components.
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`’505 Patent (Ex. 1001), 6:66-7:20 (describing address bus “stuck-at 1” and “stuck-
`
`at 0” testing), 7:26-41 (describing data bus shorts testing).
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`Hong’s Two Module Testing Embodiments
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`41. Hong describes two module-based embodiments for testing circuits.
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`Figure 1 depicts the module of Hong’s first embodiment:
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`Hong (Ex. 1001), Fig. 1, 2:25-46 (describing the first embodiment circuit
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`components). Figure 3 depicts the module of Hong’s second embodiment:
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`Id. at Fig. 3, 3:22-49 (describing the second embodiment circuit components).
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`Placing these embodiments side-by-side reveals they share nearly all circuit
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`components in a very similar configuration:
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`
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`Id. at Figs. 1, 3 (annotated to show similar structure), 2:25-46 (describing first
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`embodiment circuitry components), 3:22-34 (describing second embodiment
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`circuitry components). Hong’s second embodiment adds a shift register that works
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`in tandem with an Exclusive-OR circuit, which allows the test unit to identify “shorts
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`between the different interconnection networks on the card in addition to testing for
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`simple stuck 1's or 0's.” Id. at 3:15-21 (emphasis added). Annotated Figure 3
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`illustrates this “more complex embodiment” that builds upon the first, “simple
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`embodiment”:
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`Id. at Fig. 3 (annotated), 3:15-49 (describing the same). As depicted and disclosed
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`above, Hong applies consistent numerals and descriptions to the module input pins,
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`output pins, logic circuits, and Exclusive-OR circuits of both the first and second
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`embodiments. Accordingly, a POSITA would have recogni
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