IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`FUTURE LINK SYSTEMS, LLC,
`
`
`
`
`
`APPLE INC.,
`
`
`v.
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`Plaintiff,
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`
`
`
`
`
`
`
`Defendant.
`
`
`
`
`
`Civil Action No. 6:20-cv-00263-ADA
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`JURY TRIAL DEMANDED
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`DEFENDANT’S PRELIMINARY INVALIDITY CONTENTIONS
`
`I.
`
`INTRODUCTION
`
`Pursuant to the Parties’ Proposed Scheduling Order, Dkt. 25, Defendant Apple Inc.
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`(“Defendant” or “Apple”) provides these Preliminary Invalidity Contentions to Plaintiff Future
`
`Link Systems, LLC (“Plaintiff” or “Future Link”) for U.S. Patent Nos. 6,317,804 (the “’804
`
`patent”), 7,917,680 (the “’680 patent”), 6,622,108 (the “’108 patent”), and 6,807,505 (the “’505
`
`patent”), collectively, the “Patents-in-Suit” or “Asserted Patents.”
`
`These Preliminary Invalidity Contentions are made as to only the claims of the Patents-
`
`in-Suit that Plaintiff has identified in Plaintiff’s Preliminary Infringement Contentions served on
`
`July 8, 2021 (the “Infringement Contentions”):
`
`Patent
`’804 Patent
`’680 Patent
`’108 Patent
`’505 Patent
`
`Asserted Claims
`1-5, 8-10, 14, 17, 21-22 (the “’804 patent Asserted Claims”)
`1, 7, 8, 15, and 20 (the “’680 patent Asserted Claims”)
`1, 3, 6, and 11-13 (“’108 patent Asserted Claims”)
`1, 6, and 8 (“’505 patent Asserted Claims”; collectively with
`the asserted claims of the other Asserted Patents, the
`“Asserted Claims”)
`
`Defendant reserves the right to supplement these invalidity contentions to the extent
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`Plaintiff is allowed to change its Asserted Claims.
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`These preliminary invalidity contentions are being made in the early stages of fact
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`discovery. The parties have not yet started general discovery, and no general depositions have
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`been noticed or taken. No third party discovery has been taken. Accordingly, Defendant reserves
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`the right to supplement and amend these preliminary contentions to the extent additional
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`information becomes available during discovery. For example, Defendant may serve third party
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`discovery on companies that it believes are informed and have relevant prior art, and reserves the
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`right to supplement or amend these disclosures as may be appropriate in the future. Defendant
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`may also take third party discovery from the individuals named as inventors on the Asserted
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`Patents. Defendant reserves the right to supplement and/or amend its invalidity contentions to
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`include new prior art discovered from Plaintiff, from these third party sources, or other sources.
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`Defendant may also serve additional third-party discovery in the future including, but not limited
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`to, based on discovery received from Plaintiff and/or the above-referenced third parties, and
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`reserve the right to supplement and/or amend its contentions accordingly.
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`Defendant also reserves the right to rely on its own products or source code, some of
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`which may not become available for inspection until after these contentions have been served
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`due to current national health conditions surrounding the Coronavirus, the highly sensitive nature
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`of Defendant’s source code, and the restrictions placed on any transfer or review of that source
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`code.
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`Defendants hereby incorporate by reference the invalidity contentions served on Future
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`Link in Future Link Systems, LLC v. Advanced Micro Devices, No. 6:20-cv-01176 (W.D. Tex.),
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`Future Link Systems, LLC v. Broadcom Inc., No. 6:21-cv-00264 (W.D. Tex.), Future Link
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`Systems, LLC v. Qualcomm Inc., No. 6:21-cv-00265 (W.D. Tex.), and Future Link Systems, LLC
`
`v. Realtek Semiconductor Corp., No. 6:21-cv-00363 (W.D. Tex.), including all charts, cover
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`2
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`pleadings, exhibits, prior art, invalidity arguments including, but not limited to, arguments based
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`on 35 U.S.C. §§ 101, 102, 103, 112, and otherwise.
`
`II.
`
`RESERVATIONS
`
`A.
`
`General Reservation of Rights
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`The information provided shall not be deemed an admission regarding the scope of any
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`claims or the proper construction of those claims or any claim terms. Defendant does not waive
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`the right to contest any claim constructions or to take the positions during claim construction
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`proceedings that have yet to occur that may be inconsistent with the preliminary invalidity
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`contentions herein.
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`In certain instances, Defendant has applied the claims to the prior art in view of
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`Plaintiff’s allegations, admissions, or positions for purposes of these preliminary invalidity
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`contentions only. This disclosure of preliminary invalidity contentions is not intended to be, and
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`is not, an admission that any Asserted Claim is infringed by any of Defendant’s products, that
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`any particular feature or aspect of any of the accused products practices any limitations of the
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`Asserted Claims, or that any of the constructions implicit in Plaintiff’s Infringement Contentions
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`is reasonable, supportable, or proper. Rather, in some instances, Defendant’s application of the
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`claims to the prior art is intended to apply Plaintiff’s apparent interpretation of the claims.
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`B.
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`Plaintiff’s Infringement Contentions
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`Plaintiff’s infringement contentions are deficient in numerous respects. Defendant served
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`a deficiency letter on Plaintiff on August 4, 2021 and reserves the right to supplement or amend
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`these preliminary invalidity contentions in view of Plaintiff’s response, if any. Because
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`Plaintiff’s response to such deficiencies may lead to further grounds for invalidity, Defendant
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`specifically reserves the right to modify, amend, or supplement its contentions as Plaintiff
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`modifies, amends, or supplements its disclosures and/or produces documents in discovery.
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`3
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`Additionally, Plaintiff has presented no substantive contentions of any alleged
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`infringement under the doctrine of equivalents in its infringement contentions. It has provided
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`boilerplate reservations of rights, and made general references to the doctrine of equivalents, but
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`has provided no substantive allegation in its infringement contentions. As a result, Plaintiff has
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`waived any doctrine of equivalents theory. If Plaintiff is permitted to provide any information
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`relating to infringement under the doctrine of equivalents, Defendant may amend and
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`supplement these preliminary invalidity contentions as appropriate.
`
`C.
`
`The Intrinsic Record
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`Defendant further reserves the right to rely on applicable industry standards and prior art
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`cited in the file histories of the Asserted Patents and any related U.S. and foreign patent
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`applications as invalidating references or to show the state of the art. Defendant further reserves
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`the right to rely on the patent applicant’s admissions concerning the scope of the prior art
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`relevant to the Asserted Patents found in, inter alia: the patent prosecution history for the
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`Asserted Patents and any related patents and/or parent applications or reexaminations (or inter
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`partes review or post-grant review proceedings); any deposition testimony of the named inventor
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`of the Asserted Patents; any deposition testimony or other admissions by Plaintiff; and the papers
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`filed and any evidence submitted by Plaintiff in connection with this litigation.
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`D.
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`Rebuttal Evidence
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`Prior art not included in these preliminary invalidity contentions, whether known or not
`
`known to Defendant, may become relevant. In particular, Defendant is currently unaware of the
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`extent, if any, to which Plaintiff will contend that limitations of the Asserted Claims of the
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`Asserted Patents are not disclosed in the prior art identified herein or otherwise contend the
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`Asserted Patents are not invalid. To the extent that such an issue arises, Defendant reserves the
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`4
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`right to identify other references that would render obvious the allegedly missing limitation(s) or
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`the disclosed device or method, or otherwise rebut Plaintiff’s argument(s).
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`E.
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`Contextual Evidence
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`Defendant’s claim charts cite particular teachings and disclosures of the prior art as
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`applied to the limitations of each of the Asserted Claims. However, persons having ordinary
`
`skill in the art generally may view an item of prior art in the context of his or her experience and
`
`training, other publications, literature, products, and understandings. Moreover, common sense
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`may be employed as part of the obviousness analysis. As such, Defendant may rely on the cited
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`portions of the prior art references and on other publications, expert testimony, and common
`
`sense as aids in understanding and interpreting the cited portions, as providing context thereto,
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`and as additional evidence that the prior art discloses as claim limitation or the claimed subject
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`matter as a whole. Defendant further reserves the right to rely on uncited portions of the prior art
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`references, other publications, and testimony, including expert testimony, to establish bases for
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`combinations of certain cited references that render the asserted claims obvious. The references
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`discussed in the claim charts may disclose the elements of the asserted claims explicitly and/or
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`inherently, and/or they may be relied upon to show the state of the art in the relevant time frame.
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`The suggested obviousness combinations are provided in the alternative to anticipation
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`contentions and are not to be construed to suggest that any reference included in the
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`combinations is not by itself anticipatory.
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`5
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`III. OVERVIEW OF THE TECHNOLOGY AS OF THE ALLEGED PRIORITY
`DATES1
`
`A.
`
`The ’804 Patent
`
`From the earliest days of the telephone, engineers and entrepreneurs recognized a need
`
`for a more efficient and practical method of connecting telephones to each other.2 As the
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`number of potential telephone users increased, it would become infeasible to run wires from
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`every possible telephone to every other possible telephone.3 This problem was address through
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`the telephone exchange. The first telephone exchange was installed in New Haven, Connecticut
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`in 1878, allowing nearly two dozen telephone users to call each other by way of a manually
`
`operated central switchboard.4
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`Almost immediately, it was recognized that this process could, and should, be automated.
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`As early as 1879, publications detail ideas for automating this process via automated switching.5
`
`The first of these ideas to achieve commercial success was implemented in 1889 by Almon B.
`
`Strowger.6
`
`A more sophisticated solution, the “crossbar switch,” was invented in 1913 by J.N.
`
`Reynolds.7 Reynolds, then working at a subsidiary of AT&T named Western Electric, designed
`
`
`1 Plaintiff has provided no evidence that it is entitled to the November 18, 2004 priority date as to the ’680 patent
`and February 2, 1998 priority date as to the ’108 patent and the ’505 patent it claims in its Infringement Contentions.
`See Section III, infra. Defendant’s Preliminary Invalidity Contentions are based on Plaintiff’s representations that it
`is entitled to these earlier priority dates. However, Defendant reserves the right to amend, add to, or otherwise
`change its Preliminary Invalidity Contentions depending on findings of the correct priority dates.
`
`2 Borth, David E., “Telephone.” Encyclopedia Britannica, May 7, 2021.
`https://www.britannica.com/technology/telephone.
`
`3 Id.
`
`4 Id.
`
`5 Id.
`
`6 Id.
`
`7 Id.
`
`6
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`his crossbar switch for implementation in AT&T’s telephone systems.8 The crossbar switch
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`connected input lines to output lines by way of horizontal selecting bars mounted on vertical
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`hold bars in a grid-like formation.9 An embodiment of this invention was patented in 1932 as
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`U.S. Patent No. 2,040,334.10
`
`With the advent of the transistor in 1947 and the continued growth of telephone traffic,
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`engineers began to focus on a crossbar telephone switch that could rely on electronic
`
`components, rather than electromechanical switches.11 AT&T introduced the first commercial
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`version of this, dubbed the No. 1 Electronic Switching System, in 1965.12 That switch was
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`capable of serving as many as 65,000 two-way voice circuits and underwent numerous revisions,
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`including the adoption of semiconductor memory in 1977.13
`
`As of, November 3, 1998, the earliest possible priority date of the ’804 patent, electronic
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`interconnects like the crossbar switch were well known, commonly accepted, and routinely used
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`in a multitude of consumer and enterprise products. By this time, crossbar switch and
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`interconnect technology had been thoroughly implemented in computer technology.
`
`1.
`
`Electronic Interconnect Technology
`
`Interconnect circuits and switches connecting various computer micro-components have
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`been known and used at least since the early 1980s. In 1981, for example, U.S. Philips
`
`Corporation filed a patent application describing a two-wire bus-system that claimed priority to
`
`
`8 Id.
`
`9 Id.
`
`10 See U.S. Patent No. 2,040,334.
`
`11 Borth, David E., “Telephone.” Encyclopedia Britannica, May 7, 2021.
`https://www.britannica.com/technology/telephone.
`
`12 Id.
`
`13 Id.
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`7
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`an application filed the year before.14 The patent, titled “Two-wire bus-system comprising a
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`clock wire and a data wire for interconnecting a number of stations,” described a system for data
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`transmission allowing communication and interconnection between microprocessors, peripheral
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`devices, and other computer related systems, components, and subcomponents.15 This invention,
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`commonly known as the “I2C” (or “I2C”), taught a “single two-wire line to be used for the
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`interconnection of an unlimited number of stations.”16 The specification of that 1981 patent
`
`describes serial transmission of signals using separate data and clock lines.17 The invention
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`further discusses a method for coupling various computerized components to each other,
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`ensuring uninterrupted transmission by employing arbitration between transmitting
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`components.18
`
`Interconnect technology continued to mature during the 1980s, including with the
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`development and popularization of serial peripheral interfaces (“SPI”).19 For example, a patent
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`entitled “Queued serial peripheral interface for use in a data processing system,” filed by
`
`Motorola in 1987, describes that “[s]erial interfaces for data communications between
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`components of data processing systems are numerous.”20 The specification continues that “[o]ne
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`fairly typical such interface definition is referred to as the SPI (Serial Peripheral Interface) and is
`
`
`14 U.S. Patent No. 4,689,740.
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`15 See generally id.
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`16 Id. at 1:38–40.
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`17 Id. at 1:38–2:8; 5:4–9.
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`18 Id. at 2:35–3:4.
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`19 See U.S. Patent No. 4,816,996 at 1:10–23, Fig. 1.
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`20 Id. at 1:18–20.
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`8
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`incorporated in many microcomputers and peripherals designed by Motorola Inc.”21 This
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`“typical” interface was depicted in that patent’s Figure 1.22
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`Importantly, by this time, SPIs were already designed for implementation in data
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`
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`communications and processing systems and they already included paths for transferring data,
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`command, and clock information.
`
`2.
`
`The Crowded Space of the Crossbar Switch
`
`This interconnect technology, developed decades before the patent, continued to develop
`
`in the years preceding the ’804 patent. Such interconnect technology was demonstrably well
`
`known and various implementations of such technology would have been known or obvious to a
`
`person having ordinary skill in the art (“POSITA”) even at the earliest possible priority date for
`
`the ’804 patent.
`
`One of the most common technologies for crossbar switching and interconnect
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`technology prior to 1998 was in network switches and routers use of port-to-port interconnect
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`technology. For example, companies such as Cisco Systems, Digital Equipment Corporation and
`
`
`21 Id. at 1:20–24.
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`22 Id. at Fig. 1.
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`9
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`Lucent Technologies all created network products incorporating crossbar ASICs predating the
`
`’804 patent.
`
`
`
`
`
`
`
`
`
`
`
`
`
`The Cisco 12000 Gigabit Switch Router (GSR)
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`The Catalyst 5500 series including at least the Catalyst 5505, 5509 or 5500
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`The Cisco 7500 and 7200
`
`The Cisco Catalyst series of switches, including at least the Catalyst 2926 Switch
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`Lucent Technologies’ Cajun P550 Gigabit Switch and Cajun P550 Routing
`Switch
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`DEC’s GIGAswitch System
`
`3.
`
`The Development of ARM AMBA Interconnects
`
`In its Infringement Contentions, Future Link points to ARM AMBA (“Advanced
`
`Microcontroller Bus Architecture”) technology as evidence that Apple infringes the ’804
`
`patent.23 In fact, ARM AMBA technology was introduced years prior to the earliest priority date
`
`claimed for the ’804 patent.
`
`ARM introduced the AMBA family of interconnect technology as early as 1995.24 As
`
`disclosed in ARM AMBA’s introductory publication, the ARM AMBA specification “describes
`
`an on-chip communications standard for designing high-performance 16 and 32-bit
`
`microcontrollers, signal processors and complex peripheral devices.”25 The first version of
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`AMBA includes two buses: the Advanced System Bus (“ASB”) and Advanced Peripheral Bus
`
`(“APB”).26 The version further supported multiple bus masters through the use of an arbitration
`
`
`23 Infringement Contentions Ex. A at 1.
`
`24 ARM Limited, Introduction To AMBA (Document No. DVI 0010A, 1996) at § 1.3, available at
`https://documentation-service.arm.com/static/5f106ce80daa596235e81425.
`
`25 Id. at § 1.1.
`
`26 Id. at § 1.2.
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`10
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`scheme including bus request, bus grant, and bus lock signals.27 Among other things, ARM
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`AMBA was aimed to “minimize the silicon overhead required for . . . an on-chip bus.”28 These
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`buses served as on-chip interconnects designed to be implemented in a multitude of applications.
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`As reported in the 1996 introductory specification, the first AMBA specification had “been
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`stable from September 1995,” was “a proven bus architecture,” and had “been used in the
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`ARM7100 and many other high-integration microcontrollers.”29
`
`The second version of the ARM AMBA specification built upon the infrastructure
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`already present since 1995. AMBA 2 added only the AMBA High-performance Bus (AHB) to
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`the previously well-known ASB and APB buses in the AMBA 1 specification.30
`
`*
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`
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`*
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`
`
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`*
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`In light of the pervasive use of interconnect technology generally and specifically with
`
`respect to computerized components, implementations of this technology would have been
`
`known to a POSITA as of the time of the ’804 patent.
`
`B.
`
`The ’680 Patent
`
`The history of data packet transmission likewise extends decades before November 18,
`
`2004, the earliest possible priority date for the ’680 patent. In 1964, for example, Paul Baran
`
`authored a publication for the United States Air Force Project RAND entitled “On Distributed
`
`Communications: I. Introduction to Distributed Communications Networks,” describing the use
`
`of a distributed network to transmit packets of information across long distances.31 In particular,
`
`
`27 Id. at § 1.2.1.
`
`28 Id.
`
`29 Id. at § 1.3.
`
`30 See ARM, ARM AMBA Specification (Rev 2.0) (Document No. ARM IHI 0011A, 1999), available at
`https://documentation-service.arm.com/static/5f916403f86e16515cdc3d71.
`
`31 Paul Baran, On Distributed Communications: I. Introduction to Distributed Communications Networks (RAND
`
`11
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`the paper notes that an “all-digital-data distributed network . . . us[ing] . . . a standard format
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`message block permits building relatively simple switching mechanisms using an adaptive store-
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`and-forward routing policy to handle all forms of digital data including “real-time” voice.”32
`
`Even then, the concept of handling different varieties of packets based on their respective
`
`performance needs was recognized. Baran described that his network addressed these needs by
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`“rapidly respond[ing] to changes in the network status,” using “[r]ecent history of measured
`
`network traffic . . . to modify path selection.”33 As he discusses in his paper, simulation
`
`demonstrated that his network achieves highly efficient routing “without the necessity for any
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`central—and therefore vulnerable—control point.”34 This design was later implemented in the
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`1970s-era ARPANET.35
`
`Since that time, packet ordering and transmission technology has continued to develop
`
`and has been implemented in a wide variety of applications that predate the ’680 patent. The
`
`technology was demonstrably well known and various implementations of such technology
`
`would have been known or obvious to a person having ordinary skill in the art (“POSITA”) even
`
`at the earliest possible priority date for the ’680 patent.
`
`
`Corporation 1964), available at
`https://www.rand.org/content/dam/rand/pubs/research_memoranda/2006/RM3420.pdf.
`
`32 Id. at v.
`
`33 Id.
`
`34 Id.
`
`35 Kevin Featherly, “ARPANET.” Encyclopedia Britannica, Mar. 23, 2021.
`https://www.britannica.com/technology/telephone.
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`12
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`1.
`
`The Development of PCI Express
`
`The ’680 patent is entitled “Performance based packet ordering in a PCI Express bus.”36
`
`The focal technology however, the PCI Express bus, had been in existence many years before the
`
`’680 patent. PCI, or Peripheral Component Interconnect, is a local computer bus for attaching
`
`hardware devices in a computer.37 This technology was publicly available at least as early as the
`
`first version of the PCI Local Bus specification released in 1992.38 Notably, PCI Local Buses
`
`have long included functionality for organizing packets based on the information that is being
`
`transmitted, performing arbitration between multiple packet sources, and optimizing these
`
`processes to improve bus performance.39
`
`PCI Express (“PCIe”) is an extension of the earlier PCI and PCI-X bus interconnects used
`
`to connect peripheral devices in computing applications. Like PCI and PCI-X, PCIe is a
`
`standard issued by the PCI-SIG, based on the same fundamental framework and technology.40
`
`Specifically, PCIe and carries forward the most beneficial features from the previous generations
`
`of bus architectures. PCIe implements a serial, point-to-point type interconnection for
`
`communication between two devices. Multiple PCIe devices are interconnected via the use of
`
`switches that perform arbitration and ordering. Communication over the serial interconnect is
`
`accomplished using a packet-based communication protocol. Quality of Service (QoS) features
`
`
`36 See ’680 patent, Title.
`
`37 See PCI Special Interest Group, PCI Local Bus Specification 1.0 (Jun. 22, 1992).
`
`38 Id.
`
`39 See PCI Special Interest Group, PCI Local Bus Specification 2.2 (Dec. 18, 1998) at 11, 40–43, 61.
`
`40 See Margaret J. Chong, A PCI Express to PCIX Bridge Optimized for Performance and Area (Mass. Instit. of
`Tech. Dep’t of Elec. Eng’g and Computer Science, Mar. 17, 2004), available at
`https://dspace.mit.edu/handle/1721.1/16674
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`13
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`provide differentiated transmission performance for different applications, including those based
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`on the performance needs of those applications.41
`
`2.
`
`The Crowded Space of QoS Data Packet Transmission and Ordering
`
`PCIe’s reliance on QoS technology is part of a long history of technologies relying on
`
`QoS ordering schemes. For example, QoS technology has long been part of interconnection
`
`networks, including the Asynchronous Transfer Mode (ATM) network technology of the
`
`1990s.42 VoIP (Voice over IP) is another application that is dependent on QoS. QoS enabled
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`“VoIP to be a realistic replacement for standard public switched telephone network (PSTN)” by
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`“ensur[ing] that VoIP voice packets receive the preferential treatment they require.”43
`
`*
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`
`
`
`
`*
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`
`
`
`
`*
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`In light of the pervasive use of data packet ordering and transmission technology,
`
`including the use of QoS, implementations of this technology would have been known to a
`
`POSITA as of the time of the filing of the application that issued as the ’680 patent.
`
`C.
`
`The ’108 and ’505 Patents
`
`The ’108 and ’505 patents are directed to an alleged improvement to existing boundary
`
`scan circuit testing. The concept of boundary scan—and interconnect testing, more generally—
`
`has long been known and practiced in the semiconductor industry.
`
`
`41 See, e.g., Budruck et al., PCI Express System Architecture, MindShare, Inc. (2004) at Chapter 1.
`
`42 See, e.g., Ender Ayanoglu & Nail Akar, B-ISDN (Broadband Integrated Services Digital Network), Center for
`Pervasive Commc’n and Computing, UC Irvine (2002).
`
`43 See, Quality of Service for Voice over IP, Cisco Systems, Inc. (2001), available at
`https://www.cisco.com/c/en/us/td/docs/ios/solutions_docs/qos_solutions/QoSVoIP/QoSVoIP.pdf
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`14
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`1.
`
`History of Boundary Scan
`
`Boundary scan circuit testing was developed in the 1980s by a group of manufacturers
`
`called the “Joint Test Action Group,” or JTAG, comprising companies such as BT, GEC, and
`
`TI.44 In 1990, JTAG codified a testing technique in Institute of Electrical and Electronics
`
`Engineers (“IEEE”) Standard 1149.1, entitled “Standard Test Access Port and Boundary-Scan
`
`Architecture,” that has since evolved into a family of related standards published as recently as
`
`2013.45 The 1149.1 standard is generally known in the semiconductor industry by names such as
`
`JTAG, JTAG boundary scan, or Dot1, and JTAG devices are referred to as IEEE 1149.1
`
`compliant devices.46
`
`The 1149.1 standard originally began as an integrated method for testing interconnects on
`
`a printed circuit board (PCB) implemented at the integrated circuit (IC) level.47 It presented an
`
`elegant solution to the then-problem of growing complexity and density of circuit boards, which
`
`dramatically increased testing-related costs, by building functionality directly into the IC to assist
`
`in testing assembled electronic systems.48 Over time, boundary scan has been used for
`
`everything from testing interconnects and functionality on ICs to programming flash memory.49
`
`It is still used today.
`
`
`44 JTAG Technologies, JTAG boundary-scan, firmly based on IEEE standards, available at
`https://www.jtag.com/jtag-boundary-scan-firmly-based-on-ieee-standards/ (discussing the history and evolution of
`the original IEEE 1149.1 standard).
`
`45 Id.
`
`46 Id.
`
`47 Corelis, What is JTAG?, available at https://www.corelis.com/education/tutorials/jtag-tutorial/what-is-jtag/
`(discussing the history and evolution of the original IEEE 1149.1 standard).
`
`48 Id.
`
`49 Id.
`
`15
`
`IPR2021-01487
`Exhibit 2002
`Page 15 of 88
`
`

`

`2.
`
`The Crowded Space of Boundary Scan
`
`Since its codification, the 1149.1 standard has been adopted by electronic device
`
`companies all over the world. For example, in 1990, original JTAG member Texas Instruments
`
`(TI) developed its own line of products known as the SCOPE testability integrated-circuit
`
`family.50 This family “supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate
`
`the testing of complex circuit-board assemblies,” and includes components such as test-bus
`
`controllers SN54ACT8990, SN74ACT8990, and digital bus monitor SN74ACT8994.51
`
`Similarly, Corelis—a company founded in 1991 that offers JTAG / boundary-scan test
`
`solutions and 1149.x-compliant products—introduced its first boundary-scan products as early as
`
`1998, such as the PCI-1149.1 High Speed PCI Bus Boundary-Scan Controller, ScanPlus
`
`Debugger, and LAN-Based JTAG and ROM Emulator (NetICE-403).52
`
`IV.
`
`INVALIDITY UNDER 35 U.S.C. § 101
`
`A.
`
`Legal Background
`
`To be patentable subject matter under § 101, a claim must be directed to one of four
`
`eligible subject matter categories: “new and useful process, machine, manufacture, or
`
`composition of matter.” 35 U.S.C. § 101. “Claims that fall within one of the four subject matter
`
`
`50 See, e.g., https://www.ti.com/lit/ds/symlink/sn54act8990.pdf at 1 (datasheet for test-bus controllers
`SN54ACT8990, SN74ACT8990); https://pdf1.alldatasheet.com/datasheet-pdf/view/28255/TI/SN74ACT8994.html
`at 1 (datasheet for digital bus monitor SN74ACT8994).
`
`51 Id.
`
`52 See, e.g., Corelis, Corelis introduces ScanPlus Debugger™ for interactive control and observation of boundary-
`scan (JTAG) devices pins, available at https://www.corelis.com/corelis-introduces-scanplus-debugger-for-
`interactive-control-and-observation-of-boundary-scan-jtag-devices-pins/ (1998 press release for the ScanPlus
`Debugger); Corelis, Corelis Introduces a LAN-based JTAG and ROM Emulator for the IBM PowerPC™ 403
`Family of Processors, available at https://www.corelis.com/corelis-introduces-lan-based-jtag-rom-emulator-ibm-
`powerpc-403-family-processors/ (1998 press release for the NetICE-403); https://www.corelis.com
`/downloads/hardware/Edition%202.09/User's%20Manuals/Miscellaneous/PCI-1149.1/PCI-1149.1-User-Manual.pdf
`(user’s manual for the PCI-1149.1 High Speed PCE Bus Boundary-Scan Controller); Corelis, About Corelis,
`available at https://www.corelis.com/about/.
`
`16
`
`IPR2021-01487
`Exhibit 2002
`Page 16 of 88
`
`

`

`categories may nevertheless be ineligible if they encompass laws of nature, physical phenomena,
`
`or abstract ideas.” Digitech Image Techs., LLC v. Elecs. for Imaging, Inc., 758 F.3d 1344, 1350
`
`(Fed. Cir. 2014) (citing Diamond v. Chakrabarty, 447 U.S. 303, 309 (1980)). The Supreme
`
`Court established a two-step test for deciding the subject matter eligibility of claims under § 101.
`
`Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 134 S. Ct. 2347, 2355 (2014). First, the claims must be
`
`analyzed to determine whether they are drawn to one of the statutory exceptions. Id. Claims that
`
`invoke generic computer components instead of reciting specific improvements in computer
`
`capabilities are abstract under this first step. See Enfish, LLC v. Microsoft Corp., 822 F.3d 1327,
`
`1335-36 (Fed. Cir. 2016). Second, the elements of the claims must be viewed both individually
`
`and as an ordered combination to see if there is an “inventive concept.” Id. The mere fact that a
`
`claim recites or implies that an abstract idea is implemented using a general-purpose computer
`
`does not supply an inventive concept necessary to satisfy § 101. See Elec. Power Grp., LLC v.
`
`Alstom S.A., 830 F.3d 1350, 1355 (Fed. Cir. 2016); Alice, 134 S. Ct. at 2357-59.
`
`All of the Asserted Claims are directed to ineligible subject matter under 35 U.S.C. § 101
`
`and applicable case law authority.53
`
`
`53 See, e.g., Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 134 S. Ct. 2347 (2014); Mayo Collaborative Servs. v.
`Prometheus Labs., Inc., 132 S. Ct. 1289 (2012); Trading Techs. Int’l, Inc. v. IBG, LLC, 921 F.3d 1084 (Fed. Cir.
`2019); ChargePoint, Inc. v. SemaConnect, Inc., 920 F.3d 759 (Fed. Cir. 2019); SAP America, Inc. v. InvestPic, LLC,
`898 F.3d 1161 (Fed. Cir. 2018); Interval Licensing LLC v. AOL, Inc., 896 F.3d 1335 (Fed. Cir. 2018); Aatrix
`Software, Inc. v. Green Shades Software, Inc., 882 F.3d 1121 (Fed. Cir. 2018); Two-Way Media Ltd. v. Comcast
`Cable Commc’ns, LLC, 874 F.3d 1329 (Fed. Cir. 2017), cert. denied, 139 S. Ct. 378 (2018); Intellectual Ventures I
`LLC v. Capital One Fin. Corp., 850 F.3d 1332 (Fed. Cir. 2017); Apple, Inc. v. Ameranth, Inc., 842 F.3d 1229 (Fed.
`Cir. 2016); Affinity Labs of Texas, LLC v. DIRECTV, LLC, 838 F.3d 1253 (Fed. Cir. 2016); Elec. Power Grp., LLC
`v. Alstom S.A., 830 F.3d 1350 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327 (Fed. Cir. 2016);
`Genetic Techs. Ltd. v. Merial L.L.C., 818 F.3d 1369 (Fed. Cir. 2016); Intellectual Ventures I LLC v. Capital One
`Bank (USA), 792 F.3d 1363 (Fed.