Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 1 of 42
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`UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`HD SILICON SOLUTIONS LLC,
`
`Plaintiff,
`
`v.
`
`MICROCHIP TECHNOLOGY INC.,
`
`Defendant.
`
`Civil Action No. 6:20-cv-1092-ADA
`
`PATENT CASE
`
`JURY TRIAL DEMANDED
`
`DEFENDANT MICROCHIP TECHNOLOGY INC.’S OPENING CLAIM
`CONSTRUCTION BRIEF
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`MICROCHIP TECHNOLOGY INC. EXHIBIT NO. 1057
`Page 1 of 42
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 2 of 42
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`TABLE OF CONTENTS
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`
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`Page
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`I.
`II.
`
`III.
`
`IV.
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`LEGAL STANDARD ........................................................................................................ 1
`CLAIM TERMS FOR U.S. PATENT NO. 6,774,033 (“’033 PATENT”) ....................... 2
`A.
`“interconnect” (claim 1) ......................................................................................... 2
`B.
`“depositing a second film over the first film” (claim 1) ........................................ 2
`C.
`“metal stack” (claims 1, 8, 15) / “the first film and the second film forming
`a metal stack” (claim 1) ......................................................................................... 5
`“in-situ” (claim 2) .................................................................................................. 7
`D.
`CLAIM TERMS FOR U.S. PATENT NO. 7,154,299 (“’299 PATENT”) ....................... 8
`A.
`“via no circuit element other than one or more switch elements” (claim 1)
`/ “via no circuit element other than one or more pass gates” (claims 5, 7-9,
`13, 14, 16) .............................................................................................................. 8
`“no circuit element” (claims 1, 5, 7-9, 13, 14, 16, 19, 23) ..................................... 9
`B.
`“the logic circuit element” (claim 1) .................................................................... 10
`C.
`CLAIM TERMS FOR U.S. PATENT NO. 7,260,731 (“’731 PATENT”) ..................... 12
`A.
`“during a voltage transition” (claims 1, 6, 8) ....................................................... 12
`B.
`“power is saved” (claims 1, 6, 8) ......................................................................... 14
`C.
`“reduce its output voltage below a specified output voltage” (claim 4) .............. 16
`D.
`“means for providing signals at the input terminal of the voltage regulator”
`(claim 8) ............................................................................................................... 17
`“means for changing the voltage regulator [mode]” (claim 8) ............................ 20
`E.
`CLAIM TERMS FOR U.S. PATENT NO. 7,302,619 (“’619 PATENT”) ..................... 22
`A.
`“fetching” / “fetched” (claims 1, 2, 10, 13, 21, 29) ............................................. 22
`B.
`“means for detecting an error” (claim 29) ........................................................... 23
`C.
`“means for generating a corrected instruction” (claim 30) .................................. 24
`D.
`“means for writing the corrected instruction back to the instruction cache”
`(claim 31) ............................................................................................................. 25
`CLAIM TERMS FOR U.S. PATENT NO. 7,810,002 (“’002 PATENT”) ..................... 27
`A.
`“scan interface” (claims 1, 11, 17) ....................................................................... 27
`B.
`“software layer” (claims 1, 17) ............................................................................ 29
`VII. CLAIM TERMS FOR U.S. PATENT NO. 8,870,404 (“’404 PATENT”) ..................... 30
`A.
`“transition time” (claims 1, 5) .............................................................................. 30
`
`V.
`
`VI.
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`
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`
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`-i-
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 3 of 42
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`TABLE OF CONTENTS
`(continued)
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`
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`Page
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`B.
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`“an allowed time for transitioning from a sleep state to an operating state”
`(claim 1) / “a time period allowed for transition from a sleep state to an
`operating state” (claims 11, 18) / “a time allowed for transition from a
`sleep state to an operating state” (claim 15) ........................................................ 33
`“means for processing” (claims 18, 19) ............................................................... 33
`C.
`“means for supplying a voltage” (claims 18, 19) ................................................. 34
`D.
`VIII. CONCLUSION ................................................................................................................ 35
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`-ii-
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 4 of 42
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`
`
`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Cases
`
`AFG Indus., Inc. v. Cardinal IG Co.,
`239 F.3d 1239 (Fed. Cir. 2001)..................................................................................................1
`
`Apex Inc. v. Raritan Comput., Inc.,
`187 F. Supp. 2d 141 (S.D.N.Y. 2002)....................................................................19, 24, 27, 35
`
`Bd. of Regents of the Univ. of Tex. Sys. v. BENQ Am. Corp.,
`533 F.3d 1362 (Fed. Cir. 2008)............................................................................................9, 11
`
`Blackboard, Inc. v. Desire2Learn Inc.,
`574 F.3d 1371 (Fed. Cir. 2009)................................................................................................27
`
`Bushnell Hawthorne, LLC v. Cisco Sys., Inc.,
`813 F. App'x 522, 527 (Fed. Cir. 2020) ...................................................................................10
`
`Chiuminatta Concrete Concepts v. Cardinal Indus.,
`145 F. 3d 1303 (Fed. Cir. 1998).........................................................................................20, 23
`
`Eon Corp. IP Holdings LLC v. Silver Spring Networks, Inc.,
`815 F.3d 1314 (Fed. Cir. 2016)..............................................................................................1, 3
`
`Ergo Licensing LLC v. CareFusion 303, Inc.,
`673 F.3d 1361 (Fed. Cir. 2012)................................................................................................25
`
`Game & Tech. Co. v. Activision Blizzard Inc.,
`926 F.3d 1370 (Fed. Cir. 2019)..................................................................................................6
`
`Ibormeith IP, LLC v. Mercedes–Benz USA, LLC,
`732 F.3d 1376 (Fed. Cir. 2013)..........................................................................................24, 25
`
`Meetrix IP, LLC v. Citrix Sys., Inc.,
`No. 1:16-CV-1033-LV, 2017 WL 5986191 (W.D. Tex. Dec. 1, 2017) ....................................7
`
`Nautilus, Inc. v. Biosig Instruments, Inc.,
`572 U.S. 898 (2014) .................................................................................................................10
`
`Nilssen v. Motorola, Inc.,
`80 F. Supp. 2d 921 (E.D. Ill. 2000)........................................................................19, 24, 27, 35
`
`Noah Sys., Inc. v. Intuit Inc.,
`675 F.3d 1302 (Fed. Cir. 2012)................................................................................................25
`
`
`
`iii
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 5 of 42
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`
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`O2 Micro Int’l, Ltd. v. Beyond Innovation Tech. Co.,
`521 F.3d 1351 (Fed. Cir. 2008)..................................................................................................1
`
`Omega Eng’g, Inc. v. Raytek Corp.,
`334 F.3d 1314 (Fed. Cir. 2003)..................................................................................................6
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................................1, 7, 30
`
`SimpleAir, Inc. v. Sony Ericsson Mobile Commc'ns AB,
`820 F.3d 419 (Fed. Cir. 2016)....................................................................................................8
`
`Sulzer Textil A.G. v. Picanol N.V.,
`358 F.3d 1356 (Fed. Cir. 2004)..................................................................................................1
`
`TNA Australia PTY Ltd. v. PPM Techs., LLC,
`293 F. Supp. 3d 626 (N.D. Tex. 2017) ....................................................................................30
`
`Triton Tech of Texas, LLC v. Nintendo of Am., Inc.,
`753 F.3d 1375 (Fed. Cir. 2014)................................................................................................25
`
`U.S. Surgical Corp. v. Ethicon, Inc.,
`103 F.3d 1554 (Fed. Cir. 1997)............................................................................................6, 30
`
`Statutes
`
`35 U.S.C. § 112 ...................................................................................................................... passim
`
`
`
`
`
`iv
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 6 of 42
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`Pursuant to the Amended Joint Proposed Scheduling Order (Dkt. No. 34), Defendant
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`Microchip Technology, Inc. (“Microchip”) submits its Opening Claim Construction Brief.
`
`I.
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`LEGAL STANDARD
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`The Court is well-versed in the principles of claim construction, as laid out by the Federal
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`Circuit in Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) (en banc) and its
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`progeny. Those principles need not be repeated here.
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`For a number of terms, Plaintiff HD Silicon Solutions, LLC (“HDSS” or “Plaintiff”)
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`proposes no construction beyond plain and ordinary meaning, while Microchip proposes an actual
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`construction. When “the parties present a fundamental dispute regarding the scope of a claim term,
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`it is the court’s duty to resolve it.” Eon Corp. IP Holdings LLC v. Silver Spring Networks, Inc.,
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`815 F.3d 1314, 1318 (Fed. Cir. 2016) (quoting O2 Micro Int’l, Ltd. v. Beyond Innovation Tech.
`
`Co., 521 F.3d 1351, 1362 (Fed. Cir. 2008)). Moreover, a “determination that a claim term ‘needs
`
`no construction’ or has the ‘plain and ordinary meaning’ may be inadequate when a term has more
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`than one ‘ordinary’ meaning or when reliance on a term’s ‘ordinary’ meaning does not resolve the
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`parties’ dispute.” Id. (quoting O2 Micro, 521 F.3d at 1361). Here, either Microchip’s
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`constructions are the “plain and ordinary meaning,” or there is no undisputed meaning to the terms.
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`HDSS should not be allowed to hide its disputed constructions in order to argue the issue later on.
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`A court does “not resolve the parties’ dispute by instructing the jury that the claims should
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`be given their plain and ordinary meaning.” Id., 1319. Rather, the trial court must “set forth an
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`express construction of the material claim terms in dispute” and “must instruct the jury on the
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`meanings to be attributed to all disputed terms used in the claims in suit . . . .” Id. (quoting AFG
`
`Indus., Inc. v. Cardinal IG Co., 239 F.3d 1239, 1247 (Fed. Cir. 2001) and Sulzer Textil A.G. v.
`
`Picanol N.V., 358 F.3d 1356, 1366 (Fed. Cir. 2004) (internal quotation marks omitted).
`
`
`
`1
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 7 of 42
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`II.
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`CLAIM TERMS FOR U.S. PATENT NO. 6,774,033 (“’033 PATENT”)
`
`A.
`
`“interconnect” (claim 1)
`
`Defendant’s Proposed Construction
`Plain and ordinary meaning (which is “a structure that
`electrically connects two or more circuit elements”).
`
`Plaintiff’s Proposed Construction
`Providing an electrically conductive
`connection.
`
`The term “interconnect” appears as part of the phrase “local interconnect layer.” In this
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`context, “interconnect” is a noun (not a verb) and should be given its plain and ordinary meaning
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`as proposed by Microchip. Plaintiff proposes that an “interconnect” (or “interconnect layer”) be
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`construed as a verb, which is inconsistent with the claim language and is likely to confuse the jury.
`
`B.
`
`“depositing a second film over the first film” (claim 1)
`
`Defendant’s Proposed Construction
`Depositing a second film above the top surface of the
`first film and the oxide layer, where a “film” is a thin
`layer of material having a thickness from top to bottom
`as its smallest dimension.
`
`Plaintiff’s Proposed Construction
`Plain and ordinary meaning.
`
`The ’033 patent discloses a process for forming the local interconnect layer for a
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`semiconductor chip. Ex. 1, Abstract.1 At a high level, the process starts by depositing a first film
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`(of titanium nitride) over an oxide layer and depositing a second film (of tungsten) over the first
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`film and the oxide layer. Id., 2:63-3:20. This is shown in Figure 2 below:
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`---------------------=......._ I 04 Tungsten film
`---------------------=-----103 TiN film
`
`===================================~----- 102 Oxide layer
`
`SUBSTRATE
`
`--. 1 OJ Substrate
`
`FIG.2
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`
`
`
`1 All exhibits are attached to the Declaration of Rachel M. Walsh in Support of Microchip’s
`Opening Claim Construction Brief and are hereafter referenced as (“Ex.”).
`
`
`
`2
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`Id., Fig. 2 (annotated). After both films have been deposited over the oxide layer, the interconnects
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`are formed by removing portions of the tungsten and TiN down to the oxide layer, by forming
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`masks over the tungsten film, etching the tungsten down to the top of the titanium nitride, and then
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`subsequently etching the titanium nitride down to the top of the oxide layer. Id., 3:66-4:20; Figs.
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`3-6. The material that remains (the tungsten and titanium nitride left on top of the oxide layer)
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`forms the interconnect lines of the local interconnect layer, as shown below:
`
`SO~
`
`al interconn~ect IOS Mask SO~
`
`cal interco; ~::~ask
`
`104 __________ _ ~ I
`
`· ~ """"""" fil••
`
`103 ___...... _______ ...._ __ _.__ ----------,,~
`-
`- - - - - -- -- - - -- --
`- - -~
`SUBSTRATE
`
`l03TiN film
`I OZ Oxide layer
`
`--....., 101 Substrate
`
`FIG. 5
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`
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`Id., Fig. 5 (annotated).
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`Consistent with this disclosure, claim 1 of the ’033 patent recites “depositing a first film
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`over an oxide layer, the first film comprising titanium nitride; and depositing a second film over
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`the first film, the second film comprising tungsten.” Id., 5:57-6:2. Microchip proposes a
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`construction of “depositing a second film over the first film” that (1) explains what constitutes a
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`“film” in the context of the ’033 patent and (2) makes clear that the word “over” means “above the
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`top surface” (in this case, above the top surface of the first film and oxide layer). Microchip’s
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`proposed construction is supported by the claims and specification of the ’033 patent. Plaintiff
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`simply contends that the phrase be given its ordinary meaning, yet offers no explanation for what
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`that meaning is, or whether it actually disputes the substance of Microchip’s proposed
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`construction. The term should be construed, and Microchip’s proposed construction should be
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`
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`3
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`adopted. See Eon Corp. IP Holdings LLC, 815 F.3d at 1318 (holding a construction of “plain and
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`ordinary meaning” is inadequate when it does not resolve the parties’ dispute).
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`Starting with the claims, a person of ordinary skill in the art would have understood that in
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`the context of the claims, “depositing over” means “depositing above the top surface of.”
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`For example, claim 1 recites “the first film and the second film forming a metal stack of the local
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`interconnect layer.” Ex. 1, 6:2-4. A person of ordinary skill in the art would have understood a
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`“stack” to refer to material arranged vertically on top of another. Similarly, claims 9, 11, and 12
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`refer to etching the first and second films. A person of ordinary skill in the art would have
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`understood that etching is a process that is applied from the top-down. See Ex. 7, 521.
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`The specification further illustrates these points. For example, Figures 2 and 5 annotated
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`above show a second (tungsten) film above the top surface of the first (titanium nitride) film and
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`the oxide layer, just as Microchip has proposed. See Ex. 1, Figs. 2 and 5; 2:63-4:20; see also, e.g.,
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`Ex. 8, 1252 (defining “over” as “[i]n or at a position above or higher than”); See Ex. 7, 110
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`(describing how thin films are deposited by attaching to a surface).
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`As to the word “film,” Microchip’s proposed construction of “thin layer of material having
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`a thickness from top to bottom as its smallest dimension” is also supported by the claims and
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`specification. Starting with the claims, claims 4-7 recite thicknesses between 300 and 600
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`Angstroms (an Angstrom is one ten-billionth of a meter), emphasizing that the claimed films are
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`thin. See also, Ex. 9, 1175 (defining “thin film technology” as “A technology in which a thin film
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`(a few hundred to a few thousand angstroms in thickness) is applied by vacuum deposition to an
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`insulating substrate.”) (original emphasis). Similarly, claim 8 recites a “sheet resistance,” which
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`a person of ordinary skill in the art would have understood to also support Microchip’s
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`construction, since “sheets” typically refer to layers having a thickness from top to bottom as its
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`4
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`smallest dimension (e.g., a sheet of paper). See also Ex. 7, 109 (“The thin film, by its very
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`definition has a substantially higher surface-to-volume ratio than does a bulk material.”)
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`The specification supports this interpretation too. Figure 2, annotated above, shows the
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`first and second films depicted as thin layers having a thickness from top to bottom as their smallest
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`dimension. According to the ’033 patent, the first film “may be deposited to a thickness of about
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`200 to 300 Angstroms, preferably to a thickness of about 300 Angstroms,” and the second film
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`“may be deposited to a thickness of about 100 to 300 Angstroms, preferably to a thickness of about
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`300 Angstroms.” Ex. 1, 3:1-20. The ’033 specification also states, for example, that “a local
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`interconnect layer has to be relatively thin” (id., 1:37-38), that its purported invention “allows the
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`metal stack [which includes both the first and second films] to be relatively thin, while keeping
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`resistivity relatively low,” and that the “thin metal stack reduces the aspect ratio of the resulting
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`interconnect line.” Id., 3:42-45. A person of ordinary skill in the art would have understood from
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`each of these disclosures that the claimed “films” are thin layers of material having a top-to-bottom
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`thickness that is smaller than its other dimensions. See also Ex. 10, 718 (defining “film” as “a thin
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`layer”).
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`C.
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`“metal stack” (claims 1, 8, 15) / “the first film and the second film forming a
`metal stack” (claim 1)
`
`Defendant’s Proposed Construction
`“metal stack” – “the arrangement over the
`oxide layer of one metal film above the top
`surface of another metal film”
`“the first film and the second film forming a
`metal stack” – “the arrangement over the
`oxide layer of the second metal film above
`the top surface of the first metal film”
`
`Plaintiff’s Proposed Construction
`A “metal stack” is a stack consisting of two of
`more layers of metal (and no non-metal
`layers).
`Plain and ordinary meaning applies to “the
`first film and the second film forming a metal
`stack,” with “metal stack” construed as
`indicated.
`
`Claim 1 recites “the first film and the second film forming a metal stack of the local
`
`interconnect layer.” Microchip has proposed that the full phrase “the first film and the second film
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`5
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`forming a metal stack” be construed, whereas Plaintiff seeks to construe only the phrase “metal
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`stack.” In either case, Microchip’s proposed construction is drawn from the claims and the
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`specification, and Plaintiff’s proposed construction is not.
`
` Starting with the claim language, claim 1 recites “depositing a first film over an oxide
`
`layer” and “depositing a second film over the first film.” Ex. 1, 5:57, 6:1. By reciting that the first
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`film and second film form a metal stack, the ’033 patent simply requires an arrangement over the
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`oxide layer of the second metal film above the top surface of the first metal film, just as Microchip
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`has proposed. The specification also states that the metal stack “comprises a film 104 of tungsten
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`over a film 103 of titanium nitride,” which is also consistent with Microchip’s proposed
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`construction. Id., 3:17-20; see also id., 3:35-37 (“a metal stack comprising tungsten over titanium
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`nitride”).
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`Plaintiff’s construction, by contrast, boils down to construing “metal stack” as a stack of
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`metal, plus a negative limitation (“and no non-metal layers”). Construing a “metal stack” as a
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`stack of metal is entirely unhelpful. U.S. Surgical Corp. v. Ethicon, Inc., 103 F.3d 1554, 1568
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`(Fed. Cir. 1997) (claim construction “is not an obligatory exercise in redundancy”).
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`More importantly, Plaintiff’s proposed negative limitation is neither anchored in the explicit claim
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`language nor supported by an express disclaimer, as would be required to read a negative limitation
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`into the claims. See Omega Eng’g, Inc. v. Raytek Corp., 334 F.3d 1314, 1322-23 (Fed. Cir. 2003).
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`To the contrary, the claims merely require a second film be deposited over, or on top of, a first
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`film and oxide layer. The specification also explains that “‘over’ . . . refer[s] to the relative
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`placement of two materials that may or may not be directly in contact with each other. That is,
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`the two materials may be separated by another material.” Ex. 1, 2:18-21. Plaintiff then tries to
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`achieve the same negative limitation by injecting the close-ended phrase “consisting of” into the
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`6
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`open-ended “comprising” language of claim 1. Id., claim 1; see also, e.g., Game & Tech. Co. v.
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`Activision Blizzard Inc., 926 F.3d 1370, 1378 (Fed. Cir. 2019) (“comprising” is well understood
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`in the patent context to mean “including but not limited to”). This is an improper negative
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`limitation and should not be adopted.
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`D.
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`“in-situ” (claim 2)
`
`Defendant’s Proposed Construction
`Using the same tool without a
`vacuum break in between steps.
`
`Plaintiff’s Proposed Construction
`Plain and ordinary meaning.
`Alternatively, within the same physical vapor
`deposition system, which may have multiple chambers.
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`Claim 2 recites “wherein the first film and the second film are deposited in-situ.”
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`The parties agree that depositing films “in-situ” involves using the same tool or system. Plaintiff’s
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`proposal, however, ignores what a person of ordinary skill in the art would have understood to be
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`the most important aspect of in-situ processing: that the processes occur in the same vacuum
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`environment and without exposing the wafer to air between steps. This is true regardless of
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`whether the tool has a single chamber or a multiple chambers, and even though the patent does not
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`explicitly define “in-situ.” For example, the widely-used Wolf and Tauber textbook equates
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`“in-situ” deposition as being conducted in the same vacuum environment. See Ex. 7, 520
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`(“conducted in the same vacuum environment in which the overlying film will be deposited (in
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`situ).”) (emphasis in original); see also Meetrix IP, LLC v. Citrix Sys., Inc., No. 1:16-CV-1033-
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`LV, 2017 WL 5986191, at *7 (W.D. Tex. Dec. 1, 2017) (“Given little to no intrinsic evidence, the
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`court looks to extrinsic evidence to establish the plain and ordinary meaning of ‘authenticate.’”)
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`(citing Phillips, 415 F.3d at 1318)). A person of ordinary skill in the art would have understood,
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`for example, that depositing materials without breaking vacuum (i.e., in situ), allows for efficient
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`process flow. See Ex. 1, 3:38-41 (“the tungsten and titanium nitride may be deposited in-situ using
`
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`7
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`the same physical vapor deposition system, thereby allowing for an efficient process flow”).
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`Microchip’s proposed construction reflects this and should be adopted.
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`III. CLAIM TERMS FOR U.S. PATENT NO. 7,154,299 (“’299 PATENT”)
`
`A.
`
`“via no circuit element other than one or more switch elements” (claim 1) /
`“via no circuit element other than one or more pass gates” (claims 5, 7-9, 13,
`14, 16)
`
`Defendant’s Proposed Construction
`Using only wires and pass
`transistor switches.
`
`Plaintiff’s Proposed Construction
`A “circuit element” is a combinatorial-logic or
`sequential-logic element or combinations thereof.
`A “pass gate” is a controllable connection implemented
`using a transistor.
`Plain and ordinary meaning for Microchip’s proposed
`phrases, subject to those constructions.
`
`The parties disagree about whether a “circuit element” should be limited to only
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`combinatorial-logic elements or sequential-logic elements, rather than any circuit element.
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`The intrinsic record supports Microchip’s proposed construction.
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`Microchip proposes that the term be construed consistent with the claim language, which
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`states: “via no circuit element other than one or more switch elements” (or pass gates, or switches).
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`The plain language implies that a switch (or pass gate) is a type of circuit element. A “switch” or
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`“pass gate” is a specific circuit element, and refers to a simple transistor that can be turned on or
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`off, to either allow or block a signal from passing through. See, e.g., Ex. 11, 1133 (defining
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`“switch” as a “device for making, breaking, or changing the connections in an electric circuit.”).
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`Indeed, Plaintiff agrees that a “pass gate” is “a controllable connection implemented using a
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`transistor,” which is a simple on/off switch. See, e.g., Ex. 12 (defining “switch” as “a device that
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`allows current flow when closed and provides isolation when open.”). Simply put, a switch is
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`neither a combinatorial-logic or sequential-logic element or combinations thereof.
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`Unlike the limiting terms “defined circuit element” or “logic circuit element,” the term
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`8
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`MICROCHIP TECHNOLOGY INC. EXHIBIT NO. 1057
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 14 of 42
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`“circuit element” is not defined in the specification. See SimpleAir, Inc. v. Sony Ericsson Mobile
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`Commc'ns AB, 820 F.3d 419, 431 (Fed. Cir. 2016) (stating that a claim term that is different from
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`a defined term has a different definition). “Circuit element,” however, is well-understood by those
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`of skill in the art. Microchip’s construction is consistent with the common usage of the term,
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`which is broadly used to refer to any electronic components in a circuit other than wires (including,
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`e.g., resistors, inductors, capacitors, multiplexers, etc.). See Ex. 13, 170 (defining a “circuit
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`element” as a “basic constituent part of a circuit, exclusive of interconnections”).
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`Plaintiff’s limiting construction incorrectly attributes the definitions of “defined circuit
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`element” or “logic-circuit element” to the term “circuit element.” See, e.g., Ex. 2, 2:3-4
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`(“The defined circuit elements are combinatorial (30s) or sequential logic (36s) elements or
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`combinations thereof”) (emphasis added). But a “circuit element” is not the same as a “defined
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`circuit element” or “logic circuit element.” Indeed, the claim language also distinguishes between
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`the terms, because it uses the terms “defined sequential circuit element” or “logic circuit element”
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`in the same sentence as “circuit element.” See, e.g., id., claim 1. If the terms referred to the same
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`structures, the claim language would also use the same words. See Bd. of Regents of the Univ. of
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`Tex. Sys. v. BENQ Am. Corp., 533 F.3d 1362, 1371 (Fed. Cir. 2008) (“Different claim terms are
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`presumed to have different meanings.”).
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`B.
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`“no circuit element” (claims 1, 5, 7-9, 13, 14, 16, 19, 23)
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`Defendant’s Proposed Construction
`No electronic component other than
`wires.
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`Plaintiff’s Proposed Construction
`A “circuit element” is a combinatorial-logic or
`sequential-logic element or combinations thereof.
`Plain and ordinary meaning for Microchip’s proposed
`phrases, subject to those constructions.
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`For the reasons discussed above, the term “no circuit element” should be defined as “no
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`electronic component other than wires,” because it is consistent with the claim language and the
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`9
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 15 of 42
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`plain and ordinary meaning of “circuit element.” A “circuit element” should not be limited to “a
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`combinatorial-logic or sequential-logic element or combinations thereof” because that is the proper
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`definition of a “defined circuit element.” See Ex. 2, 2:3-4 (emphasis added).
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`C.
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`“the logic circuit element” (claim 1)
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`Defendant’s Proposed Construction
`Indefinite.
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`Plaintiff’s Proposed Construction
`The sequential logic circuit element.
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`This term is indefinite for lacking an antecedent basis, and it is not reasonably certain
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`what “the logic circuit element” refers to. The first portion of claim 1 recites that the input of “a
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`defined sequential circuit element” in a routing domain is connected to the common interconnect
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`matrix. Ex. 2, 5:27-37. In the last clause, claim 1 recites “an output of the logic circuit
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`element,” which is also connected to the common interconnect matrix. Id., 5:37-40. The claim
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`never recites a “logic circuit element” prior to this, and it is unclear whether this is a the same as
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`the “defined sequential circuit element,” another combinatorial-logic or sequential-logic element,
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`some other kind of logic circuit element, or some combination thereof.
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`Lack of antecedent basis in a claim can render it invalid. See Bushnell Hawthorne, LLC
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`v. Cisco Sys., Inc., 813 F. App'x 522, 527 (Fed. Cir. 2020). Here, the term “logic circuit
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`element” lacks antecedent basis and is open to different interpretations. See Nautilus, Inc. v.
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`Biosig Instruments, Inc., 572 U.S. 898, 901 (2014) (“a patent is invalid for indefiniteness if its
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`claims, read in light of the specification . . . fail to inform, with reasonable certainty, those
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`skilled in the art about the scope of the invention.”). The specification only further increases the
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`ambiguity of this term. Figure 8 of the ’299 patent, which depicts “the circuit diagram of an
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`interconnecting circuit block modified according to an embodiment of the invention” (Ex. 2,
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`2:39-41) illustrates and supports at least two distinct interpretations.
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`Under one interpretation, the “logic circuit element” could refer to the flip-flop 74, a
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`10
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`MICROCHIP TECHNOLOGY INC. EXHIBIT NO. 1057
`Page 15 of 42
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`Case 6:20-cv-01092-ADA Document 38 Filed 08/17/21 Page 16 of 42
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`sequential logic circuit element, because the output q of the flip-flop 74 is connected to node M
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`(element 80) (via the blue path below), part of the common interconnect matrix. See id., 4:1-4.
`
`FIG. 8
`
`~
`
`Tl
`
`76-2 ~
`
`76-3---::J'.?
`
`------
`
`77-2
`
`77-3
`
`7 -2
`
`A2
`
`75.3
`A3
`
`76• '.:!...----1:'._m-l
`
`FF
`
`79-n
`
`,, _/
`
`'-
`77m
`
`75m-l
`
`Am-I
`
`/
`
`75m
`
`Am
`
`
`
`Id., Fig. 8 (annotated).
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`Under a second interpretation, the specification also teaches that the “logic circuit element”
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`may refer to a combinatorial-logic or sequential-logic element completely separate from the
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`“defined sequential circuit element” (i.e., flip-flop 74). For example, as shown above in Figure 8,
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`the output from the logic block providing signal A1 (element 72) is also connected to Node M
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`(element 80) (via the red path above), which is part of a common interconnect. See id., 3:65-4:1.
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`Given that claim 1 uses both terms (“logic circuit element” and “defined sequential circuit
`
`element”), the two terms are presumed to have different meaning, and to refer to different
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`structures. See Bd. of Regents of the Univ. of Tex. Sys., 533 F.3d at 1371 (“Different claim terms