Case 6:20-cv-01092-ADA Document 1 Filed 11/30/20 Page 1 of 42
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`
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
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`
`
`Plaintiff,
`
`
`
`v.
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`HD SILICON SOLUTIONS LLC,
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`
`
`
`
`MICROCHIP TECHNOLOGY INC.,
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`
`
`
`
`Civil Action No. 6:20-cv-1092
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`PATENT CASE
`
`JURY TRIAL DEMANDED
`
`
`
`Defendant.
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`COMPLAINT FOR PATENT INFRINGEMENT
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`
`
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`This is an action for patent infringement in which plaintiff HD Silicon Solutions LLC
`
`(“HDSS”), makes the following allegations against defendant Microchip Technology Inc.
`
`(“MTI”):
`
`BACKGROUND
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`1.
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`This lawsuit asserts causes of action for infringement of HDSS’s patents
`
`referenced in Counts One through Seven herein (collectively, the “Asserted Patents”).
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`2.
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`The Asserted Patents address various core
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`technologies
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`in modern
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`semiconductors, including microcontrollers, microprocessors, and programmable gate arrays.
`
`THE PARTIES
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`3.
`
`Plaintiff HDSS is an intellectual property licensing company. HDSS is organized
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`and existing as a limited liability company under the laws of Texas with a principal place of
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`business at 5900 Balcones Drive, Suite 100, Austin, Texas 78731.
`
`4.
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`Defendant MTI is a corporation organized and existing under the laws of
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`Delaware, with a principal place of business at 2355 West Chandler Boulevard, Chandler,
`
`Arizona 85224. MTI is doing business, either directly or through its agents, on an ongoing basis
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`1
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`in this judicial district and elsewhere in the United States, and has a regular and established place
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`of business in this judicial district. MTI may be served through its registered agent The
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`Corporation Trust Company, Corporation Trust Center, 1209 Orange Street, Wilmington,
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`Delaware 19801.
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`JURISDICTION AND VENUE
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`5.
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`This action arises under the patent laws of the United States, Title 35 of the
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`United States Code, including in particular 35 U.S.C. § 271.
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`6.
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`7.
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`This Court has subject matter jurisdiction under 28 U.S.C. §§ 1331 and 1338(a).
`
`This Court has personal jurisdiction over MTI because MTI has minimum
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`contacts with Texas and this district such that this venue is a fair and reasonable one. MTI
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`conducts substantial business in this forum, including (i) engaging in the infringing conduct
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`alleged herein and (ii) regularly doing or soliciting business, engaging in other persistent courses
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`of conduct, and/or deriving substantial revenue from goods and services provided to companies
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`and individuals in Texas and in this district.
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`8.
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`Venue in the Western District of Texas is proper under 28 U.S.C. §§ 1391(b) and
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`(c) and 1400(b).
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`9.
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`Upon information and belief, MTI has committed infringing acts in this judicial
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`district by making, using, offering for sale, selling, or importing products or services that infringe
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`the Asserted Patents, or by inducing others to infringe the Asserted Patents. On information and
`
`belief, MTI maintains a “regular and established” place of business in this district, including by
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`maintaining and operating one or more places in this district where research, development, or
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`sales are conducted or where customer service is provided.
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`10.
`
`On information and belief, MTI has a regular and established physical presence in
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`the district, including but not limited to, ownership of or control over property, equipment, or
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`2
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`inventory. For example, MTI has an office located at 8601 Ranch Road 2222, Park Centre
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`Building 3, Austin, Texas 78730, which lies within this federal judicial district.
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`11.
`
`In other recent actions, MTI has either admitted or not contested that this federal
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`judicial district is a proper venue for patent infringement actions against it. See, e.g., Answer to
`
`1st Am. Compl. ¶ 14, Vantage Micro LLC v. Microchip Tech. Inc., No. W-19-cv-581 (W.D. Tex.
`
`Feb. 18, 2020), ECF No. 22, answering 1st Am. Compl. ¶ 14, ECF No. 16 (Feb. 4, 2020);
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`Answer ¶ 5, Far North Patents, LLC v. Microchip Tech. Inc., No. 6:20-cv-221 (W.D. Tex. Jun.
`
`23, 2020), ECF No. 17, answering Compl. ¶ 5, ECF. No. 1 (Mar. 25, 2020). MTI has also
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`admitted or failed to contest that it has transacted business in this district. See, e.g., Answer to 1st
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`Am. Compl. ¶ 13, Vantage Micro LLC v. Microchip Tech. Inc., No. W-19-cv-581 (W.D. Tex.
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`Feb. 18, 2020), ECF No. 22, answering 1st Am. Compl. ¶ 13, ECF No. 16 (Feb. 4, 2020).
`
`COUNT ONE
`Infringement of U.S. Patent No. 7,260,731
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`12.
`
`Plaintiff repeats and incorporates by reference each preceding paragraph as if
`
`fully set forth herein and further states:
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`13.
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`On August 21, 2007, the United States Patent and Trademark Office duly and
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`legally issued U.S. Patent No. 7,260,731 B1 (“the ’731 Patent”), entitled “Saving power when in
`
`or transitioning to a static mode of a processor.” A true and correct copy of that patent is attached
`
`as Exhibit 1.
`
`14.
`
`HDSS is the owner by assignment of the ’731 Patent and holds all substantial
`
`rights in that patent, including the sole and exclusive right to sue and recover for any and all
`
`infringement.
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`15.
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`Claim 6 of the ’731 Patent recites:
`
`6. A method for reducing power utilized by a system having a least a
`processor, comprising the steps of:
`
`
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`3
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`determining that the processor is transitioning from a computing mode
`to a mode in which a system clock to the processor is disabled,
`
`reducing core voltage being furnished by a voltage regulator to the
`processor to a value sufficient to maintain state during the mode in
`which the system clock is disabled, and
`
`transferring operation of the voltage regulator furnishing core in a
`mode in which power is dissipated during a voltage transition in
`reduction in core voltage to a mode in which power is saved during
`said voltage transition in the reduction in core voltage when it is
`determined that the processor is transitioning from the computing
`mode to the mode in which the system clock to the processor is
`disabled.
`
`16.
`
`By way of example, MTI’s PIC24 family of 16-bit microcontroller chips utilize
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`what MTI refers to as “eXtreme Low-Power or XLP Technology.”1 This XLP Technology
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`provides different power management modes, including a “Low-Voltage/Retention Sleep” mode
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`at a reduced voltage level, to reduce power consumption by the chip’s processor. In this mode,
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`the core voltage drops from an operating voltage of 1.8V (or more) to 1.2V and the main CPU
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`clock is shut down, but device state is maintained.2
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`17.
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`The “’731 Accused Chips” include at least each of the aforementioned chips as
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`well as any other MTI chips utilizing XLP Technology supporting a Low-Voltage/Retention
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`Sleep mode.
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`18. MTI has directly infringed and continues to directly infringe one or more claims,
`
`including at least claim 6, of the ’731 Patent in violation of 35 U.S.C. § 271(a) by, without
`
`authority, making, using, offering to sell, or selling in the United States or importing into the
`
`United States the ’731 Accused Chips.
`
`
`1 eXtreme Low-Power (XLP) PIC Microcontrollers: An Introduction to Microchip’s Low-Power
`Devices, AN1267, at 1 (2017),
`http://ww1.microchip.com/downloads/en/AppNotes/00001267b.pdf.
`2 Id. at 4–5.
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`4
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`19.
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`For example, the ’731 Accused Chips implement a method for reducing power
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`utilized by the processor. The method utilizes an on-board voltage regulator that, according to
`
`MTI, “has the ability to alter functionality to provide power savings.” The voltage regulator
`
`includes “two basic modules: the Voltage Regulator (VREG) and the Retention Regulator
`
`(RETREG).” In the regular operating “Run” mode of the ’731 Accused Chips, “the main VREG
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`is providing a regulated voltage with enough current to supply a device running at full speed.” In
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`this mode, the RETREG “may or may not be running, but is unused.” In the Low-
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`Voltage/Retention Sleep mode, “the device is in Sleep and all regulated voltage is provided
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`solely by the Retention Regulator.”3
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`20. When the ’731 Accused Chips determine that the processor is transitioning from
`
`Run mode to Low-Voltage/Retention Sleep mode, the voltage regulator transitions the core
`
`voltage to the processor down to 1.2V and during the transition turns off the VREG and provides
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`voltage solely with the RETREG (also known the “low-voltage/retention regulator”). This
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`changes the voltage regulator from a regulation mode in which power is dissipated to one in
`
`which power is saved during the voltage transition.
`
`21.
`
`In addition, MTI has indirectly infringed and continues to indirectly infringe the
`
`’731 Patent in violation of 35 U.S.C. § 271(b) by taking active steps to encourage and facilitate
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`direct infringement by others, including OEMs, agent-subsidiaries, affiliates, partners, service
`
`providers, manufacturers, importers, resellers, customers, and/or end users, in this district and
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`elsewhere in the United States, through the dissemination of the ’731 Accused Chips and the
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`creation and dissemination of promotional and marketing materials, supporting materials,
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`instructions, product manuals, and/or technical information relating to such products (including
`
`
`3 PIC24FV32KA304 Family Datasheet, DS30009995E, at 133 (2017),
`http://ww1.microchip.com/downloads/en/DeviceDoc/30009995e.pdf.
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`the materials previously cited) with knowledge and the specific intent that its efforts will result in
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`the direct infringement of the ’731 Patent.
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`22.
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`For example, MTI took active steps to encourage end users to use the ’731
`
`Accused Chips in the United States in a manner it knows will directly infringe each element of
`
`one or more claims, including at least claim 6, of the ’731 Patent, including by selling the chips
`
`and promoting and instructing on their use despite knowing of the patent and the fact that such
`
`acts will cause the user to use the chip in a manner that infringes the patent. MTI continues to
`
`undertake the above-identified active steps after receiving notice of the ’731 Patent and how
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`those steps induce infringement of that patent.
`
`23.
`
`In addition, MTI has indirectly infringed and continues to indirectly infringe the
`
`’731 Patent in violation of 35 U.S.C. § 271(c) by selling or offering to sell in the United States,
`
`or importing into the United States, the ’731 Accused Chips with knowledge that they are
`
`especially designed or adapted to operate in a manner that infringes that patent and despite the
`
`fact that the infringing technology or aspects of the chips are not a staple article of commerce
`
`suitable for substantial non-infringing use.
`
`24.
`
`For example, MTI is aware that the functionality included in the ’731 Accused
`
`Chips enables such chips to reduce power consumption as described above and that such
`
`functionality infringes the ’731 Patent, including at least claim 6. MTI continues to sell and offer
`
`to sell such chips in the United States after receiving notice of the ’731 Patent and how the chips’
`
`functionality infringes that patent.
`
`25.
`
`The infringing aspects of the ’731 Accused Chips can be used only in a manner
`
`that infringes the ’731 Patent and thus have no substantial non-infringing uses. The infringing
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`aspects of those instrumentalities otherwise have no meaningful use, let alone any meaningful
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`non-infringing use.
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`26. MTI’s acts of infringement have caused and continue to cause damage to HDSS,
`
`and HDSS is entitled to recover from MTI the damages it has sustained as a result of those
`
`wrongful acts in an amount subject to proof at trial. MTI’s infringement of HDSS’s rights under
`
`the ’731 Patent will continue to damage HDSS, causing irreparable harm for which there is no
`
`adequate remedy at law, unless enjoined by this Court.
`
`COUNT TWO
`Infringement of U.S. Patent No. 7,870,404
`
`27.
`
`Plaintiff repeats and incorporates by reference each preceding paragraph as if
`
`fully set forth herein and further states:
`
`28.
`
`On January 11, 2011, the United States Patent and Trademark Office duly and
`
`legally issued U.S. Patent No. 7,870,404 B2 (“the ’404 Patent”), entitled “Transitioning to and
`
`from a sleep state of a processor.” A true and correct copy of that patent is attached as Exhibit 2.
`
`29.
`
`HDSS is the owner by assignment of the ’404 Patent and holds all substantial
`
`rights in that patent, including the sole and exclusive right to sue and recover for any and all
`
`infringement.
`
`30.
`
`Claim 1 of the ’404 Patent recites:
`
`1. A computer system comprising:
`
`a processing unit;
`
`circuitry coupled to the processing unit, said circuitry configured to
`provide to said processing unit:
`
`a sleep voltage;
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`a first operating voltage; and
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`a second operating voltage that is less than the first operating
`voltage;
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`wherein said computer system has a first transition time for
`transitioning from said sleep voltage to said first operating voltage;
`
`wherein said computer system has a second transition time for
`transitioning from said sleep voltage to said second operating
`voltage;
`
`wherein said second transition time is within an allowed time for
`transitioning from a sleep state to an operating state; and
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`wherein said first transition time is greater than said allowed time.
`
`31.
`
`By way of example, MTI’s PIC24FV32KA304 and other members of MTI’s
`
`PIC24 family of 16-bit microcontroller chips utilize “eXtreme Low-Power” (XLP) technology
`
`providing for “sleep” and “low-voltage/retention sleep” power-saving modes. The “’404
`
`Accused Chips” include at least each of the aforementioned chips as well as any other MTI chips
`
`utilizing XLP technology.
`
`32. MTI has directly infringed and continues to directly infringe one or more claims,
`
`including at least claim 1, of the ’404 Patent in violation of 35 U.S.C. § 271(a) by, without
`
`authority, making, offering to sell, or selling in the United States or importing into the United
`
`States the ’404 Accused Chips.
`
`33.
`
`The ’404 Accused Chips include a CPU processor and an adjustable voltage
`
`supply for the processor in the form of “a Voltage Regulator that has the ability to alter
`
`functionality to provide power savings” or “VREG.” The adjustable voltage supply also includes
`
`a “Retention Regulator (RETREG).” According to MTI, “[w]ith the combination of VREG and
`
`RETREG,” several power modes are available.4
`
`
`4 DS30009995E, supra note 3, at 1, 133.
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`34.
`
`The voltage regulator of the ’404 Accused Chips is configured to output various
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`operating voltages ranging from, for example, 2.0V at the low end to 3.2V–5.5V at the high end.
`
`According to MTI, the figure below shows a “PIC24FV32KA304 voltage-frequency graph
`
`(industrial and extended).”5 As shown in the figure, the various operating voltages have
`
`corresponding supported operating frequencies.
`
`5.SV
`
`3.2W
`
`2.Q[JI/
`
`5.SV
`
`3.20V
`
`0
`
`a-
`<!, .. C>
`
`J!
`~
`
`8 MHz
`
`Fr•qu•ncy
`
`32MHZ
`
`Not@:
`
`FO< frequencies between 8 MHz and 32 MHZ, FMAX = 20 MHZ • (Voo - 2.0) + 8 MHZ.
`
`
`
`Figure 1
`
`35.
`
`These operating voltages support the chips’ “Run Mode.” According to MTI, “In
`
`Run mode, the main VREG is providing a regulated voltage with enough current to supply a
`
`device running at full speed.”6
`
`36.
`
`The voltage regulator of the ’404 Accused Chips is also configured to output a
`
`sleep voltage, which is the voltage supporting the mode that MTI describes as “Retention Sleep
`
`mode.” According to MTI, “In Retention Sleep mode, the device is in Sleep and all regulated
`
`voltage is provided solely by the Retention Regulator. Consequently, this mode has lower power
`
`consumption than regular Sleep mode, but is also limited in terms of how much functionality can
`
`5 Id. at 264 & Fig. 29-1.
`6 Id. at 264; AN1267, supra note 1, at 133.
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`be enabled.”7 According to MTI, “Low-Voltage/Retention Sleep mode is similar to Sleep mode”
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`except that “the low-voltage/retention regulator allows the core digital logic voltage (VCORE) to
`
`drop to 1.2V. This permits an incremental reduction in power consumption over what would be
`
`required if VCORE was maintained at [an operating] level.”8 When the processor transitions from
`
`“Low-Voltage/Retention Sleep mode” into “Run mode,” the voltage regulator returns to
`
`outputting an operating voltage.
`
`37.
`
`On information and belief, the adjustable voltage supply transitions from “Low-
`
`Voltage/Retention Sleep mode” to a higher operating voltage in a time period greater than the
`
`time period allowed for transition to a lower operating voltage. According to MTI, “Low-
`
`Voltage Sleep mode requires a longer wake-up time than Sleep mode, due to the additional time
`
`required to bring [the core voltage] back to [an operating voltage].”9 The transition to 3.2V, for
`
`example, takes longer than the transition to 2.0V because, among other reasons, the frequency
`
`must be increased, as shown in Figure 1 above, from 8 Mhz to 32 Mhz, which is done over a
`
`period of additional time.
`
`38.
`
`In addition, MTI has indirectly infringed and continues to indirectly infringe the
`
`’404 Patent in violation of 35 U.S.C. § 271(b) by taking active steps to encourage and facilitate
`
`direct infringement by others, including OEMs, agent-subsidiaries, affiliates, partners, service
`
`providers, manufacturers, importers, resellers, customers, and/or end users, in this district and
`
`elsewhere in the United States, through the dissemination of the ’404 Accused Chips and the
`
`creation and dissemination of promotional and marketing materials, supporting materials,
`
`instructions, product manuals, and/or technical information relating to such products (including
`
`
`7 DS30009995E, supra note 3, at 133.
`8 AN1267, supra note 1, at 5.
`9 AN1267, supra note 1, at 5.
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`the materials previously cited) with knowledge and the specific intent that its efforts will result in
`
`the direct infringement of the ’404 Patent.
`
`39.
`
`For example, MTI took active steps to encourage end users to use the ’404
`
`Accused Chips in the United States in a manner it knows will directly infringe each element of
`
`one or more claims of the ’404 Patent, including by selling the chips and promoting and
`
`instructing on their use despite knowing of the patent and the fact that such acts will cause the
`
`user to use the chip in a manner that infringes the patent. MTI continues to undertake the above-
`
`identified active steps after receiving notice of the ’404 Patent and how those steps induce
`
`infringement of that patent.
`
`40.
`
`In addition, MTI has indirectly infringed and continues to indirectly infringe the
`
`’404 Patent in violation of 35 U.S.C. § 271(c) by selling or offering to sell in the United States,
`
`or importing into the United States, the ’404 Accused Chips with knowledge that they are
`
`especially designed or adapted to operate in a manner that infringes that patent and despite the
`
`fact that the infringing technology or aspects of the chips are not a staple article of commerce
`
`suitable for substantial non-infringing use.
`
`41.
`
`For example, MTI is aware that the functionality included in the ’404 Accused
`
`Chips enables such chips to transition between voltages as described above and that such
`
`functionality infringes the ’404 Patent. MTI continues to sell and offer to sell such chips in the
`
`United States after receiving notice of the ’404 Patent and how the chips’ functionality infringes
`
`that patent.
`
`42.
`
`The infringing aspects of the ’404 Accused Chips can be used only in a manner
`
`that infringes the ’404 Patent and thus have no substantial non-infringing uses. The infringing
`
`
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`aspects of those instrumentalities otherwise have no meaningful use, let alone any meaningful
`
`non-infringing use.
`
`43. MTI’s acts of infringement have caused and continue to cause damage to HDSS,
`
`and HDSS is entitled to recover from MTI the damages it has sustained as a result of those
`
`wrongful acts in an amount subject to proof at trial. MTI’s infringement of HDSS’s rights under
`
`the ’404 Patent will continue to damage HDSS, causing irreparable harm for which there is no
`
`adequate remedy at law, unless enjoined by this Court.
`
`COUNT THREE
`Infringement of U.S. Patent No. 7,810,002
`
`44.
`
`Plaintiff repeats and incorporates by reference each preceding paragraph as if
`
`fully set forth herein and further states:
`
`45.
`
`On October 5, 2010, the United States Patent and Trademark Office duly and
`
`legally issued U.S. Patent No. 7,810,002 B2 (“the ’002 Patent”), entitled “Providing trusted
`
`access to a JTAG scan interface in a microprocessor.” A true and correct copy of that patent is
`
`attached as Exhibit 3.
`
`46.
`
`The ’002 Patent teaches a method for securing access to the trusted resources of a
`
`secure processor. Such processors contain secret information, such as cryptographic keys,
`
`authentication information, or runtime register states, that normally should not leave the secure
`
`processor. However, it is often useful to have an interface that provides access to such
`
`information for purposes of debugging, profiling, aiding the manufacturing process, testing, or
`
`diagnosing defects of a chip. Some preexisting processors allowed entirely unsecured access to
`
`such information from outside the chip, such as through a documented software or scan chain
`
`interface, whereas others may have allowed access through an undocumented hardware interface,
`
`relying on the absence of public documentation as the sole basis for security.
`
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`47.
`
`The ’002 Patent teaches the use of a trusted software layer in conjunction with a
`
`secure processor, such that only the trusted software layer, and not any untrusted software, has
`
`access to the ability to enable the scan chain interface providing access to the internal secrets. At
`
`the time of the invention and at the time of the filing of the application leading to the ’002 Patent,
`
`the use of such a trusted software layer in conjunction with a secure processor was
`
`unconventional, uncommon, and not well-understood in the industry.
`
`48.
`
`The trusted software is in a unique position to be able to securely authenticate the
`
`validity of a request to allow access to the scan chain interface and, if the request is valid, enable
`
`access to the scan chain interface. The use of such a trusted software layer in conjunction with a
`
`secure processor prevents untrusted software from enabling access to the internal secrets of the
`
`processor. This provides a level of security unavailable in prior processors. In addition, the
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`performance of authentication operations at the trusted software layer, instead of in hardware,
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`minimizes the number of hardware components necessary in the secure processor to support the
`
`authentication process. This also potentially allows the authentication operation to occur even
`
`though portions of a chip or processor may be malfunctioning, as may often be the case when the
`
`purpose of accessing the interface is to diagnose defects. Furthermore, because the authentication
`
`operation occurs in software, it is more easily modified, enhanced, or patched than any
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`hardware-based solution.
`
`49.
`
`HDSS is the owner by assignment of the ’002 Patent and holds all substantial
`
`rights in that patent, including the sole and exclusive right to sue and recover for any and all
`
`infringement.
`
`50.
`
`Claim 1 of the ’002 Patent recites:
`
`1. A method for securing a scan chain architecture, said method
`comprising:
`
`
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`disabling a scan interface in a system comprising a secure processor
`and a software layer, wherein said software layer is authorized to
`access trusted resources in said secure processor;
`
`receiving authentication information at the software layer, wherein
`said authentication information if valid provides access to said
`scan interface;
`
`verifying whether said authentication information is valid using said
`software layer; and
`
`allowing access to said scan interface if said authentication
`information is valid.
`
`51.
`
`Claim 17 of the ’002 Patent recites:
`
`17. A computer-readable medium having stored thereon, computer-
`executable instructions that, responsive to execution by a computing
`device, cause the computing device to perform operations comprising:
`
`disabling a scan interface of a system comprising a secure processor
`and a software layer, wherein said software layer is authorized to
`access trusted resources in said secure processor;
`
`receiving authentication information at the software layer, wherein
`said authentication information if valid provides access to said
`scan interface;
`
`verifying whether said authentication information is valid using said
`software layer; and
`
`allowing access to said scan interface if said authentication
`information is valid.
`
`52.
`
`By way of example, MTI’s SAM L11 family of microcontroller chips utilize
`
`TrustZone technology to provide access control for debug functionality. The “’002 Accused
`
`Chips” include at least each of the aforementioned chips as well as any other MTI chips that
`
`provide access control for debug functionality in a substantially similar manner.
`
`53. MTI has directly infringed and continues to directly infringe one or more claims,
`
`including at least claim 17, of the ’002 Patent in violation of 35 U.S.C. § 271(a) by, without
`
`authority, making, offering to sell, or selling in the United States or importing into the United
`
`
`
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`
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`States the ’002 Accused Chips. In addition, on information and belief, MTI has directly infringed
`
`and continues to directly infringe one or more claims, including at least claim 1, of the ’002
`
`Patent in violation of 35 U.S.C. § 271(a) by, without authority, using in the United States the
`
`claimed method for accessing the scan interface on the ’002 Accused Chips, including for
`
`purposes of developing, debugging, profiling, aiding the manufacturing process, testing, or
`
`diagnosing defects of such chips.
`
`54.
`
`For example,
`
`the ’002 Accused Chips
`
`include an “Arm Cortex-M23”
`
`microprocessor.10 Arm is a technology provider that licenses processor and system-on-chip
`
`designs to chip providers such as MTI.
`
`55.
`
`The ’002 Accused Chips include “Arm TrustZone technology” providing for
`
`“integrated hardware security” including “secure debug” functionality, resulting in a secure
`
`processor.11 This debug functionality is provided across a “Serial Wire Debug (SWD)” scan
`
`interface.12
`
`56.
`
`The ’002 Accused Chips include a computer-readable memory coupled to the
`
`processor in the form of an internal ROM containing program instructions including for “Secure
`
`Boot.”13
`
`57.
`
`According to MTI, “TrustZone for an ARMv8-M device is based on a specific
`
`hardware that is implemented in the Cortex-M23 core, which is combined with a dedicated
`
`secure instructions set. It enables creating multiple software security domains that restricts access
`
`
`10 Microchip SAM L10/L11 Family Datasheet, DS60001513F, at 1, 53 (2020),
`https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-L10L11-Family-DataSheet-
`DS60001513F.pdf.
`11 https://www.microchip.com/design-centers/32-bit/sam-32-bit-mcus/sam-l-mcus/sam-l10-and-
`l11-microcontroller-family
`12 DS60001513F, supra note 10, at 3.
`13 Id. at 17.
`
`
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`to selected memory, peripherals, and I/O to trusted software without compromising the system
`
`performances.”14 The secure instructions including those in secure boot ROM are a software
`
`layer authorized to access trusted resources in the processor.
`
`58.
`
`According to MTI, the ’002 Accused Chips provide several “debug access levels
`
`(DAL), which restrict programming and debug access to Secure and Non-Secure resources in the
`
`system.” In DAL0, which is the lowest level of access, “No access is authorized except with a
`
`debugger using the Boot ROM Interactive mode.” In DAL1, “Access is limited to the Non-
`
`Secure memory regions. Secure memory region accesses are forbidden.” DAL2 provides “Debug
`
`access with no restrictions in terms of memory and peripheral accesses.”15
`
`59.
`
`According to MTI, “For security reasons, while the Boot ROM is executing, no
`
`debug is possible except when entering a specific Boot ROM mode called CPU Park mode.”16
`
`As a result, the scan interface is initially disabled.
`
`60.
`
`Accessing higher DAL levels requires submitting authentication information in
`
`the form of a secret “ChipErase” key to the trusted software layer. According to MTI, “The chip
`
`erase commands allow to erase memories of the device and provide secure transitions between
`
`the different Debug Access Levels.” In particular, as reflected in the MTI figure below depicting
`
`“SAM L11 Debug Access Levels Transitions,” the “CEKEY2” key enables a transition to
`
`DAL2.17 According to MTI, “The various chip erase operations are managed by the boot ROM
`
`
`14 Microchip SAM L11 Security Reference Guide, AN5365, DS70005365B, at 3 (2019),
`http://ww1.microchip.com/downloads/en/Appnotes/SAML11-Security-Reference-Guide-
`DS70005365B.pdf.
`15 AN5365, supra note 14, at 13.
`16 DS60001513F, supra note 10, at 67.
`17 Id. at 75.
`
`
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`code.”18 The trusted software layer verifies whether the CEKEY2 is correct and, if so, allows
`
`DAL2 access to the scan interface.
`
`I) Progr.:wn NVM rajon~
`Delivered p3r1S ~
`2)SondSDN.O corrm¥lCI (NVMCTRl.)
`
`I / - ~ ~~SOAI ' """"""d<NIIMCTAL)
`
`""''""""'
`
`__J /
`
`Chl,'el'~_S
`Wflh CEKtY 1 key d 9S =0
`
`.. ,., ··---·---~-.... _
`
`Chiifr.1::c _,\LL
`.ih('.(KEY21ct'(
`
`Figure 2
`
`1) Program Non Seo.ire N\IM reg,ons.
`2) Send SCW.O carnm:illd (NVMCTRL)
`
`--(
`
`
`
`61.
`
`In addition, MTI has indirectly infringed and continues to indirectly infringe the
`
`’002 Patent in violation of 35 U.S.C. § 271(b) by taking active steps to encourage and facilitate
`
`direct infringement by others, including OEMs, agent-subsidiaries, affiliates, partners, service
`
`providers, manufacturers, importers, resellers, customers, and/or end users, in this district and
`
`elsewhere in the United States, through the dissemination of the ’002 Accused Chips and the
`
`creation and dissemination of promotional and marketing materials, supporting materials,
`
`instructions, product manuals, and/or technical information relating to such products (including
`
`the materials previously cited) with knowledge and the specific intent that its efforts will result in
`
`the direct infringement of the ’002 Patent.
`
`62.
`
`For example, MTI took active steps to encourage end users to use the ’002
`
`Accused Chips in the United States in a manner it knows will directly infringe each element of
`
`one or more claims, including at least claim 1, of the ’002