United States Patent [19]
`Hwang
`
`I 1111111111111111 11111 lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`US005565761A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,565,761
`Oct. 15, 1996
`
`[54] SYNCHRONOUS SWITCHING CASCADE
`CONNECTED OFFLINE PFC-PWM
`COMBINATION POWER CONVERTER
`CONTROLLER
`
`[76]
`
`Inventor: Jeffrey H. Hwang, 20576 Manor Dr.,
`Saratoga, Calif. 95070
`
`[21] Appl. No.: 300,475
`
`[22] Filed:
`
`Sep. 2, 1994
`
`Int. Cl.6
`...................................................... G0SF 1/656
`[51]
`[52] U.S. CI . ............................................. 323/222; 323/282
`[58] Field of Search ..................................... 323/222, 223,
`323/224, 282, 284, 288; 363/21, 23, 25
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,731,574
`4,736,151
`5,278,490
`5,412,308
`5,457,622
`5,461,302
`
`3/1988 Melbert ................................... 323/282
`4/1988 Dishner ................................... 323/222
`1/1992 Smedley .................................. 323/282
`5/1995 Brown ..................................... 323/222
`10/1995 Arakawa ................................. 323/222
`10/1995 Garcia et al. .. ......................... 323/222
`
`Primary Examiner-Matthew V. Nguyen
`Attorney, Agent, or Firm-Haverstock & Associates
`
`[57]
`
`ABSTRACT
`
`A synchronous switching cascade connected power con(cid:173)
`verter includes a first power factor correction converter stage
`and a second DC to DC converter stage for generating an
`output voltage in response to an input voltage and current.
`The output voltage is controlled by a circuit which measures
`a level of current within the circuit, compares that level to
`a predetermined desired level, and develops a response
`elsewhere in the circuit. Leading edge modulation for the
`first stage and trailing edge modulation for the second stage
`is implemented to realize synchronous switching between
`the two power stages. A single reference clock signal is used
`to control both the power stages. The duty cycle of the first
`stage is varied according to the input voltage. The duty cycle
`of the second stage is ideally held constant at fifty percent
`but will vary as the input voltage to this stage varies. A de
`ok comparator is coupled to the first stage for comparing an
`output voltage to a threshold value and preventing the
`second stage from turning on if the output voltage of the first
`stage is below the threshold value. A transconductance
`amplifier is used to control the input current and the output
`voltage of the power stages. A circuit for capturing a portion
`of the voltage lost due to the parasitic capacitances of the
`switches is also included. This capturing stage is coupled to
`the switch to capture voltage discharged by the parasitic
`capacitance and use it to then charge the output capacitor of
`the converter stage.
`
`23 Claims, 12 Drawing Sheets
`
`120
`
`L1
`
`SW2
`
`SW3
`
`L2
`
`124
`
`VIN
`
`122
`
`C2
`
`RL
`
`PTI VOUT
`
`126
`
`SCV1
`
`SCV3
`
`150
`
`osc
`
`CLK
`
`154
`
`132
`
`s Q
`
`D
`CLKQ
`
`134
`
`DUTY
`LIMIT
`
`136
`
`Q
`
`R
`D
`
`CLKQ
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 1 of 21
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`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 1 of 12
`
`5,565,761
`
`10
`
`L1
`
`SW2 I2 I3
`
`14
`
`VIN
`
`12
`
`SW1
`
`RL
`
`VOUT
`
`16
`
`SCV1
`FIGURE 1 (Prior Art)
`
`20
`
`L1
`
`SW2
`
`SW3
`
`L2
`
`24
`
`__ , SW1
`
`SCV2
`C1
`
`VIN
`
`22
`
`RL
`
`VOUT
`
`26
`
`SCV1
`
`SCV3
`
`FIGURE 2 (Prior Art)
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 2 of 21
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`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 2 of 12
`
`5,565,761
`
`L1
`
`rr
`
`I3
`SW2 I2
`~ ~
`
`+
`
`-
`
`VIN
`DC
`
`SW1
`
`r--------------------- 7
`U3
`
`REF
`
`U4
`
`U2
`
`RAMP
`
`Q
`DOFF
`OSC 1-C.;;;;..;;L;;.;..K;__ ____ -4---0 CLK Q
`
`31
`
`L----------------------~
`
`FIGURE 3 (Prior Art)
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 3 of 21
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`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 3 of 12
`
`5,565,761
`
`FIGURE 4
`(Prior Art)
`
`VSW1
`
`~ ~ I
`
`I
`
`I
`I
`I
`
`RAMP
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`FIGURE 5
`(Prior Art)
`
`FIGURE 6
`(Prior Art)
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`CLK
`
`VEAO
`
`TIME
`
`...
`,,.. TIME
`
`TIME
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 4 of 21
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`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 4 of 12
`
`5,565,761
`
`+
`
`-
`
`-
`
`L1
`rr
`
`VIN
`DC
`
`SW2 I2 I]
`
`~ ~
`
`!I4
`
`C1
`
`RL
`
`SW1
`
`PTI
`
`U2
`
`REF
`
`U4
`
`---<1S Q
`RAMP
`D
`OSC CLK
`Q-
`1-----------t-----1>CLK
`
`OFF
`
`FIGURE 7 (Prior Art)
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 5 of 21
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`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 5 of 12
`
`5,565,761
`
`FIGURE 8
`(Prior Art)
`
`VSW1
`
`~ ~
`
`I
`I
`
`I
`
`CLK
`
`FIGURE 9
`(Prior Art)
`
`FIGURE 10
`(Prior Art)
`
`RAMP
`
`I
`I
`I
`I
`
`I
`I
`I
`I
`
`I
`I
`I
`I
`
`I
`I
`I
`I
`
`I
`I
`I
`I
`
`I
`I
`I
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`VEAO
`
`TIME
`
`...
`,,... TIME
`
`TIME
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 6 of 21
`
`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 6 of 12
`
`5,565,761
`
`20
`
`L1
`
`SW2
`
`SW3
`
`L2
`
`24
`
`VIN
`
`22
`
`C1
`
`RL
`
`VOUT
`
`26
`
`SCV1
`
`SCV3
`
`FIGURE 11
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 7 of 21
`
`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 7 of 12
`
`5,565,761
`
`120
`
`L 1
`
`SW2
`
`SW3
`
`L2
`
`124
`
`VIN
`
`122
`
`PTI VOUT
`
`126
`
`SCV1
`
`SCV3
`
`150
`
`osc
`
`CLK
`
`132
`
`Q
`
`134
`
`LIMIT
`
`136
`
`R
`D
`
`Q
`
`CLKQ
`
`FIGURE 12
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 8 of 21
`
`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 8 of 12
`
`5,565,761
`
`ACIN
`
`F1
`C11uF
`
`C3
`0.1uF
`U) a:
`U)
`.....
`N
`ci
`
`R3
`100k
`LL
`:::, .----.
`ci
`C\I
`0
`
`Lt)
`
`R4
`
`17.5k
`
`RNULL2
`
`FIGURE 13A
`
`R2739k
`T1
`D4 1N4148
`
`N
`
`<0
`
`C o "" U) z .....
`
`T"' a:
`::E
`.....
`
`....---41-------------- R30/P13
`00
`....
`'I:!'
`'I:!' z
`
`C11
`1uF
`
`T"'
`
`C4
`+ ';
`Lt) 0
`0.01uF o~
`R82.37k
`
`....,
`a:
`'----1--------➔ R8/P15
`,___ ________________ Rl/P2
`,___ ___________ ____ __ R4/P4
`
`'--------------------1-------- R5/P3
`C251uF
`
`R18
`3k
`
`Q3
`
`0
`.,..
`i.n
`a:
`=>
`It)
`::E C
`
`+
`C21
`
`R24
`
`C22~+-_.
`I
`R23
`
`R22
`
`R25 ~----< IV RET
`
`-=-
`~-------➔ U2/R10
`~ - - - - - - - - - - - - - - - R19/P8
`'---------------------➔ R14/P11
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 9 of 21
`
`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 9 of 12
`
`5,565,761
`
`R30/P13
`R21/P12
`
`R5/P3
`
`RNULL1
`R8/P15
`
`Rl/P2
`
`R4/P4
`
`r; R11
`
`9
`ISENSE ' - - - -
`3
`
`IAC
`
`VRMS
`
`l(cid:173)o
`
`ILIM:
`
`R19/P8>---1-+------18f--+----+
`C\I
`1.25V
`C.
`:iii
`<(
`CC
`
`I
`I
`I
`I
`
`I
`
`V
`U2/R10>---t-----;
`IS
`
`C6
`
`R12
`
`C7
`
`IEAO
`1 ----------------------1
`LEADING EDGE MODULATION PFC
`FB
`+ U19
`-if
`2.7V
`
`1
`1
`
`2.575V
`
`0
`0 >
`
`D9
`
`ML4824
`
`DCOK-
`I
`I
`_ ~ - - - - - - - - - -~
`I
`1 __ - _______________________________ ..J
`R14 /P l l> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
`FIGURE 138
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 10 of 21
`
`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 10 of 12
`
`5,565,761
`
`140
`
`L1
`
`152
`
`SW1
`
`142
`
`144
`
`146
`
`1
`
`-
`
`-
`
`- 154 -
`
`- -L2 -
`
`-
`
`7
`I
`
`156
`158
`
`I
`I
`150 I
`I
`
`I
`L ____________ _J
`
`FIGURE 14
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 11 of 21
`
`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 11 of 12
`
`5,565,761
`
`ML4824 IOTA GM
`
`CURSOR ( 1.7500V
`MARKER ( 2.5000V
`
`• 255E-06.
`65.7E-06.
`
`)
`)
`
`250.0
`E-06
`
`25.00
`/div
`
`.0000'---------------....i.--....i.----------------
`.0000
`5.000
`
`VIN
`
`.5000/div
`
`(V)
`
`FIGURE 15
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 12 of 21
`
`

`

`U.S. Patent
`
`Oct. 15, 1996
`
`Sheet 12 of 12
`
`5,565,761
`
`ML4824 IOTA GM
`
`MARKER {
`
`• OOOOV
`
`181E-06.
`
`250.0
`E-06
`
`25.00
`/div
`
`.oooo---------------------------------
`
`-500.0
`
`VJ:N
`
`0
`100.0/div
`
`{mV)
`
`500.0
`
`FIGURE 16
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 13 of 21
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`

`

`5,565,761
`
`1
`SYNCHRONOUS SWITCHING CASCADE
`CONNECTED OFFLINE PFC-PWM
`COMBINATION POWER CONVERTER
`CONTROLLER
`
`FIELD OF THE INVENTION
`
`This invention generally relates to the field of cascade
`power converters. More particularly, the present invention
`relates to the field of two stage, AC to DC power converters
`which include a power factor correction converter.
`
`BACKGROUND OF THE INVENTION
`
`Switching mode power converters of the prior art, as
`illustrated in FIG. 1, produce large harmonic current, gen(cid:173)
`erating interference in communication circuits and may also
`produce excessive neutral current, hot spots in the trans(cid:173)
`former, resonance, inaccuracies in the instrumentation, mis(cid:173)
`operation of relays and voltage distortion in the power
`distribution system. With the increase of such nonlinear 20
`· 1oads connected to the power grid, efficient techniques for
`power factor correction (PFC) are increasingly sought after
`to deliver more power to the load at a constant level.
`For switching mode power converters the output voltage
`is controlled by an electronic circuit which measures a level
`of electric current within the circuit, compares that measured
`level to a predetermined desired level, and develops a
`response to that measurement elsewhere in the circuit in
`order to more accurately achieve the desired level. A boost
`converter power stage of the prior art is illustrated in FIG.
`L The input voltage VIN is coupled to the input terminals 10
`and 12. The input terminal 10 is coupled to a first terminal
`of the inductor LL A second terminal of the inductor Ll is
`coupled to the positive terminals of the switches SWl and 35
`SW2. The switch control voltage SCVl is coupled to control
`the switch SWl and to the input of the inverter 18. The
`output of the inverter 18 is coupled as the switch control
`voltage SCV2 for controlling the switch SW2. The capacitor
`Cl is coupled between the negative terminals of the switches 40
`SWl and SW2. The load RL is coupled across the capacitor
`Cl and the output voltage VOUT can be measured across the
`output terminals 14 and 16. This power stage is designed so
`that when the switch SWl is closed, the switch SW2 is open
`and when the switch SWl is open, the switch SW2 is closed. 45
`The boost converter of FIG. 1 converts the input voltage
`VIN to a desired output voltage VOUT. The voltage VIN is
`applied to a pair of terminals 10 and 12 of the boost power
`stage. The input voltage VIN is turned on and turned off
`relative to the boost power stage by alternately closing and
`opening the switches SWl and SW2. The switches SWl and
`SW2 are controlled by the switch control voltage signals
`SCVl and SCV2. The circuit is designed so that when the
`switch SWl is open, the switch SW2 is closed and when the
`switch SWl is closed, the switch SW2 is open. The input 55
`voltage VIN is isolated from the load RL by the inductor Ll
`so that the switching noise is not readily coupled to the input
`line.
`The output voltage VOUT is established by integrating
`the inductor current in the LC filter network. This integrated 60
`current is supplied to the load circuit as the converted output
`voltage VOUT. In order to establish the proper output
`voltage from a given input voltage, the input voltage VIN is
`switched in and out of the circuit by the switches SWl and
`SW2. The resulting oscillating signal is integrated in the LC 65
`network to form the desired output voltage VOUT. If the
`input voltage VIN changes or varies over time, the fre-
`
`15
`
`25
`
`2
`quency at which the switches SWl and SW2 are opened and
`closed can also be varied in order to maintain the desired
`output voltage VOUT.
`When the switch SWl is open and the switch SW2 is
`5 closed the input voltage VIN is connected to the remainder
`of the circuitry and the inductor current IL rises linearly until
`it reaches the peak current level. When the inductor current
`IL reaches the peak current level, the switch SWl is closed,
`the switch SW2 is open and the inductor current IL
`10 decreases at a linear rate. The linear rise and fall rates for the
`inductor current IL need not be the same. Once the current
`has fallen to the minimum level, the circuit is "turned on",
`by opening the switch SWl and closing the switch SW2, and
`the cycle is then repeated. The output voltage VOUT is equal
`to the average of the inductor current IL multiplied by the
`load resistance RL. The inductor current IL is integrated by
`the LC network forming the output voltage VOlJT.
`The boost converter, as illustrated in FIG. 1, is typically
`used in power factor correction circuits of the prior art
`because the input current flows through an inductor and is
`therefore relatively smooth and easy to control. However,
`since the input instantaneous power does not equal the
`output instantaneous power, the intermediate stage consist(cid:173)
`ing of the capacitor Cl must be installed to store the excess
`instantaneous power temporarily. Because the system typi(cid:173)
`cally must interface with a universal input such as an oflline
`AC source, the capacitor Cl must have the ability to sustain
`a very high output voltage of approximately 380 VDC. Such
`capacitors are typically very expensive. Isolation of the
`30 boost converter is difficult to implement because such a high
`PFC output voltage is required. In order to implement
`isolation of the boost converter, a second stage comprising
`a step down power converter with isolation is required.
`The cascade connection of power stages is a very effective
`and powerful tool in the design of state-of-the-art high
`frequency switching mode power converters. Power factor
`corrected power supplies offer improved performance when
`compared to ordinary off-line switching power supplies.
`However, the system stability of such power factor corrected
`power supplies needs special care.
`Systems which contain a right hand zero are referred to as
`non-minimum phase systems. It is difficult to compensate
`for a cascade power stages system, because of the right hand
`zero and the two close poles which are caused by a momen(cid:173)
`tary no load. For example in the single boost power con-
`verter stage illustrated in FIG. 1, the load of this stage RL is
`continuously connected to the output stage. Because the load
`RL is also part of the output filter, it is very important to the
`50 switching power converter. Reduction of the load will cause
`the poles due to the inductor and the capacitor to become
`closer and thus reduce the phase margin.
`A cascade connection of two power stages is illustrated in
`FIG. 2. The input voltage VIN is coupled to the terminals 20
`and 22. The terminal 20 is coupled to a first terminal of the
`inductor LL The second terminal of the inductor Ll is
`coupled to the positive terminals of the switches SWl and
`SW2. The switch control voltage SCVl is coupled to control
`the switch SWl and to the input of the inverter 28. The
`output of the inverter 28 is coupled as the switch control
`voltage SCV2 for controlling the switch SW2. The capacitor
`Cl is coupled between the negative terminals of the switches
`SWl and SW2. The positive terminal of the switch SW3 is
`coupled to the capacitor Cl and the negative terminal of the
`switch SW2. The negative terminal of the switch SW3 is
`coupled to the positive terminal of the switch SW4 and to a
`first terminal of the inductor L2. The capacitor C2 is coupled
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 14 of 21
`
`

`

`5,565,761
`
`15
`
`3
`between a second terminal of the inductor L2 and the
`negative terminal of the switch SW4. The switch control
`voltage SCV3 is coupled to control the switch SW3 and to
`the input of the inverter 30. The output of the inverter 30 is
`coupled as the switch control voltage SCV 4 for controlling
`the switch SW4. The load RL is coupled across the capacitor
`C2 and the output voltage VOUT can be measured across the
`terminals 24 and 26.
`In the cascade power stage, as illustrated in FIG. 2, the
`load RL could be momentary and not constant, causing
`periods when there is no load. Without the load connected to
`the power stage, the system will oscillate and cannot main(cid:173)
`tain a constant output voltage VOUT. Many systems of the
`prior art attempt to reduce the no load period by speeding up
`the loop response for the second stage. A second, faster
`clock, is typically used to speed up the response of the
`second stage, causing the system to become more compli(cid:173)
`cated.
`A trailing edge modulation control scheme is illustrated in
`FIG. 3. The converter stage of this trailing edge scheme is
`the same as the converter stage of FIG. 1 with the addition
`of the switch control circuitry 31. A reference voltage REF
`is coupled to the positive input of the error amplifier U3. The
`negative or inverting input of the error amplifier U3 is
`coupled to the potentiometer PTl. The output VEAO of the
`error amplifier is coupled as the positive input of the
`comparator Ul. The negative input of the comparator Ul is
`coupled to the ramp output of the oscillator U4. The output
`of the comparator Ul is coupled as the reset input R of the
`flip flop U2. The input D of the flip flop U2 is coupled to the
`output Q. The clock input CLK of the flip flop U2 is coupled
`to the clock output of the oscillator U4. The output Q of the
`flip flop U2 is coupled to control the operation of the switch
`SWl.
`Pulse width modulation (PWM) is a technique used to
`maintain a constant output voltage VOUT when the input
`voltage does not remain constant and varies over time. By
`changing the frequency at which the switches are opened
`and closed, as the input voltage changes, the output voltage
`VOUT can be maintained at a constant level as desired. The
`inductor current IL is stored as a voltage level on the plates
`of the capacitor Cl. Because of its parallel connection to the
`output of the circuit, the voltage across the capacitor Cl is
`equivalent to the output voltage VOUT and the voltage
`across the potentiometer PTl. A fraction of that voltage is
`measured from the potentiometer PTl forming the voltage
`VEA which is input into the negative terminal of the error
`amplifier and is compared to the reference voltage REF. This
`comparison determines how close the actual output voltage
`VOUT is to the desired output voltage.
`Conventional pulse width modulation techniques use the
`trailing edge of the clock signal, so that the switch will tum
`on right after the trailing edge of the system clock. FIGS. 4,
`5 and 6 show corresponding voltage waveforms with respect
`to time of different voltage levels at different points within 55
`the switch control circuitry 31. The time axis for the FIGS.
`4, 5 and 6 has been drawn to correspond in all three figures.
`FIG. 4 illustrates the voltage levels with respect to time of
`the error amplifier output VEAO and the modulating ramp
`output of the oscillator U4. FIG. 5 illustrates the voltage 60
`level of the switch SWl with respect to time. The switch
`SWl is at a high voltage level when it is "on" or closed. The
`switch SWl is at a low voltage level when it is "off" or open.
`FIG. 6 illustrates the clock impulses with respect to time of
`the clock output of the oscillator U4.
`The switch SWl will tum on after the trailing edge of the
`system clock. Once the switch SWl is on, the modulator
`
`4
`then compares the error amplifier output voltage and the
`modulating ramp; when the modulating ramp reaches the
`error amplifier output voltage, the switch will be turned off.
`When the switch is on, the inductor current will ramp up.
`5 The effective duty cycle of the trailing edge modulation is
`determined during the on time of the switch. FIG. 3 illus(cid:173)
`trates a typical trailing edge control scheme using a single
`boost power converter stage. As the input voltage VIN varies
`over time, the duty cycle or time that the switch SWl is on
`will vary in order to maintain a constant output voltage
`10 VOUT.
`A leading edge modulation control scheme is illustrated in
`FIG. 7. The difference between the circuit of FIG. 3 and the
`circuit of FIG. 7 is that the reference voltage in the circuit
`of FIG. 7 is coupled to the negative input of the error
`amplifier U3 and the voltage VEA from the potentiometer
`PTl is coupled to the positive input of the error amplifier U3.
`FIGS. 8, 9 and 10 show corresponding voltage waveforms
`with respect to time. FIG. 8 illustrates the voltage levels with
`20 respect to time of the error amplifier output VEAO and the
`ramp output of the oscillator U4 for the leading edge
`modulation circuit of FIG. 7. FIG. 9 illustrates the voltage
`level of the switch SWl with respect to time. The switch
`SWl is at a high voltage level when it is "on" or closed. The
`25 switch SWl is at a low voltage level when it is "off" or open.
`FIG. 10 illustrates the clock impulses with respect to time.
`In the case of leading edge modulation, the switch SWl
`is turned off after the leading edge of the system clock; when
`the modulating ramp reaches the level of the error amplifier
`30 output voltage VEAO, the switch will be turned on. The
`effective duty cycle of the leading edge modulation is
`determined during the off time of the switch. FIG. 7 shows
`a typical leading edge control scheme using a single boost
`power converter stage. While the voltage waveforms for the
`35 switch SWl shown in FIGS. 5 and 9 show a constant duty
`cycle for the switch SWl, as the input voltage VIN varies
`over time, the time that the switch SWl is on or closed, will
`vary in order to maintain a constant output voltage VOUT
`level.
`Ripple voltage is a quantity used to measure the amount
`of AC voltage introduced into the DC output voltage. If the
`boost-buck cascade power converter as illustrated in FIG. 2
`is used as the offline PFC-PWM power converter, the ripple
`voltage of the PFC output stage can be separated into two
`portions. The first portion is due to the voltage drop across
`the ESR which corresponds to the capacitor Cl and C2. The
`second portion of the ripple voltage is due to the change in
`voltage with respect to time across the capacitor Cl. Prior art
`schemes control the switches SWl and SW3 with two
`50 separate clock signals, so that the switch SWl and the switch
`SW3 are opened and closed at different times. If both
`converters are in the continuous conduction mode (CCM)
`and the conventional trailing edge modulation scheme with
`two different clocks controlling the switches SWl and SW3
`is used, the ripple voltage is
`
`40
`
`45
`
`I2max
`Total Ripple Voltage =l2maxx ESR + 0.433 X Cl xfsw
`
`(1)
`
`Where, the maximum current lzmax through a closed switch
`SW2 is equal to
`
`Avg. Input Powerx TI
`efficiency x Vin rms
`When the input phase is equal to 60 degrees, the change in
`65 voltage dV across the capacitor Cl reaches a maximum if
`the second portion of the ripple voltage which corresponds
`to the change in voltage across the capacitor Cl is dominant.
`
`(2)
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 15 of 21
`
`

`

`5,565,761
`
`5
`Each of the switches used has an associated parasitic
`capacitance which causes a loss of the power transferred to
`the output circuit. The parasitic capacitance of the switch
`builds up a stored voltage when the switch is open. This
`voltage is then discharged when the switch is closed, causing
`a loss of the power that was stored in the parasitic capaci(cid:173)
`tance of the switch.
`What is needed is a synchronous switching method for a
`cascade connected power converter which utilizes a single
`clock reference signal and reduces the ripple voltage in order 10
`to facilitate more efficient power usage and lower harmonic
`content in the line current. What is further needed is a
`method for capturing a portion of the voltage lost due to the
`parasitic capacitances of the switches.
`
`5
`
`SUMMARY OF THE INVENTION
`
`6
`FIG. 8 illustrates the voltage levels with respect to time of
`the error amplifier output and the ramp output of the
`oscillator for the leading edge modulation circuit of FIG. 7.
`FIG. 9 illustrates the voltage level of the switch SWl with
`respect to time.
`FIG. 10 illustrates the clock impulses with respect to time
`of the clock output of the oscillator.
`FIG. 11 illustrates a synchronous switching cascade
`power converter of the present invention.
`FIG. 12 illustrates a schematic of a synchronous switch(cid:173)
`ing two-stage cascade power converter of the present inven(cid:173)
`tion including switch control circuitry.
`FIG. 13 illustrates a detailed schematic of a synchronous
`15 switching two-stage cascade power converter of the present
`invention including switch control circuitry.
`FIG. 14 illustrates a schematic including a capturing
`circuit for capturing a portion of the voltage lost across the
`parasitic capacitance of a switch.
`FIG. 15 illustrates the transconductance characteristics for
`the voltage transconductance amplifier Ul.
`FIG. 16 illustrates the transconductance characteristics for
`the current transconductance amplifier U2.
`
`A synchronous switching two-stage cascade connected
`power converter includes a first power factor correction
`boost converter stage and a second DC to DC converter 20
`stage for generating an output voltage in response to an input
`voltage and current. The output voltage is controlled by an
`electronic circuit which measures a level of electric current
`within the circuit, compares that measured level to a prede(cid:173)
`termined desired level, and develops a response to that 25
`measurement elsewhere in the circuit. Leading edge modu(cid:173)
`lation for the first power factor correction boost converter
`stage and trailing edge modulation for the second DC to DC
`converter stage is implemented to realize synchronous
`switching between the two power stages. A single reference 30
`clock signal is used to control both the first and the second
`converter stages. The duty cycle of the first power stage is
`varied according to the input voltage in order to maintain a
`constant output voltage. The duty cycle of the second power
`stage is ideally held constant at fifty percent but will vary as
`the input voltage to this power stage varies. A de ok
`comparator is coupled to the first stage for comparing an
`output voltage of the first stage to a threshold value and
`preventing the second stage from turning on if the ·output
`voltage of the first stage is below the threshold value. A
`transconductance amplifier is used to control the input
`current and the output voltage of the power stages.
`A circuit for capturing a portion of the voltage lost due to
`the parasitic capacitances of the switches is also included.
`This capturing stage is coupled to the switch to capture the
`voltage discharged by the parasitic capacitance and use this
`voltage to then charge the output capacitor of the converter
`stage.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`A cascade power converter of the present invention, as
`illustrated in FIG. 1, uses a synchronous switching scheme
`and controls the switches SWl and SW3 with a single
`system clock signal. The difference between the power
`converter of FIG. 11 and the power converter of FIG. 2 is
`that the switches SWl and SW3 are turned on or off at the
`same time in order to minimize the momentary no load
`35 period and reduce the ripple voltage delivered to the load
`RL.
`The ripple voltage for the cascade power converter of
`FIG. 11 is equal to
`40 Total Ripple Voltage =
`
`(3)
`
`hmax-13
`(fimax - /3) x ESR + 0.433 x Cl x Jsw
`
`45 Therefore the total ripple voltage is reduced from the
`cascade power converter of FIG. 2, because everywhere the
`current l 2max was used in the equation (1), that value is
`replaced by the value (l2max-l3) in the equation (3).
`A schematic of a synchronous switching, two-stage cas-
`50 cade connected, offiine PFC-PWM power converter,
`designed according to the present invention, is illustrated in
`FIG. 12. The first stage of the power converter illustrated in
`FIG. 12 uses a leading edge modulation control scheme
`which controllably varies the duty cycle of the switches
`55 SWl and SW2 in order to maintain a constant output voltage
`VOUT. The second stage of the power converter uses a
`trailing edge modulation scheme in which the duty cycle of
`the switches SW3 and SW4 is ideally held constant, but will
`vary as necessary if the input voltage to the second stage, as
`60 measured across the capacitor Cl, varies.
`The function of the power factor correction first stage is
`to ensure that the current follows the voltage in time and
`amplitude proportionally. This means that for a steady-state
`constant output power condition, the amplitude of the cur-
`rent waveform will follow the amplitude of the voltage
`waveform in the same proportion at any instant in time.
`Therefore, when the voltage amplitude is at its maximum,
`
`65
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 illustrates a schematic diagram for a switching
`mode boost power converter of the prior art.
`FIG. 2 illustrates a schematic diagram of a cascade
`connection of two power stages.
`FIG. 3 illustrates a trailing edge modulation control
`scheme of the prior art.
`FIG. 4 illustrates the voltage levels with respect to time of
`the error amplifier output and the ramp output of the
`oscillator for the trailing edge modulation circuit of FIG. 3.
`FIG. 5 illustrates the voltage level of the switch SWl with
`respect to time.
`FIG. 6 illustrates the clock impulses with respect to time
`of the clock output of the oscillator.
`FIG. 7 illustrates a leading edge modulation control
`scheme of the prior art.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1043
`Page 16 of 21
`
`

`

`5,565,761
`
`25
`
`7
`the current amplitude will also be at its maximum. Corre(cid:173)
`spondingly, when the voltage amplitude is at half of its
`maximum value, the current amplitude will also be at half of
`its maximum value. This proportional relationship results in
`a sinusoidal current waveform which is in phase with the
`incoming sinusoidal voltage waveform.
`The voltage control loop for this stage is forced to have a
`slow response in order to allow the current to follow the
`voltage because the first stage is concerned with current
`processing, and the frequency of the current is related to the 10
`line frequency. This-slow voltage loop response makes
`necessary the addition of the second power stage for faster
`and more accurate voltage processing.
`Two transconductance amplifiers Ul and U2, as illus(cid:173)
`trated in the circuit of FIG. 13, are utilized within this
`control loop. The transconductance amplifiers Ul and U2
`exhibit low transconductance when the inputs of the ampli(cid:173)
`fiers are balanced. When these inputs become unbalanced
`the transconductance will increase. These transconductance
`amplifiers Ul and U2 do not require local feedback com(cid:173)
`pensation. During transient operation, due to the transcon(cid:173)
`ductance amplifiers Ul and U2, the response of the voltage
`control loop will be forced to speed up. The transconduc(cid:173)
`tance characteristics for the transconductance amplifier Ul
`are illustrated in FIG. 15. The transconductance character(cid:173)
`istics for the transconductance amplifier U2 are illustrated in
`FIG. 16.
`In the power converter of FIG. 12, the input voltage VIN
`is coupled to the input terminals 120 and 122. The input
`terminal 120 is coupled to a first terminal of the inductor LI. 30
`The second terminal of the inductor LI is coupled to the
`positive terminals of the switches SWl and SW2. The
`negative terminal of the switch SWl is coupled to the input
`terminal 122. The negative terminal of the switch SW2 is
`coupled to a first terminal of the capacitor Cl and the 35
`positive terminal of the switch SW3. A second terminal of
`the capacitor Cl is coupled to the input terminal 122. The
`negative terminal of the switch SW3 is coupled to the
`positive terminal of the switch SW4 and a first terminal of
`the inductor L2. The negative terminal of the switch SW4 is 40
`coupled to the input terminal 122. The second terminal of the
`inductor L2 is coupled to a first terminal of the capacitor C2,
`a first terminal of the load resistance RL, a first terminal of
`the potentiometer PTl and the output terminal 124. The
`second terminal of the capacitor C2, the second terminal of 45
`the resistor RL, the second terminal of the potentiometer
`PTl and the output terminal 126 are all coupled to the input
`terminal 122. The output voltage VOUT is measured across
`the output terminals 124 and 126.
`The output voltage VEA from the potentiometer PTl is 50
`coupled to the positive input of the error amplifier 128. A
`reference voltage REF is coupled as the negative or invert(cid:173)
`ing input of the error amplifier 128. The output VEAO from
`the error amplifier 128 is coupled as the positive input to the
`comparator 130. The ramp output of the oscillator 150 is 55
`coupled as the negative input to the comparator 130. The
`