United States Patent (19)
`Bittner
`
`(54)
`
`VOLTAGE REGULATOR THAT OPERATES
`NETHER PWM OR PFM MODE
`
`(75)
`
`73)
`
`21
`22
`(51)
`(52)
`(58)
`
`56)
`
`Inventor: Harry J. Bittner, Santa Clara, Calif.
`Assignee: Micrel, Inc., San Jose, Calif.
`
`Appl. No. 313,489
`Filed:
`Sep. 27, 1994
`Int. Cl. ................. GOSF 1/40
`U.S. Cl. ........................... 323/272; 323/287; 323/224
`Field of Search .................................. 363/21, 41, 23;
`323/268, 284, 272, 271, 224, 285, 286,
`287
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`4,047,083 9/1977 Plunkett .................................... 363f4.
`4,400,767 8/1983 Fenter ....................................... 363/21
`4,456.872 6/1984 Froeschle ...
`... 323,286
`4,626,763 12/1986 Edwards .................................... 363f41
`5,481,178
`1/1996 Wilcox et al. .......................... 323/287
`
`III IIII
`US005568044A
`11
`Patent Number:
`5,568,044
`(45) Date of Patent:
`Oct. 22, 1996
`
`Primary Examiner-Peter S. Wong
`Assistant Examiner-Shawn Riley
`Attorney, Agent, or Firm–Skjerven, Morrill, MacPherson,
`Franklin & Friel; William L. Paradice, III
`(57)
`ABSTRACT
`A switching voltage regulator achieves high efficiency by
`automatically switching between a pulse frequency modu
`lation (PFM) mode and a pulse-width modulation (PWM)
`mode. Switching between the modes of voltage regulation is
`accomplished by monitoring the output voltage and the
`output current, wherein the regulator operates in PFM mode
`at small output currents and in PWM mode at moderate to
`large output currents. PFM mode maintains a constant
`output voltage by forcing the switching device to skip cycles
`when the output voltage exceeds its nominal value. In PWM
`mode, a PWM signal having a variable duty cycle controls
`the switching device. A constant output voltage is main
`tained by feedback circuitry which alters the duty cycle of
`the PWM signal according to fluctuations in the output
`Voltage.
`
`6 Claims, 9 Drawing Sheets
`
`CONTROL
`CIRCUIT
`
`HIGH-SIDE
`SWITCH
`DRIVER
`
`CONTROL
`LOGIC
`
`PFM
`CONTROL
`CIRCUIT
`
`LOW-SIDE
`SWITCH
`DRIVER
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FEEDBACK
`
`OUTPUT
`WOLAGE
`SENSE
`CIRCUIT
`
`
`
`
`
`
`
`
`
`
`
`INDUCTOR
`CURRENT
`SENSE
`CIRCUIT
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 1 of 15
`
`

`

`U.S. Patent
`
`Oct. 22, 1996
`
`Sheet 1 of 9
`
`5,568,044
`
`100A o
`
`Z!
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`| [[]OH|0
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`TOHINOO
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`BOIS-MOT
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`TOHI NOO
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 2 of 15
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`

`

`U.S. Patent
`
`Oct. 22, 1996
`
`Sheet 2 of 9
`
`5,568,044
`
`LOGIC 1
`
`toN->-toFF
`
`LOGIC 0
`
`DT
`
`T
`
`FIG. 2A
`
`
`
`INDPK
`
`INDMIN
`
`O
`
`loUT = IND, PK- - -
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 3 of 15
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`

`

`U.S. Patent
`
`Oct. 22, 1996
`
`Sheet 3 of 9
`
`5,568,044
`
`IND
`
`
`
`LIM, PFM
`
`toN =
`
`LIM, PFML
`toFF
`WOUT + 04W
`
`LIM, PFML
`WIN-WOUT
`FIG. 3B
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 4 of 15
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`

`

`U.S. Patent
`
`Oct. 22, 1996
`
`Sheet 4 of 9
`
`5,568,044
`
`IND
`
`LIM, PFM
`
`FIG. 4A
`
`
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 5 of 15
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`

`

`U.S. Patent
`
`Oct. 22, 1996
`
`Sheet 5 of 9
`
`5,568,044
`
`roa -amala m.
`
`pm - Her - no mua as a m on m -as so a nun are
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`mim a
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`na
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`703
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`
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 6 of 15
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`

`

`U.S. Patent
`
`Oct. 22, 1996
`
`Sheet 6 of 9
`
`5,568,044
`
`100A
`
`
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 7 of 15
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`

`

`U.S. Patent
`
`
`
`5,568,044
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 8 of 15
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`

`

`U.S. Patent
`
`Oct. 22, 1996
`
`Sheet 8 of 9
`
`5,568,044
`
`
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 9 of 15
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`

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`MICROCHIP TECHNOLOGYINC. EXHIBIT 1034
`Page 10 of 15
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 10 of 15
`
`
`
`
`

`

`1.
`VOLTAGE REGULATOR THAT OPERATES
`NETHER PWM OR PFM MODE
`
`FIELD OF THE INVENTION
`The present invention relates to a voltage regulator. More
`specifically, the present invention relates to a high efficiency
`switching voltage regulator capable of operating in either
`one of two modes.
`
`10
`
`15
`
`20
`
`25
`
`BACKGROUND OF THE INVENTION
`Typically, voltage regulator circuits provide a constant
`output voltage of a predetermined value by monitoring the
`output and using feedback to keep the output constant. In a
`typical pulse width modulation (PWM) regulator circuit, a
`square wave is provided to the control terminal of the
`switching device to control its on and off states. Since
`increasing the on time of the switching device increases the
`output voltage, and vice versa, the output voltage may be
`controlled by manipulating the duty cycle of the square
`wave. This manipulation is accomplished by a control circuit
`which continually compares the output voltage to a refer
`ence voltage and adjusts the duty cycle of the square wave
`to maintain a constant output voltage.
`When the switching device is an MOS transistor, a
`significant amount of power is used to periodically charge
`the gates of the switching transistors. As the switching
`frequency increases, more power is lost. If the switching
`frequency is too low and the output current of the regulator
`is high, the output voltage of the regulator will be difficult to
`filter and convert to a DC voltage. Hence, the switching
`frequency must be kept relatively high. When the output
`current is low, the relatively high power loss due to con
`trolling the switching transistors results in a low efficiency
`35
`(output power/total power consumed) regulator.
`A continuing challenge in the design of voltage regulators
`is to reduce the power loss in the regulator circuit and
`thereby increase its efficiency. As such, the power dissipate
`in the control circuitry and switching circuitry of the PWM
`40
`regulator is of great concern.
`
`30
`
`45
`
`50
`
`SUMMARY OF THE INVENTION
`A switching voltage regulator is disclosed which is
`capable of operating in either a pulse frequency modulation
`(PFM) or pulse-width modulation (PWM) mode. The volt
`age regulator achieves high efficiency by automatically
`choosing the more efficient mode of regulation based on a
`continuous monitoring of the output current and the output
`voltage. The regulator operates in PFM mode when the
`regulator generates a small output current and switches to
`PWM operation when the regulator generates a moderate to
`large output current.
`A PFM mode of voltage regulation provides better effi
`55
`ciency at small output current levels than does a PWM
`mode. First, a PFM mode requires a fewer turn-on transi
`tions to maintain a constant output voltage than does a PWM
`mode of voltage regulation, thus resulting in a lower gate
`drive power dissipation for PFM mode. Second, since a
`PFM mode can be achieved with a much simpler control
`circuit having fewer components, the power dissipation in
`the control loop of a PFM mode is less than that of the
`control loop of a PWM mode.
`However, when the output current reaches a moderate
`level, a PFM mode of voltage regulation becomes imprac
`tical, since the maximum output current available from a
`
`60
`
`65
`
`5,568,044
`
`2
`PFM mode is generally much less than that available from
`a PWM mode. Thus, the present invention switches from a
`PFM mode of operation to a PWM mode of operation when
`the output current exceeds a predetermined level.
`A novel technique to determine when to operate in PWM
`or PFM mode is also described along with a novel PFM type
`voltage regulator.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a simplified block diagram of one embodimen
`of the present invention;
`FIG. 2A is a pictorial representation of the PWM control
`signal;
`FIG. 2B is a pictorial representation of the inductor
`current during PWM mode of voltage regulation;
`FIGS. 3A and 3B are pictorial representations of the
`output switch voltage and the inductor current during PFM
`mode of voltage regulation, respectively;
`FIGS. 4A-4C are pictorial representations of the inductor
`current, switching node voltage, and feedback voltage dur
`ing PFM mode of voltage regulation;
`FIG. 5 is a gate level schematic of one embodiment of the
`present invention;
`FIG. 6A shows the inductor current during both PFM
`mode and PWM mode; and
`FIGS. 6B-6E are timing diagrams showing the logic
`states of various components in the preferred embodiment.
`
`DETALED DESCRIPTION OF PREFERRED
`EMBODIMENT
`FIG. 1 is a simplified block diagram of an embodiment of
`the present invention. The voltage regulator of FIG. 1
`includes a feedback circuit 2, output voltage sensing circuit
`3, inductor current sensing circuit 4, control logic circuit 5,
`PWM control circuit 6, PFM control circuit 7, high-side
`switch driver 8, low-side switch driver 9, input terminal 10,
`high-side switch 11, switching node 12, low-side switch 13,
`schottky diode 14, inductor 15, capacitor 16, and output
`terminal 17.
`High-side switch 11 is preferably a P-channel MOSFET
`that has a first terminal connected to input terminal 10 and
`a second terminal connected to a terminal (switching node
`12) of inductor 15. The other terminal of inductor 15 is
`connected to output terminal 17.
`PWM control circuit 6, which includes a PWM signal
`generator, has an output terminal connected to a first input
`terminal of the high-side switch driver 8. The output termi
`nal of PWM control circuit 6 is also connected to the
`low-side switch driver 9. The output terminal of high-side
`switch driver 8 is connected to the control terminal of
`high-side switch 11 for supplying a voltage to turn switch 11
`on and off. Similarly, the output terminal of low-side switch
`driver 9 is connected to the control terminal of low-side
`switch 13, which is preferably an N-channel MOSFET, for
`supplying a voltage to turn switch 13 on and off. A schottky
`diode 14 is placed in parallel with low side switch 13 for
`shunting current to ground when current discharging from
`inductor 15 forces switching node 12 below approximately
`-0.4 volts.
`Feedback circuit 2 is coupled between output terminal 17
`and a first input terminal of PWM control circuit 6 for
`providing a feedback signal to PWM control circuit 6. This
`feedback signal is also provided to a first input terminal of
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 11 of 15
`
`

`

`5,568,044
`
`10
`
`20
`
`3
`PFM control circuit 7. PFM control circuit 7 has a second
`input terminal connected to switching node 12 for sensing
`the voltage V at switching node 12 and has an output
`terminal connected to a second input terminal of high-side
`switch driver 8 for controlling the on and off states of switch
`11.
`Output voltage sensing circuit 3 has an input terminal
`connected to output terminal 17 and an output terminal
`connected to a first input terminal of control logic circuit 5.
`Inductor current sensing circuit 4 has an input terminal
`connected to switching node 12 and an output terminal
`connected to a second input terminal of control logic circuit
`5 and to a third input terminal of PFM control circuit 7. An
`output terminal of control logic circuit 5 is connected to a
`second input terminal of PWM control circuit 6 and to a
`15
`fourth input terminal of PFM control circuit 7. Control logic
`circuit 5 enables/disables PWM control circuit 6 and PFM
`control circuit 7, thus determining in which mode the
`regulator will operate.
`Capacitor 16 is coupled between output terminal 17 and
`ground and acts to smooth the voltage at output terminal 17.
`The operation of the regulator is as follows. When an
`input voltage V to be regulated is supplied to the regulator
`circuit via input terminal 10, the voltage at output terminal
`17, V is initially below its nominal value, V.
`25
`Output voltage sensing circuit 3 detects the low value of V
`and sends a logic low signal to control logic circuit 5, which
`in turn enables PWM control circuit 6 and disables PFM
`control circuit 7. This state is denoted as PWM mode.
`Once in PWM mode, PWM control circuit 6 generates
`and transmits a fixed frequency square wave to the first
`inputs of high-side switch driver 8 and low-side switch
`driver 9 which, as mentioned previously, control the on and
`off states of switches 11 and 13. A high PWM signal turns
`high-side switch 11 on and turns low-side switch 13 off.
`Conversely, a low PWM signal turns high-side switch 11 off
`and turns low-side switch on. Operating switches 11 and 13
`in a push-pull fashion allows inductor 15 to store current
`from input terminal 10 when switch 11 is on and discharge
`current to output terminal 17 when switch 11 turns off.
`FIG. 2A illustrates a PWM square wave signal having a
`period of T. This PWM signal has an on-time (representing
`a logic high) from t=0 to t=DT and an off-time (representing
`a logic low) from t=DT to t-T, where the duty cycle of the
`signal is defined as the ratio of on-time to period T.
`A feedback voltage V corresponding to V is coupled
`to PWM control circuit 6 via feedback circuit 2. PWM
`control circuit 6 compares V, to a reference voltage V, and
`adjusts the duty cycle of the PWM square wave signal such
`that V, is equal to V,
`PWM control circuit 6 continues to control switches 11
`and 13 until the peak current flowing through inductor 15,
`denoted as Ina, drops below a predetermined level, In,
`When I
`drops below Int, inductor sensing circuit 4
`55
`sends a first enabling signal to control logic circuit 5. If
`output voltage sensing circuit 3 detects that V has not
`dropped below the regulated output voltage value, output
`voltage sensing circuit 3 sends a second enabling signal to
`control circuit 5, which then simultaneously disables PWM
`60
`control circuit 6 and enables PFM control circuit 7. When
`PWM control circuit 6 is disabled, low-side switch 13 is
`turned off and will remain off until PWM control circuit 6 is
`re-enabled. This state is known as PFM mode.
`FIG. 2B illustrates the inductor current during PWM
`65
`mode. The relationship between in and It is set by
`the following equation:
`
`(1)
`outnin-pkmin Alina/2
`It can be seen from the above equation that detecting Int
`accurately corresponds to detecting a constant value of
`I
`as long as the change in AI remains small relative
`to Iki. If AI changes substantially compared to Ikm,
`then pkmin must change in equal proportion to changes in
`AI in order for In to remain constant.
`Referring back to FIG. 1, when the regulator circuit
`begins operating in PFM mode, PFM control circuit 7 sends
`an activation signal to high-side switch driver 8, thus turning
`on switch 11. As mentioned earlier, switch 13 remains in an
`of state during PFM mode. Switch 11 will remain on until
`the inductor current I
`charges to an upper limit, Impr.
`When inductor current sensing circuit 4 detects that this
`limit has been reached, inductor current sensing circuit 4
`sends a de-activation signal to high-side switch driver 8,
`thereby turning switch 11 off. The inductor current I
`then
`discharges through schottky diode 14, causing the voltage at
`switching node 12, V, to swing from approximately V to
`-0.4V. When I
`reaches a zero level, V changes abruptly
`from-0.4V to V. PFM control circuit 7 detects this abrupt
`increase in V and turns on switch 11. Thus, when operating
`in PFM mode, the regulator circuit monitors the inductor
`current and the voltage at switching node 12 to determine
`when to turn on and off high-side switch 11. This PFM mode
`of voltage regulation is advantageous over others since an
`internal oscillator is not required.
`PFM control circuit 7 regulates V by controlling the on
`and off states of switch 11 and by preventing switch 11 from
`turning on when V exceeds its predetermined nominal
`value, V
`as follows. PFM control circuit 7 includes a
`comparator which compares feedback signal V, which is
`proportional to V, to reference voltage V, V, has an
`upper value V,
`and a lower value V. If V is less than
`V., PFM control circuit 7 will turn on switch 11 as
`described in the previous paragraph. If, however, V.
`exceeds V,ii (corresponding to V, exceeding Von),
`V, will fall to V, causing PFM control circuit 7 to turn
`switch 11 off. V. must then fall below V,
`before PFM
`control circuit 7 again turns on switch 11. This method of
`regulating the V by preventing switch 11 from turning on
`when V, exceeds its nominal value V
`is commonly
`referred to as "skipping cycles'. The PFM characteristic of
`the reference voltage V, prevents the regulator from spo
`radically skipping cycles.
`FIGS. 3A and 3B illustrate the waveforms of the voltage
`at switching node 12, V, and the inductor 15 current, I,
`where t
`is the on time of switch 11, t is the off time of
`switch 11, It is the time average value of I,
`and td=the
`delay time between I
`discharging to Zero and high-side
`switch 11 turning on. The above parameters are defined by
`the following equations:
`
`lindava F LLim, PFM(on top)
`indava - 20, it id)
`in F lum, PFM L.
`on - V - Vout
`
`Lim. PFM
`2
`
`-
`
`Eq. 2
`
`Eq. 3
`
`+ tal
`
`tfire luri PFM
`of W. 04y
`It can be seen from FIG. 3B that the average value of the
`inductor current waveform Ida is a function of only
`Inter, assuming that td is relatively small compared to the
`switching period. The values of to and t
`will vary as
`function of V, V, and the inductance L of inductor 15.
`
`Eq. 4
`
`30
`
`35
`
`40
`
`45
`
`50
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 12 of 15
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`10
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`15
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`20
`
`5
`When the regulator is supplying maximum current to
`output terminal 17 in PFM mode, switch 11 turns on at every
`switching cycle. Therefore, the maximum output current the
`regulator can supply when operating in PFM mode, Ida,
`will always be equal to IP/2 irrespective of the values
`of V, V, and L. This circuit is thus advantageous over
`previous methods of PFM mode regulation whose maximum
`output currents are dependent upon input voltage, output
`voltage, and inductance values.
`The regulator circuit monitors V to determine when to
`switch from PFM mode to PWM mode as follows. When the
`output current exceeds the maximum current the regulator is
`able to supply in PFM mode, i.e., when I
`exceeds I,
`PFM/2, Wu falls below Van Output voltage sensing
`circuit 3 detects this change in V and sends a logic low
`signal to control logic circuit 5. In response to this low
`signal, control logic circuit 5 sends a disable signal to PFM
`control circuit 7 and an enable signal to PWM control circuit
`6, thus switching the circuit from PFM mode to PWM mode.
`In order to make a clean transition between PFM and
`PWM modes of operation, the following conditions must be
`met: (1) the output sensing circuit 3 has a slow enough
`response time to ensure that brief negative transients at V
`do not trigger an erroneous change from PFM to PWM
`mode, (2) when the regulator changes from PFM to PWM
`25
`mode, the control logic circuit 5 forces the regulator to
`remain in PWM mode while the PWM control loop settles
`out (otherwise, during this period control logic circuit 5 may
`detect I,
`falling below I
`for brief transients, thereby
`causing the regulator to oscillate between PWM and PFM
`30
`operation), and (3) the PFM current limit (Ire) is
`greater than twice the value of the minimum output current
`required for PWM operation (I) (this condition ensures
`that the maximum output current for PFM mode (I/2)
`is greater than lumin. If Impri?2 is less than or equal to
`35
`In the regulator will oscillate between PFM and PWM
`modes).
`The PFM mode of operation described above varies when
`the difference between V and V is approximately 1 volt
`or less and the output current is less than Ier. FIGS. 4A,
`4B, and 4C illustrate the current of inductor 15 (I), the
`voltage at switching node 12 (Vsw), and the output of
`feedback circuit 2, respectively, when the regulator is oper
`ating in PFM mode in this particular situation. Since under
`these conditions I
`never exceeds IF, inductor cur
`rent sense circuit 4 does not cause PFM control circuit 7 to
`turn switch 11 off. Thus, as described previously, switch 11
`will remain on until V exceeds V, at which point PFM
`control circuit 7 causes switch 11 to turn off. Inductor 15
`then discharges through schottky diode 14, causing V to
`50
`swing from approximately V to -0.4V. When I
`reaches
`a zero level, V abruptly changes from -0.4V to V.
`However, switch 11 remains off until V falls below V.
`PFM control circuit 7 then causes switch 11 to turn on. I
`will then increase, but it will never exceed Ilier. There
`55
`fore, switch 11 remains on until V rises above V,
`Thus, the present invention achieves high efficiency over
`a wide range of output currents by automatically switching
`between PFM mode operation (when the output current is
`relatively small) and PWM mode operation (when the output
`current exceeds a predetermined level).
`FIG. 5 is a gate-level schematic of one embodiment of the
`present invention. When power is first applied to the regu
`lator circuit at V, V, is below its nominal value, V
`is of
`out,non
`This is detected by comparator 174 which sends a logic high
`signal to the gate of switch 178, turning on switch 178. The
`drain of switch 178 then swings low, forcing the output of
`
`45
`
`40
`
`60
`
`65
`
`5,568,044
`
`6
`SR latch 138 high which, in turn, enables the PWM con
`troller 140. This high signal from latch 138 also disables the
`PFM control circuit by forcing the output of NOR gate 202
`low. Thus, the circuit initially operates in PWM mode and
`will remain in PWM mode as long as the peak inductor
`current It is equal to or greater than the minimum current
`required for PWM mode, In, When I
`drops below
`In the regulator switches to PFM mode as previously
`described.
`PWM controller 140 generates a fixed frequency square
`wave PWM signal with a variable duty cycle. When the
`PWM signal is high (rising edge), a logic low signal appears
`at the output of invertor 170, turning off low-side switch 13.
`This high PWM signal also puts a logic high at the input of
`pulse circuit 151, which turns on switch 150 long enough to
`pull down the input of invertor 156, thus turning on switch
`11. Switch 150 is used to turn on switch 11 during PWM
`mode, while switch 152 is used to turn on switch 11 during
`PFM mode.
`Positive feedback is applied to inverters 154 and 156 so
`that the output of invertor 156 will remain low after switch
`150 (PWM mode) or switch 152 (PFM mode) turns off. It is
`important that switches 150 and 152 turn off as soon as
`possible to ensure that switches 146, 148, and 200 can reset
`the output of invertor 156 to a logic low to turn off switch
`11. Hence, switches 150 and 152 must be turned on with a
`relatively narrow pulse at the beginning of the PWM and
`PFM switching cycles, respectively.
`Pulse circuits 151 (PWM mode) and 153 (PFM mode)
`detect a leading edge from the outputs of invertor 144 and
`nor gate 160, respectively, and generate a positive pulse
`approximately 200 nanoseconds long at the gates of
`switches 150 and 152, respectively. This pulse turns on
`switches 150 and 152 just long enough to set the output of
`invertor 156 high, thereby turning on high-side switch 11.
`When the PWM signal is low (falling edge), switch 146
`pulls down the input of invertor 154, turning off switch 11.
`This low PWM signal also provides a logic high at the input
`of NAND gate 168, allowing low-side switch 13 to turn on
`when V swings low to -0.4V. This method of turning on
`switch 13 results in break-before-make switching of
`switches 11 and 13. Switch 11 remains off and switch 13
`remains on until the beginning of the next PWM cycle.
`Error amplifier 176 monitors V, during PWM operation
`by measuring the difference between the V and V. (V.
`appears across resistors 184, 186 which, acting as a voltage
`divider, generate V at node 185). This voltage difference is
`amplified and provided as input to PWM controller 140.
`PWM controller 140 uses this amplified voltage difference
`to adjust the duty cycle of the PWM signal so that V equals
`V, thereby regulating V. PWM controller 140 can be
`either a voltage mode or current mode controller. In order to
`achieve maximum efficiency when the regulator is operating
`in PFM mode, PWM controller 140 and error amplifier 176
`remain off during PFM mode.
`The regulator indirectly senses the current of inductor 15
`by monitoring the drain to source voltage V of switch 11.
`When switch 11 is on, switch 102 connects the drain of
`switch 11 to the inputs of comparators 122 and 124. When
`switch 11 is off, switch 104 shorts the inputs of comparators
`122 and 124 to the input voltage V. In order to eliminate
`the noise at the leading edge of the V waveform when
`switch 11 is turned on, capacitor 108 and resistor 112 keep
`switch 102 off and switch 104 on until switch 11 has been
`on approximately 200 nanoseconds. When switch 11 turns
`off, diode 114 allows switch 102 to turn off and switch 104
`to turn on immediately.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1034
`Page 13 of 15
`
`

`

`5,568,044
`
`10
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`15
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`20
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`25
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`7
`Comparator 122 causes high-side switch 11 to turn off
`when the peak inductor current I
`has exceeded the
`current limit for PWM mode (I) and PFM mode
`(Impr.). Comparator 122 monitors Ina by comparing
`the V of switch 11 to V of switch 116. In one embodi
`ment, switch 11 is a power MOSFET constructed of thou
`sands of small MOSFET cells connected in parallel. Switch
`116 is one of those MOSFET cells with its drain separated
`from the drain of switch 11. Switch 116 has an area factor
`of 1 (1 cell), while switch 11 has an area factor of K (K
`cells).
`When the regulator operates in PFM mode, switch 126 is
`off, allowing only current source 132 to flow through switch
`116. Current source 132 is set equal to I./K so that the
`V of switch 116 equals the V of switch 11 when I
`equals line. In other words, when the regulator is
`operating in PFM mode, the threshold voltage of comparator
`122 corresponds to Impr.
`When the regulator is operating in PWM mode, switch
`126 turns on to allow both current sources 130 and 132 to
`flow through switch 116. Current source 130 is set to a value
`so that the sum of current sources 130 and 132 equals
`In/K. Thus, the threshold voltage of comparator 122
`corresponds to I
`when the regulator is operating in
`Limpwm
`PWM mode.
`Comparator 124, monitoring the peak inductor current
`by comparing the V of switch 11 with the V of
`I,
`switch 118, determines when the regulator should switch
`from PWM mode to PFM mode. Like switch 116, switch 118
`is a single MOSFET cell (having an area factor of 1) with its
`drain separated from the drain of switch 11. Current source
`30
`128 provides a current through switch 118 equal to I./K,
`so that the V of switch 11 equals the V of switch 118
`when Ina reaches the value Int. The value of Inn is
`adjusted by a multiplier circuit so that it changes in propor
`tion to changes in V-V. This allows I
`to change in
`proportion to changes in AI, which, as shown in equation
`l, results in I
`remaining constant.
`Accordingly, if the peak inductor current It is greater
`than I, the regulator remains in PWM mode. Referring
`to FIG. 6A, this event corresponds to time period A. Com
`40
`parator 124 outputs a logic low which in turn produces a
`logic low at the output of SR latch 134. The output of latch
`134 remains low until reset to logic high by the falling edge
`of the PWM signal (see FIG. 6B). When switch 11 turns off,
`the rising edge of the inverted PWM signal appears at the
`clock input of master-slave D flip-flop 136 (see FIG. 6C).
`The inverted PWM signal is inverted again and used as the
`reset signal for latch 134. Due to the time delay of invertor
`163 and latch 134, the rising edge of the clock input of
`flip-flop 136 occurs before the output of latch 134 is reset to
`a logic high. Under the conditions of time period A, the
`output of flip-flop 136 is set to a logic high and remains high
`so long as Ina exceeds Inn (see FIG. 6D). The logic
`high output from flip-flop 136 has no effect on the previously
`set high output of SR latch 138 (see FIG. 6E).
`The logic high signal at the output of latch 138 turns on
`PWM controller 140 and error amplifier 176, as well as
`allowing the PWM signal to propagate through NAND gate
`142, thereby enabling PWM operation. The high signal from
`the output of latch 138 also turns on switch 126, re-setting
`the threshold voltage of comparator 122 to a value corre
`sponding to Iran. Furthermore, the high signal from the
`output of latch 138 prevents PFM control signals from
`propagating through NOR gate 202. By setting the threshold
`of comparator 122 to I
`and preventing PFM control
`signals from propagating through NOR gate 202, PFM mode
`operation is thereby disabled.
`
`50
`
`8
`If the inductor current Ina is equal to or exceeds Innwn,
`the output of comparator 122 transitions to a logic high,
`turning on switch 148. Switch 148 pulls down the input of
`invertor 120, which turns off switch 11. The positive feed
`back of weak inverters 154 and 156 keeps the output of 156
`low after switch 148 turns off so that switch 11 will remain
`off until the next rising edge of the PWM signal.
`When Ia is less than Inn (corresponding to time
`period B in FIG. 6A), the regulator enters PFM mode. The
`output of comparator 124 and the output of latch 134 remain
`at logic high when the PWM cycle ends (see FIG. 6B),
`causing the output of flip-flop 136 to transition to logic low
`(see FIG. 6D). The logic low signal at the output of flip-flop
`136 sets the output of latch 138 low (see FIG. 6E), which
`will remain low until reset to logic high by switch 178. This
`low signal from latch 138 turns off PWM controller 140 and
`error amplifier 176, and it prevents the PWM signal from
`propagating through NAND gate 142, thereby disabling the
`PWM control circuit. The low signal from latch 138 also
`enables PFM control signals to propagate through NOR gate
`202. In addition, the low signal from the output of latch 138
`turns off switch 126, resetting the threshold voltage of
`comparator 122 to a value corresponding to Inter. In
`other words, a low signal from the output of latch 138
`switches the regulator from PWM mode to PFM mode.
`Once in PFM mode, the on and off states of high-side
`switch 11 are controlled as described previously. Assuming
`that switch 11 is initially on, current flows through inductor
`15 to output terminal 17. When the inductor current I
`exceeds IP, comparator 122 turns off switch 11. In
`then discharges through diode 14, causing V to drop to
`-0.4 volts. When I
`discharges to Zero, causing V to
`swing to V, invertor 158 sends a logic low signal to NOR
`gate 160 which, in turn, puts a logic high at the input of pulse
`circuit 153. Pulse circuit 153, generating a brief turn on
`pulse at the gate of switch 152, causes switch 11 to turn on
`and thereby starts a new switching cycle.
`The regulator will skip cycles when V exceeds its
`nominal value V
`Comparator 172 monitors V by
`comparing V to V. When V is greater than V,
`comparator 172 puts a logic high at an input of NOR gate
`160, thereby preventing switch 11 from turning on in
`response to the signal swing of V via invertor 158. The
`logic high signal from comparator 172 also propagates
`through invertor 204 and NOR gate 202 so as to turn on
`switch 200, which causes switch 11 to turn off. Thus,
`high-side switch 11, turning off when the output voltage has
`exceeded its nominal value, will turn back on (when I
`discharges to Zero) only if the output voltage has dropped to
`less than or equal to its nominal value. As explained earlier,
`V, exhibits hysteresis to prevent the regulator from spo
`radically skipping cycles. Preferably, comparator 172 exhib
`its hysteresis at its input terminals of approximately 10 mV.
`As mentioned previously, a variation of PFM mode opera
`tion occurs when (1) the difference between V and V is
`approximately 1 volt or less and (2) the output current is less
`than Ire. Since under these conditions the inductor
`current never exceeds left, the output of comparator
`122 will remain at logic low and thus never turn off switch
`11. When V, exceeds V, the logic high output of
`comparator 172 turns on switch 200 which, in turn, causes
`switch 11 to turn off. The regulator then stops delivering
`current to output node 17. The output of comparator 172 will
`remain at logic high until V falls below V. When
`the output of compara