United States Patent (19)
`Nguyen
`
`USOO5955871A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,955,871
`Sep. 21, 1999
`
`54) VOLTAGE REGULATOR THAT BASES
`CONTROL ON A STATE OF A POWER
`CONSERVATION MODE
`
`75 Inventor: Don J. Nguyen, Portland, Oreg.
`73 Assignee: Intel Corporation, Santa Clara, Calif.
`
`21 Appl. No.: 09/173,483
`22 Filed:
`Oct. 14, 1998
`(51) Int. Cl." ........................................................ G05F 1/40
`52 U.S. Cl. ...................... 323/282; 323/285; 395/750.03
`58 Field of Search ..................................... 323/282, 283,
`323/284, 285, 259; 395/750.03, 75004,
`750.05
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,745,352 4/1998 Sandri et al. ............................. 363/41
`Primary Examiner Shawn Riley
`
`Attorney, Agent, or Firm Trop, Pruner, Hu & Miles, P.C.
`57
`ABSTRACT
`A Switching regulator for use with a computer System having
`a power conservation mode includes a Switch circuit, a
`Sampling Storage device, a Sampling circuit and a controller.
`The Switch circuit is coupled to an input Voltage Source to
`produce an output Voltage, and the Switch circuit provides an
`indication of a parameter of the regulator. When the com
`puter System is not in a power conservation mode, the
`controller operates the Sampling circuit to provide the indi
`cation to the Sampling Storage device at a Switching fre
`quency. When the computer System is in the power conser
`Vation mode, the controller operates the Sampling circuit to
`continuously provide the indication to the Sampling Storage
`device for Substantially the duration of the power conser
`Vation mode. Based on the indications provided to the
`Sampling Storage device, the controller interacts with the
`Switch circuit to regulate the output voltage.
`
`24 Claims, 7 Drawing Sheets
`
`DSPS OR
`Vosps
`
`46
`
`
`
`f
`
`182-VE
`
`F
`
`CONTROLLER
`
`42
`
`Whi
`
`FEEDBACK
`CIRCUIT
`
`44
`
`DRIVE
`CIRCUIT
`
`40
`V
`SW1
`Vsw2
`DSPS DR
`
`STP CLK#
`
`N-30
`
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`U.S. Patent
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`Sep. 21, 1999
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`Sheet 1 of 7
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`5,955,871
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`CONTROLLER
`
`VsWITCH 2
`
`
`
`
`
`FIG. 1 (PRIOR ART)
`
`VswiTCH 1
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`9 1
`
`19
`
`FG. 2
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`U.S. Patent
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`Sep. 21, 1999
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`Sheet 2 of 7
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`5,955,871
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`2O2
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`MICROPROC
`
`204
`
`206
`
`208
`
`211
`
`DISPLAY
`CNTRL
`
`2
`12
`
`210
`
`lose
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`DISPLAY
`
`MEMORY
`HUB
`
`SYSTEM
`MEMORY
`
`209
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`205
`
`I/O
`
`HUB
`
`216
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`217
`
`I/O
`
`242
`
`230
`
`–
`222
`KEYBOARD
`
`226
`
`O
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`232
`
`DRIVE
`CNTRL
`
`231
`
`224
`
`233
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`246
`
`
`
`240
`
`
`
`243
`
`FIG. 4
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`U.S. Patent
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`Sep. 21, 1999
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`Sheet 3 of 7
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`5,955,871
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`
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`37
`
`46
`
`f
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`VDsps
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`182-V
`F
`
`CONTROLLER
`
`controller
`
`42
`
`V,i
`
`DRIVE
`
`CIRCUIT
`
`FEEDBACK
`IRCUIT
`CIRCU
`44
`
`40
`V
`SW1
`Vsw2
`DSPS DR
`
`STP CLK#
`
`N-30
`
`FIG. 5
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`U.S. Patent
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`Sep. 21, 1999
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`Sheet 4 of 7
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`5,955,871
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`Vswa
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`11
`
`To
`
`T
`
`T2
`
`T
`
`V, V.V. V.
`M/N /N
`R-1 NU1
`V - a
`
`F
`
`FIG. 6
`
`FIG. 7
`
`FIG. 8
`
`FIG. 9
`
`FIG. 10
`
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`U.S. Patent
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`Sep. 21, 1999
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`Sheet 5 of 7
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`5,955,871
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`
`
`C2
`LL
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`
`
`s= s=
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`t FIG. 12
`
`t FIG. 13
`
`t FIG. 14
`
`Ts2
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`U.S. Patent
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1007
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`U.S. Patent
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`Sep. 21, 1999
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`Sheet 7 of 7
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`5,955,871
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`| 7
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`ERHdZwsA
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`5,955,871
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`1
`VOLTAGE REGULATOR THAT BASES
`CONTROL ON A STATE OF A POWER
`CONSERVATION MODE
`
`15
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`25
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`BACKGROUND
`The invention relates to a Voltage regulator, Such as a
`Switching Voltage regulator.
`ADC-to-DC voltage regulator typically is used to convert
`a DC input voltage to either a higher or a lower DC output
`Voltage. One type of Voltage regulator is a Switching regu
`lator which is often chosen due to its Small size and
`efficiency. The Switching regulator typically includes one or
`more Switches that are rapidly opened and closed to transfer
`energy between an inductor (a stand-alone inductor or a
`transformer, as examples) and an input voltage Source in a
`manner that regulates an output Voltage.
`AS an example, referring to FIG. 1, one type of Switching
`regulator is a Synchronous Buck Switching regulator 10 that
`receives an input DC voltage (called V) from an input
`Voltage Source 9 and converts the Vy Voltage to a lower
`regulated output Voltage (called Vor?) that appears at an
`output terminal 11. To accomplish this, the regulator 10 may
`include a Switch 20 (a metal-oxide-semiconductor field
`effect-transistor (MOSFET), for example) that is operated
`(via a Switching control Voltage called Vs) by a
`controller 15 in a manner to regulate the V. Voltage.
`Referring also to FIGS. 2 and 3, in particular, the con
`troller 15 opens and closes the Switch 20 to control
`energization/de-energization cycles 19 (each having a con
`stant duration called Ts) of an inductor 14. In each cycle 19,
`the controller 15 asserts (drives high, for example) the
`Vswitc. Voltage during an on interval (called Tow) to
`Close the Switch 20 and transfer energy from the input
`Voltage Source 9 to the inductor 14. During the Ty interval,
`a current (called I, (see FIG. 3)) of the inductor 14 has a
`positive slope. During an off interval (called T.) of the
`cycle 19, the controller 15 deasserts (drives low, for
`example) the Vswitc. Voltage to open the Switch 20 and
`isolate the input voltage source 9 from the inductor 14. At
`this point, the level of the I current is not abruptly halted,
`but rather, a diode 18 (see FIG. 1) begins conducting to
`transfer energy from the inductor 14 to a bulk capacitor 16
`and a load (not shown) that are coupled to the output
`terminal 11. During the T interval, the It current has a
`negative slope, and the controller 15 may close another
`Switch 21 (via a signal called Vswitc.) to shunt the diode
`18 to reduce the amount of power that is otherwise dissi
`pated by the diode 18. The bulk capacitor 16 serves as a
`Stored energy Source that is depleted by the load, and
`additional energy is transferred from the inductor 14 to the
`bulk capacitor 16 during each Ty interval.
`For the Buck Switching regulator, the ratio of the Ty
`interval to the T interval, called a duty cycle, generally
`governs the ratio of the V
`to the Vy Voltages. Thus, to
`increase the V. Voltage, the controller 15 may increase
`the duty cycle, and to decrease the V. Voltage, the
`controller 15 may decrease the duty cycle. For purposes of
`monitoring the V. Voltage, the controller 15 may receive
`a voltage (called V) that is proportional to the V.
`60
`Voltage. The V. Voltage may be provided by a resistor
`divider 13 that is coupled to the output terminal 11.
`The regulator 10 may be used in a computer (a laptop
`computer, for example) that is capable of entering a power
`conservation mode, Such as a stop clock mode, for example.
`In the power conservation mode, the power losses intro
`duced by the on-off transitions of the Switches 20 and 21
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`become significant, as compared to the total amount of
`power being consumed by the computer. Therefore, for
`purposes of maximizing the efficiency of the regulator 10,
`the controller 15 may leave the Switch 21 open during the
`power conservation mode.
`
`SUMMARY
`In one embodiment, a method for use with a computer
`System having a power conservation mode includes when
`the computer System is not in the power conservation mode,
`Sampling indications of a parameter of a Switching regulator
`at a Switching frequency. When the computer System is in
`the power conservation mode, the method includes obtain
`ing a Substantially continuous indication of the parameter for
`Substantially the duration of the power conservation mode.
`An output Voltage of the regulator is regulated based on the
`indications.
`
`BRIEF DESCRIPTION OF THE DRAWING
`FIG. 1 is a Schematic diagram of a Switching Voltage
`regulator of the prior art.
`FIGS. 2 and 3 are voltage and current waveforms that
`illustrate operation of the regulator of FIG. 1.
`FIG. 4 is a Schematic diagram of a computer System
`according to an embodiment of the invention.
`FIG. 5 is a Schematic diagram of a Switching Voltage
`regulator of the computer System of FIG. 4 according to an
`embodiment of the invention.
`FIGS. 6, 7, 8, 9 and 10 are voltage and current waveforms
`that illustrate operation of the regulator of FIG. 5 without
`transient load conditions.
`FIGS. 11, 12, 13 and 14 are voltage and current wave
`forms that illustrate operation of the regulator of FIG. 5 with
`transient load conditions.
`FIG. 15 is a more detailed schematic diagram of the
`regulator of FIG. 5 according to an embodiment of the
`invention.
`FIG. 16 is a schematic diagram of the driver circuit of
`FIG. 15.
`
`DETAILED DESCRIPTION
`Referring to FIG. 4, an embodiment 200 of a computer
`System in accordance with the invention includes Voltage
`regulation circuitry 246 that provides power to components
`of the computer system 200 via power lines 242. As
`described below, the Voltage regulation circuitry 246 has
`features that enhance the output Voltage accuracy and power
`conversion efficiency of the Voltage regulation circuitry 246
`when the computer system 200 enters a power conservation
`mode, Such as a stop clock mode, for example.
`Referring to FIG. 5, as an example, in Some embodiments,
`the Voltage regulation circuitry 246 may include a Synchro
`nous Switching Buck regulator 30 that has its output terminal
`33 coupled to one or more of the power lines 242. The
`regulator 30 includes an inductor 34 that is selectively
`energized and de-energized to regulate an output voltage
`(called V.) that appears at the output terminal 33. To
`accomplish this, the regulator 30 may include a controller 42
`that interacts with a Switch drive circuit 44 to generate
`non-Overlapping Switching Voltages called Vs and Vs
`(see also FIGS. 6 and 7) that control operations of comple
`mentary switches 32 and 38, respectively. In this manner, the
`controller 42 may close the switch 32 (a short time after
`opening the Switch 38) to couple an input voltage Source 35
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`3
`(that provides an input voltage called V DC) to the inductor
`34 during a T interval to transfer energy to the inductor
`34, and the controller 42 may close the switch 38 (a short
`time after opening the Switch 32) to provide a path for
`transferring energy from the inductor 34 to the output
`terminal 33 during a T interval. A bulk capacitor 48 may
`Store part of the energy that is transferred from the inductor
`34 and help regulate the Vo Voltage.
`For purposes of limiting the amount of power that is
`dissipated when the computer system 200 is not in the power
`conservation mode (i.e., when the computer system 200 is in
`a higher power dissipation State), the controller 42 may
`lower the V. Voltage. In Some embodiments, the con
`troller 42 may perform this function by monitoring a param
`eter of the regulator 30 that indicates the power output of the
`regulator 30 and regulating the V. Voltage based on the
`indicated power output. As a result of this technique, the
`regulator 30 may regulate the V. Voltage near one of two
`levels: a lower level when the computer system 200 is not in
`the power conservation mode and a higher level when the
`computer system 200 is in the power conservation mode.
`For example, the controller 42 may use a Sampled indi
`cation of the average I current and regulate the level of the
`Vo Voltage based on the Sampled average. As a result of
`this technique, when the computer system 200 enters the
`power conservation mode, the computer System 200 requires
`far less I, current than for operation outside of the power
`conservation mode, and the controller 42 raises the level of
`the Vo Voltage in response to a detected low average
`level of the It current. Conversely, when the computer
`system 200 is not in the power conservation mode, the
`computer System 200 requires more I, current, and the
`controller 42 lowers the level of the V. Voltage in
`response to a detected higher average level of the I current.
`In Some embodiments, the controller 42 Samples the
`average I current by periodically activating Sampling cir
`cuitry that may include, for example, a Switch 47. In this
`manner, the controller 42 closes the Switch 47 to sample a
`Voltage acroSS a Sampling resistor 46 that is in Series with the
`parallel combination of the Switch 38 and the diode 36. The
`closing of the Switch 47 Stores a sampled Voltage (called
`V,ses)in a storage device, Such as a Sampling capacitor 82.
`The controller 42, in turn, uses the Voss Voltage to regulate
`the V. Voltage, in a manner described below.
`When the computer system 200 is not in the power
`conservation mode, the controller 42 closes and opens the
`switch 47 (via a voltage called DSPS DR) concurrently
`with the Switch 38 to update the Voss Voltage. However,
`when the computer system 200 is in the power conservation
`mode, the controller 42 operates the Switch 47 in a different
`manner to conserve power and accurately indicate the aver
`age I, current, as described below.
`More specifically, the Switching losses introduced by the
`on-off transitions of the Switches (the Switches 38 and 47, as
`examples) become significant during the power conserva
`tion mode, as compared to the total amount of power being
`used by the computer system 200. Therefore, for purposes of
`maximizing the efficiency of the regulator during the power
`conservation mode, a regulator could possibly open both of
`the Switches 38 and 47 during the power conservation mode,
`and as a result, the regulator may effectively become a
`non-Synchronous Buck converter during the power conser
`Vation mode.
`However, it has been discovered that the power conser
`Vation mode may last for a time that is Sufficient to Sub
`Stantially deplete the charge Stored on the Sampling capaci
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`tor 82 if the Switch 47 is left open during the power
`conservation mode. Therefore, because the V,
`Voltage
`controls the V. Voltage (as described below), depletion
`of charge from the Sampling capacitor 82 may cause the
`controller 42 to Set the V. Voltage to an incorrect Voltage
`level.
`For purposes of ensuring that the Voss Voltage accu
`rately indicates the average I current, the regulator 30 does
`not open the Switch 47 during the power conservation mode.
`Instead, the regulator 30 closes the Switch 47 for substan
`tially the entire duration of the power conservation mode to
`continuously provide the Voltage acroSS the resistor 46 to the
`capacitor 82. The continuous closing of the Switch 47 also
`minimizes power losses due to Switching, as the Switch 47
`does not open and close at the Switching frequency during
`the power conservation mode. Thus, by keeping the Switch
`47 closed during the power conservation mode, the regulator
`30 maintains the Voss Voltage at the appropriate level and
`as a result, maintains the V. Voltage at the appropriate
`level.
`Thus, the advantages of the above-described arrangement
`may include one or more of the following: power losses may
`be minimized; accurate Voltage regulation may be achieved
`during the power conservation mode; and efficiency of the
`regulator may be enhanced.
`The current Sensing resistor 46 may be coupled between
`a Sampling node 37 and ground and may also be coupled in
`series with the parallel combination of the diode 36 and the
`main current path of the Switch 38. The anode of the diode
`36 may be coupled to the sampling node 37, and the cathode
`of the diode 36 may be coupled to a node 41. The inductor
`34 may be coupled between the node 41 and the output
`terminal 33, and the main current path of the Switch 32 may
`be coupled between the input voltage source 35 and the node
`41. The main current path of the Switch 47 may be coupled
`between the sampling node 37 and one terminal of the
`Sampling capacitor 82. The other terminal of the Sampling
`capacitor 82 may be coupled to ground.
`A typical controller may operate the Switches 32 and 38
`at a fixed Switching frequency and regulate a duty cycle of
`the Switching based on a monitored level of the V
`Voltage. However, unlike the typical controller, the control
`ler 42 regulates the V. Voltage by monitoring an indi
`cation (provided by a voltage called V that is proportionate
`to the Vo Voltage, for example) of the Vo Voltage and
`controlling the frequency of the Switching based on this
`indication. The V, Voltage is furnished by a feedback circuit
`40.
`In Some embodiments, the controller 42 interacts with the
`drive circuit 44 by generating a voltage called Vit (wherein
`the suffix "#" denotes negative, or inverse logic) that the
`drive circuit 44 receives and converts into the Vs and
`Vs. Voltages. The Vs Voltage generally indicates the
`complement of the Vit Voltage, and the Vs Voltage
`generally indicates the Vif voltage. The drive circuit 44
`includes circuitry to prevent the Vs. and Vs. Voltages
`from overlapping to keep the regulator 30 functioning
`properly.
`In Some embodiments, to regulate the Switching
`frequency, the controller 42 regulates a ripple Voltage com
`ponent that is present in the Vo Voltage. Referring also
`to FIG. 9, in this manner, the controller 42 monitors the V
`Voltage, and in response, the controller 42 operates the
`switches 32 and 38 (via selective assertion of the Vit
`voltage) to keep the V, Voltage between a high voltage
`threshold (called V) and a low voltage threshold (called
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`V,). This regulation, in turn, keeps the Vort Voltage within
`predetermined regulated limits (limits within 5% of a pre
`determined voltage level, for example).
`Referring to FIGS. 5, 6, 7, 9 and 10, the controller 42
`regulates the Switches 32 and 38 in the following manner for
`an exemplary energization/de-energization cycle 11 that
`lasts from time To to time T. First, the controller 42
`interacts with the drive circuit 44 to assert, or drive high, the
`Vs. Voltage at time To. The assertion of the Vs. Voltage
`causes the Switch 32 to close. Once this occurs, the I current
`(see FIG. 10) has a positive slope, as energy is being Stored
`in the inductor 34 from time T to time T. Also during the
`interval from time To to time T, the V. Voltage rises
`upwardly from the low threshold voltage V, to the upper
`threshold Voltage V. In this manner, at time T, the V
`Voltage reaches the upper threshold V. The controller 42
`detects this occurrence and responds by interacting with the
`drive circuit 44 to deassert, or drive low, the Vs Voltage
`to open the Switch 32.
`The opening of the Switch 32 begins an interval during
`which energy is transferred from the inductor 34 to the bulk
`capacitor 48. After the Switch 32 opens, the diode 36
`conducts and allows energy to be transferred from the
`inductor 34 and to the output terminal 33. The I, circuit
`assumes a negative slope from time T to T. A short time
`after the controller 42 deasserts the Vs. Voltage, the
`controller 42 asserts the Vs. Voltage to close the Switch 38.
`The closed Switch 38, in turn, shunts the diode 36 which
`reduces the effective resistance path for the It current and
`thus, reduces the power that is otherwise dissipated by the
`diode 36.
`The controller 42 asserts the Vs Voltage from time T
`to T. to allow energy to be transferred from the inductor 34.
`This transfer of energy causes the V, Voltage (which indi
`cates the V. Voltage) to decrease from the V, threshold
`to the V, threshold. When the V voltage reaches the V,
`threshold at time T, this event causes the controller 42 to
`interact with the drive circuit 44 to deassert the Vs
`Voltage, which, in turn, causes the Switch 38 to open. A short
`time thereafter, the controller 42 closes the Switch 32 to
`begin another energization/de-energization cycle.
`Thus, for the regulator 30 the Switching frequency and
`duty cycle are not constant, but rather, the controller 42 may
`dynamically adjust both to accommodate changing load
`conditions. As an example, the waveforms shown in FIGS.
`6, 7, 9 and 10 illustrate a Scenario when the V. Voltage
`stays within regulation (i.e., the proportionate V, Voltage
`stays within the V, and V, limits) and no load transient load
`conditions occur. However, referring to FIGS. 11, 12, 13 and
`14, a different Scenario may occur in which the requirements
`of the load change rapidly and cause the Vo Voltage to
`undershoot or overshoot predetermined regulated limits.
`However, the regulator 30, because of its variable frequency
`and duty cycle control, responds rapidly to this Scenario, as
`described below.
`In particular, referring to FIG. 11, another exemplary
`power cycle 150 begins at time T. During the power cycle
`150, the V voltage may rise to a voltage above the V,
`threshold. When the controller 42 responds to this occur
`rence at time T, the controller 42 interacts with the drive
`circuit 44 to deassert the Vs. Voltage to open the Switch 32.
`The opening of the Switch 32 prevents additional energy
`from being transferred from the input voltage source 35 to
`the inductor 34. From time Ts to time T, the I current
`assumes a negative slope and transferS energy from the
`inductor 34, an event that lowers the V. Voltage. The
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`interval from times Ts to T is Sufficient to allow the V
`Voltage to decrease back to a regulated range of values.
`When the V voltage drops to the V, threshold at time T,
`the controller 42 interacts with the drive circuit 44 to assert
`the Vs. Voltage to once again close the Switch 32 and cause
`the V. Voltage to rise. Thus, due to the above-described
`mechanism, the T time is variable, as the Switch 32 stays
`closed for an appropriate time for regulation to occur.
`Conversely, in the opposite Situation when a Voltage droop
`(instead of a Voltage Surge) in the Vo Voltage occurs, the
`controller 42 permits a variable Ty time to allow additional
`energy to be transferred into the inductor 34 to raise the level
`of the Voort Voltage.
`Referring to FIG. 15, in some embodiments, the controller
`42 may include a hysteretic comparator circuit 56 which
`compares the V. Voltage to the V, and V, thresholds to
`generate the Vit Voltage. The Vit Voltage, in turn, is used
`by the drive circuit 44 to generate the Vs and Vs.
`Voltages. In this manner, the circuit 56 may include a
`comparator 58 (a comparator with a 10 nanosecond (ns)
`propagation delay, for example) that furnishes the Vif
`Voltage at an inverting output terminal. The circuit 56 may
`be coupled to the feedback circuit 40 that is formed from
`resistors 50 and 52 and furnishes the V voltage at the union
`the resistors 50 and 52. A resistor 54 (of the circuit 56) is
`coupled between the inverting input and output terminals of
`the comparator 58 to establish the hysteretic thresholds V,
`and V. The non-inverting input terminal of the comparator
`58 receives a reference voltage (called V) which may be
`located approximately midway between the V and V,
`thresholds, as shown in FIG. 11, and is used, in Some
`embodiments, to adjust the level of the V. Voltage based
`on the power output of the regulator 30, as described below.
`Thus, due to the above-described arrangement, the com
`parator 58 asserts (drives high, for example) the Vif voltage
`when the V voltage decreases below the V, threshold and
`deasserts (drives low, for example) the Vif voltage when the
`V. Voltage rises above the V, threshold.
`In Some embodiments, the Switch 32 may include a
`metal-oxide-Semiconductor field-effect-transistor
`(MOSFET) 43 which has its drain arranged to receive the
`V DC voltage and its source coupled to the node 41. The
`gate of the MOSFET 43 receives the Vs voltage. The
`switch 38 may include a MOSFET 39 which has its drain
`coupled to the node 41 and its Source coupled to the
`sampling node 37. The gate of the MOSFET 39 receives the
`Vs. Voltage. The diode 36 may be an intrinsic diode of the
`MOSFET 39, for example. The switch 47 may include a
`MOSFET 80 that has its drain coupled to the sampling node
`37 and its Source Serially coupled to one terminal of a
`resistor 84 of a voltage adjustment circuit 87, as described
`below.
`Among other features of the Voltage adjustment circuit
`87, the other terminal of the resistor 84 is coupled to the
`non-inverting input terminal of the comparator 58 and
`provides the V. Voltage. The output voltage adjustment
`circuit 87 may also include a capacitor 86 that is coupled
`between the non-inverting input terminal of the comparator
`58 and ground. A resistor 88 is coupled between the non
`inverting input terminal of the comparator 58 and a node 91.
`The node 91, in turn, provides a reference voltage (called
`V). A resistor 92 is coupled between the node 91 and a
`positive Voltage Supply, and a Zener diode 90 has its cathode
`coupled to the node 90 and its anode coupled to the ground.
`In this manner, at powerup, the Zener diode 90 establishes
`the Vic Voltage.
`Because the Voss Voltage indicates the average I,
`current, the Voss Voltage decreases during the power
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1007
`Page 11 of 14
`
`

`

`7
`conservation mode and, in turn, decreases the level of the V
`Voltage due to the following relationship:
`
`5,955,871
`
`WR = (VREF - Vasps)
`
`+ VDSPs,
`
`8
`206 may interface the front side bus 204, a memory bus 209
`and an Accelerated Graphics Port (AGP) bus 211 together.
`A system memory 208 may be coupled to the memory bus
`209, and a display controller 212 (that controls a display
`214) may be coupled to the AGP bus 211. A hub commu
`nication link 205 may couple the memory hub 206 to a
`downstream bridge circuit, or input/output (I/O) hub 210.
`The I/O hub 210 may include interfaces to an Industry
`Standard Architecture (ISA) bus 216 and a Peripheral Com
`ponent Interconnect (PCI) bus 230. An I/O controller 217
`may be coupled to the ISA bus 216 and receive input data
`from a keyboard 224 and a mouse 226, as examples. The I/O
`controller 217 may also control operations of a floppy disk
`drive 222. A drive controller 231 may be coupled to the PCI
`bus 230 and may control operations of a hard disk drive 232
`and a CD-ROM drive 233, as examples.
`While the invention has been disclosed with respect to a
`limited number of embodiments, those skilled in the art,
`having the benefit of this disclosure, will appreciate numer
`ouS modifications and variations therefrom. It is intended
`that the appended claims cover all Such modifications and
`variations as fall within the true Spirit and Scope of the
`invention.
`What is claimed is:
`1. A Switching regulator for use with a computer System
`having a power conservation mode, comprising:
`a Switch circuit coupled to an input voltage Source to
`produce an output Voltage;
`a Sampling Storage device;
`a Sampling circuit, and
`a controller to:
`operate the Sampling circuit to first provide an indica
`tion of the output voltage to the sampling storage
`device at a Switching frequency when the computer
`System is not in the power conservation mode,
`when the computer System is in the power conservation
`mode, operate the Sampling circuit to continuously
`provide the indication to the Sampling Storage device
`for Substantially the duration of the power conser
`Vation mode, and
`based on the first and continuously provided
`indications, interact with the Switch circuit to regul
`late the output voltage.
`2. The Switching regulator of claim 1, wherein the Sam
`pling circuit comprises a Switch to Selectively provide the
`indication to the Sampling Storage device.
`3. The Switching regulator of claim 2, wherein the Switch
`comprises a transistor.
`4. The Switching regulator of claim 1, wherein the Sam
`pling Storage device comprises a capacitor.
`5. The Switching regulator of claim 1, wherein the Switch
`circuit comprises:
`a Switch; and
`an energy Storage element,
`wherein the controller further operates the Switch to
`regulate the output Voltage when the computer System
`is in the power conservation mode based on the con
`tinuously provided indication.
`6. The Switching regulator of claim 1, wherein the indi
`cation comprises an indication of a current.
`7. The Switching regulator of claim 1, wherein the Switch
`circuit comprises:
`a Switch; and
`an energy Storage element,
`wherein the controller further operates the Switch to
`regulate the output Voltage when the computer System
`
`15
`
`25
`
`where Rs and Rss represent the resistances of resistorS 84
`and 88, respectively, and V represents a reference Volt
`age. Therefore, because of the comparison that is performed
`by the comparator circuit 56, the downward adjustment of
`the V. Voltage during the power conservation mode of the
`computer System 200 upwardly adjusts the V. Voltage.
`Conversely, the Voss Voltage increases when the computer
`system 200 is not in the power conservation mode and
`downwardly adjusts the Vo Voltage.
`In Some embodiments, the regulator 30 may include a
`powerup circuit 103 to hold the V. Voltage to ground during
`powerup. The end of powerup may be indicated by the
`insertion of a V oxy voltage. When powerup has occurred,
`then the circuit 103 decouples itself from the non-inverting
`input terminal of the comparator 58, and allows the circuitry
`to behave as described above.
`Referring to FIG. 16, the drive circuit 44 includes a
`Voltage buffer, or driver 144, that furnishes the Vs Voltage
`at its output terminal. An inverted indication of the Vs
`voltage is received by an input terminal of a NAND gate
`140. Another input terminal of the NAND gate 140 receives
`a STP CLK# signal which is asserted, or driven low, to
`indicate the power conservation mode and deasserted, or
`driven high, otherwise. The output terminal of the NAND
`gate 140 furnishes a DSPS DR signal that is received by the
`gate of the Sampling transistor 80. Therefore, as a result of
`this arrangement, when the computer System 200 is in the
`power conservation mode, the NAND gate 140 asserts the
`DSPS DR signal to cause the sampling transistor 80 to
`conduct, and when the computer system 200 is not in the
`power conservation mode, the state of the DSPS DR signal
`closely follows the State of the Vs Voltage.
`The drive circuit 44 may also include an overlap protec
`tion circuit 148 that uses the Vif voltage to generate two
`40
`non-Overlapping Voltages called Vs were and Vs wer.
`The Vs
`et Voltage generally follows the complement of
`the Vit signal, and the Vs
`Pro Voltage generally follows
`the Vit Voltage. Adriver 146 receives the Vs
`et Voltage
`and furnishes the Vs Voltage. An AND gate 142 receives
`the Vs
`et Voltage and the STP CLK# signal. The
`output terminal of the AND gate 142 is coupled to an input
`terminal of a driver 144, and the output terminal of the driver
`144 furnishes the Vs. Voltage. In this manner, when the
`computer system 200 is not in the power conservation mode
`(i.e., when the STP CLK# Signal is dcasserted), the Vs
`Voltage follows the Vs
`Pro Voltage. However, when the
`computer system 200 is in the power conservation mode
`(i.e., when the STP CLKit Signal is asserted), the Vs.
`Voltage is deasserted.
`Referring back to FIG. 4, in addition to the voltage
`regulation circuitry 246, the computer system 200 may also
`include an AC-to-DC converter 240 that may receive an AC
`wall Voltage and convert the AC Voltage into a DC voltage
`that is provided to the voltage regulation circuitry 246. The
`60
`Voltage regulation circuitry 246 may also receive a DC
`voltage from a battery pack 243 that furnishes power when
`AC power is unavailable.
`Among the components that consume power, the com
`puter system 200 may include a microprocessor 202 and a
`65
`bridge circuit, or memory hub 206, both of which are
`coupled to a local, or front side, bus 204. The memory hub
`
`35
`
`45
`
`50
`
`55
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1007
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`

`5,955,871
`
`is not in the power conservation mode based on the first
`provided indications.
`8. The Switching regulator of claim 1, wherein the Switch
`ing regulator comprises a Synchronous Buck Switching
`regulator when the c