Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 1 of 38
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`
`
`Plaintiff,
`
`
`
`v.
`
`
`HD SILICON SOLUTIONS LLC,
`
`
`
`
`
`MICROCHIP TECHNOLOGY INC.,
`
`
`
`
`
`Civil Action No. 6:20-cv-1092-ADA
`
`PATENT CASE
`
`JURY TRIAL DEMANDED
`
`
`
`Defendant.
`
`PLAINTIFF’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
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`
`
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1058
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 2 of 38
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`TABLE OF CONTENTS
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`I.
`
`INTRODUCTION............................................................................................................. 1
`
`II.
`
`ARGUMENT ..................................................................................................................... 1
`
`A.
`
`Claim Terms for U.S. Patent No. 6,774,033 ........................................................... 1
`
`1.
`2.
`3.
`4.
`
`5.
`
`Background ..................................................................................................1
`“interconnect” ..............................................................................................2
`“depositing a second film over the first film” ..............................................3
`“metal stack” / “the first film and the second film forming a metal
`stack”............................................................................................................5
`“in-situ” ........................................................................................................7
`
`B.
`
`Claim Terms for U.S. Patent No. 7,154,299 ........................................................... 8
`
`1.
`2.
`
`3.
`4.
`
`Background ..................................................................................................8
`“via no circuit element other than one or more switch elements” /
`“via no circuit element other than one or more pass gates” .........................9
`“no circuit element” ...................................................................................11
`“the logic circuit element” .........................................................................11
`
`C.
`
`Claim Terms for U.S. Patent No. 7,260,731 ......................................................... 14
`
`1.
`2.
`3.
`4.
`5.
`
`6.
`
`Background ................................................................................................14
`“during a voltage transition” ......................................................................15
`“power is saved” ........................................................................................16
`“reduce its output voltage below a specified output voltage”....................17
`“means for providing signals at the input terminal of the voltage
`regulator” ...................................................................................................19
`“means for changing the voltage regulator [mode]” ..................................20
`
`D.
`
`Claim Terms for U.S. Patent No. 7,302,619 ......................................................... 20
`
`1.
`2.
`3.
`4.
`5.
`
`Background ................................................................................................20
`“fetching” / “fetched” ................................................................................21
`“means for detecting an error” ...................................................................21
`“means for generating a corrected instruction” .........................................23
`“means for writing the corrected instruction back to the instruction
`cache” .........................................................................................................24
`
`E.
`
`Claim Terms for U.S. Patent No. 7,810,002 ......................................................... 25
`
`1.
`2.
`3.
`
`Background ................................................................................................25
`“scan interface” ..........................................................................................25
`“software layer” .........................................................................................26
`
`
`
`i
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 3 of 38
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`F.
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`Claim Terms for U.S. Patent No. 8,870,404 ......................................................... 27
`
`1.
`2.
`3.
`4.
`5.
`
`Background ................................................................................................27
`“transition time” .........................................................................................28
`“allowed time” ...........................................................................................29
`“means for processing” ..............................................................................30
`“means for supplying a voltage” ................................................................31
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`III. CONCLUSION ............................................................................................................... 33
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`ii
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 4 of 38
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`TABLE OF AUTHORITIES
`
`CASES
`
`Automated Techs., Inc. v. Microfil, LLC,
`244 Fed. App’x 354 (Fed. Cir. 2007)................................................................................ 12
`
`Ergo Licensing, LLC v. CareFusion 303, Inc.,
`673 F.3d 1361 (Fed. Cir. 2012)......................................................................................... 23
`
`KCJ Corp. v. Kinetic Concepts, Inc.,
`223 F.3d 1351 (Fed. Cir. 2000)......................................................................................... 32
`
`Microsoft Corp. v. i4i Ltd. Partnership,
`564 U.S. 91 (2011) ...................................................................................................... 14, 23
`
`Minnesota Mining & Mfg. Co. v. Molex, Inc.,
`2000 WL 35731890 (W.D. Tex. Nov. 16, 2000) ................................................................ 3
`
`Nautilus Inc. v. Biosig Instruments, Inc.,
`572 U.S. 898 (2014) .............................................................................................. 14, 23, 28
`
`Nevro Corp. v. Bos. Sci. Corp.,
`955 F.3d 35 (Fed. Cir. 2020)............................................................................................. 24
`
`O2 Micro Int’l Ltd. v. Beyond Innovation Tech. Co.,
`521 F.3d 1351 (Fed. Cir. 2008)........................................................................................... 3
`
`U.S. Surgical Corp. v. Ethicon, Inc.,
`103 F.3d 1554 (Fed. Cir. 1997)......................................................................................... 26
`
`
`
`
`
`
`
`iii
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 5 of 38
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`
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`I.
`
`
`
`INTRODUCTION
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`Plaintiff HDSS respectfully requests the entry of an order resolving the claim construction
`
`disputes as HDSS proposes below.
`
`II.
`
`ARGUMENT
`
`A.
`
`Claim Terms for U.S. Patent No. 6,774,033
`
`1.
`
`Background
`
`
`
`The ’033 Patent is titled “Metal Stack for Local Interconnect Layer.” As the specification
`
`explains, integrated circuits may have several levels of interconnect layers, which are employed to
`
`electrically couple various nodes. See ’033 Patent, at 1:10–12. Interconnect layers employed
`
`throughout a given level of an integrated circuit are called “regular interconnect layers,” while
`
`those employed in a relatively small section of an integrated circuit are called “local interconnect
`
`layers.” See id. at 1:17–30. The patent discloses improved methods for forming local interconnect
`
`layers.
`
`
`
`Claim 1 of the ’033 Patent provides an exemplar and includes many of the disputed terms
`
`(as emphasized):
`
`1. A method of forming a local interconnect layer in an integrated circuit, the
`method comprising:
`
`depositing a first film over an oxide layer, the first film comprising titanium
`nitride; and
`
`depositing a second film over the first film, the second film comprising
`tungsten, the first film and the second film forming a metal stack of the local
`interconnect layer.
`
`
`
`1
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 6 of 38
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`2.
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`“interconnect”
`
`Claim Language
`
`HDSS’s Construction
`
`Microchip’s Construction
`
`“interconnect”
`(’033: 1)
`
`Providing an electrically
`conductive connection.
`
`Plain and ordinary meaning (which
`is “a structure that electrically
`connects two or more circuit
`elements”).
`
`With respect to the term “interconnect,” it appears from Microchip’s brief that the parties’
`
`dispute is largely grammatical. Microchip insists that “interconnect” is a noun and claims that
`
`HDSS proposes to construe it as a verb. ECF No. 38 at 7. Microchip is wrong. “Interconnect” in
`
`the claims is an adjectival noun, and HDSS proposes construing it as one.
`
`
`
`The term “interconnect” appears as part of the phrase “local interconnect layer.” In this
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`context, “interconnect” is a noun modifying another noun, “layer.” Like “race” in “race car” or
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`“lemon” in “lemon tea,” “interconnect” is a noun serving as an adjective. Accordingly, HDSS
`
`proposes a construction aligning with how “interconnect” is used in context.
`
`
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`With that understanding, there are two differences between the parties’ proposed
`
`constructions. First, HDSS’s construction clarifies that the electrical connection is conductive.
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`This tracks the specification, which explains that local interconnect layers are conductive as
`
`opposed to isolating. See, e.g., ’033 Patent, at 1:11–14 (“Interconnect layers are employed to
`
`electrically couple various nodes of an integrated circuit. An integrated circuit may have several
`
`levels of interconnect layers, with a dielectric layer providing electrical isolation between levels.”).
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`It also tracks the claims, which recite using conductive materials (titanium nitride and tungsten).
`
`Consequently, HDSS’s construction is more precise. Second, although Microchip purports to
`
`propose a plain and ordinary meaning, it defines “interconnect” as connecting “two or more circuit
`
`elements.” ECF No. 38, at 7. The phrase “circuit elements” does not appear anywhere in the patent.
`
`Nor has Microchip offered any extrinsic evidence that would support construing “interconnect” by
`
`
`
`2
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`reference to “circuit elements.” Consequently, Microchip’s proposed construction should be
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`rejected.
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`3.
`
`“depositing a second film over the first film”
`
`Claim Language
`
`HDSS’s Construction
`
`Microchip’s Construction
`
`Plain and ordinary meaning.
`
`“depositing a second
`film over the first
`film”
`(’033: 1, 15)
`
`Depositing a second film above the
`top surface of the first film and the
`oxide layer, where a “film” is a thin
`layer of material having a thickness
`from top to bottom as its smallest
`dimension.
`
`
`
`
`Microchip proposed the straightforward phrase “depositing a second film over the first
`
`film” for construction, but the language does not require construction. See O2 Micro Int’l Ltd. v.
`
`Beyond Innovation Tech. Co., 521 F.3d 1351, 1362 (Fed. Cir. 2008) (recognizing that “district
`
`courts are not (and should not be) required to construe every limitation present in a patent’s
`
`asserted claims”); Minnesota Mining & Mfg. Co. v. Molex, Inc., 2000 WL 35731890, at *3 (W.D.
`
`Tex. Nov. 16, 2000) (declining to further define the term “adjacent” and noting: “The Court
`
`continues to be amazed that parties in patent litigation feel the need to re-define straightforward,
`
`simple terms.”) In asking the Court to construe this phrase, Microchip seeks to rewrite
`
`unambiguous claim language and import three new limitations found nowhere in the patent.
`
`
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`First, Microchip proposes that “over” be construed as “above the top surface of.” ECF No.
`
`38, at 9. But Microchip does not suggest that the everyday preposition “over” lacks a plain and
`
`ordinary meaning—let alone why that meaning should be squeezed into such an uncomfortable
`
`construction. Nor does Microchip’s construction find any support in the patent. The claims
`
`themselves do not reference “top surfaces.” Nor does the specification. In fact, the specification
`
`uses the word “surfaces” only twice: once to describe how, in the existing art, titanium oxynitride
`
`may form on the surface of a titanium nitride film, and once to note that electrical testing can be
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`3
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`performed on a tungsten/titanium nitride stack “because the tungsten surface does not appreciably
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`harden and remains probable.” ’033 Patent, at 2:36–38, 3:55–57. Neither reference supports
`
`Microchip’s attempt to introduce a new “above the top surface” limitation.
`
`
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`Microchip claims that a POSITA “would have understood a ‘stack’ to refer to material
`
`arranged vertically on top of another,” ECF No. 38, at 9, but makes no attempt to show how that
`
`would require this Court to construe “over” with reference to a “top surface.” Likewise, Microchip
`
`makes no attempt to show how etching from the top down or figures showing a second film over
`
`a first film mean that “over” should be understood with reference to a “top surface.” See ECF No.
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`38, at 9. Finally, Microchip’s citation to extrinsic evidence describing how films may be deposited
`
`by attaching to a surface should carry no weight at all because that description is flatly contrary to
`
`the language in the specification, which expressly notes that “‘over’ . . . refer[s] to the relative
`
`placement of two materials that may or may not be directly in contact with each other.” ’033 Patent,
`
`at 2:18–20.
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`
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`Second, Microchip proposes that “film” be construed as a “thin layer of material having a
`
`thickness from top to bottom as its smallest dimension.” ECF No. 38, at 9. Here, Microchip’s
`
`proposed construction is entirely unsupported.
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`
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`Microchip argues that its construction is proper because the patent discloses a thin film.
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`But there’s no question that the films disclosed are quite thin. An Angstrom is equal to 0.1
`
`nanometers, or 10-10 meters. And the specification contemplates a titanium nitride film “deposited
`
`to a thickness of about 200 to 300 Angstroms [20 to 30 nanometers], preferably to a thickness of
`
`about 300 Angstroms.” ’033 Patent, at 3:1–4. So the question is not whether the film is thin; it’s
`
`whether the patent discloses a film whose thickness from top to bottom is its smallest dimension.
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`It does not. For that reason, Microchip cannot and does not point to anywhere in the claims, the
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`4
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`specification, or the prosecution history where the inventors disclosed that a film is not a film
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`unless it has a thickness from top to bottom as its smallest dimension. Instead, Microchip
`
`repeatedly emphasizes that a film is thin and then makes the unsupported leap that a POSITA
`
`would have understood a film to have a top-to-bottom thickness smaller than its other dimensions.
`
`
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`Nothing in the patent requires that a film be both wider and deeper than it is tall. The figures
`
`are not drawn to scale and do not purport to describe the relative height, depth, or width of the
`
`films. See ’033 Patent, at 2:5–6. Likewise, neither the claims nor the specification describes the
`
`depth or the width of the films, either in absolute terms or relative to height.
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`
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`Third, Microchip proposes to include the language “and the oxide layer.” But Microchip
`
`does not explain why it proposes adding additional limiting language to the claim. This
`
`unsupported proposal should be rejected.
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`4.
`
`“metal stack” / “the first film and the second film forming a metal
`stack”
`
`Claim Language
`
`HDSS’s Construction
`
`Microchip’s Construction
`
`“metal stack”
`(’033: 1, 8, 15)
`
`A “metal stack” is a stack
`consisting of two or more layers of
`metal (and no non-metal layers).
`
`The arrangement over the oxide
`layer of one metal film above the
`top surface of another metal film.1
`
`“the first film and
`the second film
`forming a metal
`stack”
`(’033: 1)
`
`No construction is necessary for
`the phrase “the first film and the
`second film forming a metal stack,”
`with “metal stack” construed as
`indicated.
`
`The arrangement over the oxide
`layer of the second metal film
`above the top surface of the first
`metal film.
`
`
`
`
`1 As discussed above, Microchip seeks to construe “over” as “above the top surface.” But here,
`Microchip uses both “over” and “above the top surface” in the same proposed construction.
`Microchip’s inconsistency highlights the awkwardness of its proposed construction for “over.”
`This is Microchip’s second attempt to import an unsupported “top surface” limitation into the
`claims, and it should be rejected for the same reasons given above.
`
`
`
`5
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 10 of 38
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`The parties agree that “metal stack” should be construed. However, HDSS’s proposed
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`construction tightly tracks the claims and specification, while Microchip’s construction attempts
`
`to import a reference to an oxide layer.
`
`
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`The meaning of “metal stack” is found in claims 1, 5, and 15, which explain that “the first
`
`[titanium nitride] film and the second [tungsten] film form a metal stack.” ’033 Patent, at 6:23–24.
`
`Microchip’s proposed construction would rewrite that language to include reference to an oxide
`
`layer. But the claims do not define a metal stack by giving its position relative to an oxide layer.
`
`They define a metal stack by explaining that it is a stack formed by two layers of metal. Similarly,
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`the specification repeatedly describes a metal stack with reference to two metal layers, but not with
`
`reference to an oxide layer. See, e.g., ’033 Patent, at 3:16–20 (“In one embodiment, the thickness
`
`of a metal stack comprising a film 104 of tungsten over a film 103 of titanium nitride is equal to
`
`or less than about 600 Angstroms.”), 3:35–37 (“The use of a metal stack comprising tungsten over
`
`titanium nitride in a local interconnect layer provides several advantages heretofore unrealized.”),
`
`3:47–49 (“A resist material may be formed over a tungsten/titanium nitride stack without having
`
`to deal with resist poisoning issues.”), 3:51–54 (“Because of tungsten’s stability, the sheet
`
`resistance and critical dimensions of a tungsten/titanium nitride stack do not significantly change
`
`during the fabrication process.”), 3:54–56 (“Electrical testing may also be performed on a
`
`tungsten/titanium nitride stack because the tungsten surface does not appreciably harden and
`
`remains probable.”).
`
`
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`Microchip mischaracterizes HDSS’s position as construing “metal stack” as a “stack of
`
`metal.” ECF No. 38, at 6. That is not HDSS’s proposed construction. Further, Microchip’s straw
`
`man is ironic considering Microchip also proposes using “metal” twice to define “metal stack.”
`
`HDSS’s proposed construction is that, in this context, a “stack” means two or more layers and that
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`a “metal stack” means all those layers are metal. This construction tracks how “metal stack” is
`
`used in claims 1, 5, and 15, which state that two metallic films form a metal stack. That “metal
`
`stack” might include more than two layers comes straight from the specification, which explains
`
`that the second metallic film would be deposited over the first, but that the two materials “may or
`
`may not be directly in contact with each other.” ’033 Patent, at 2:18–21. That all layers are metal
`
`comes straight from the claim language, which recites a “metal stack”—not a “stack,” not a “stack
`
`including metal,” and not a “stack comprising metal.”2
`
`5.
`
`“in-situ”
`
`Claim Language
`
`HDSS’s Construction
`
`Microchip’s Construction
`
`Using the same tool without a
`vacuum break in between steps.
`
`“in-situ”
`(’033: 2)
`
`Plain and ordinary meaning.
`
`Alternatively: Within the same
`physical vapor deposition system,
`which may have multiple
`chambers.
`
`Compromise proposal: Within the
`same physical vapor deposition
`system (which may have multiple
`chambers), without a vacuum break
`between steps.
`
`
`
`
`Claim 2 discloses the method of claim 1, but where “the first film and the second film are
`
`deposited in-situ.” ’033 Patent, at 6:5–6. From Microchip’s brief, it appears the parties’
`
`understandings of the term “in-situ” are not materially different. HDSS agrees that “in-situ”
`
`processing occurs in the same vacuum environment. And Microchip agrees that depositing films
`
`“in-situ” involves using the same system. HDSS maintains that this term is straightforward to a
`
`
`2 Microchip argues that HDSS’s proposed construction replaces “comprising” with “consisting
`of.” ECF No. 38, at 11–12. That’s simply wrong. The word “comprising” doesn’t appear in the
`term for construction as proposed by either party.
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`
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`7
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`POSITA and needs no construction. HDSS also maintains that its proposed alternative is a more
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`accurate construction. However, because the parties appear to agree, HDSS proposes the following
`
`compromise construction: “Within the same physical vapor deposition system (which may have
`
`multiple chambers), without a vacuum break between steps.” This construction tracks the only
`
`language in the patent explaining the meaning of “in-situ.” See ’033 Patent, at 3:21–25 (“In one
`
`embodiment, a film 104 of tungsten is deposited in-situ after the deposition of a film 103 of
`
`titanium nitride. That is, a film 104 of tungsten may be deposited using the same multi-chamber
`
`physical vapor deposition system used to deposit a film 103 of titanium nitride.”). It also accounts
`
`for the parties’ agreement that the process would occur in the same vacuum environment.
`
`B.
`
`Claim Terms for U.S. Patent No. 7,154,299
`
`1.
`
`Background
`
`
`
`The ’299 Patent is titled “Architecture for Programmable Logic Device,” and it discloses
`
`improvements to Field Programmable Gate Arrays (FPGAs). As the specification explains, FPGAs
`
`are general-purpose logic devices that can be configured to provide a wide array of logic functions.
`
`FPGAs comprise, internally, one or more Programmable Logic Blocks (PLBs), which can be
`
`interconnected. Within each PLB are logic circuit elements. What a PLB can do is limited by how
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`many logic circuit elements are available. The more logic circuit elements available, the greater
`
`the PLB’s capabilities. In certain applications, some PLBs might be underutilizing available logic
`
`circuit elements, while other PLBs have insufficient logic circuits available. In other words, one
`
`PLB might have more resources than it needs while others have too few. The ’299 Patent addresses
`
`this inefficiency by disclosing an architecture that enables PLBs to access resources on any other
`
`PLB on the device.
`
`
`
`Claim 1 of the ’299 Patent provides an exemplar and includes the disputed terms (as
`
`emphasized):
`
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`8
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`1. An improved programmable logic device architecture that provides more
`efficient utilization of resources by enabling access to a defined sequential
`circuit element in a routing domain associated with a programmable logic block
`from any other programmable logic block in the device, by incorporating a
`connecting means in the routing structure operable to selectively connect an
`input of the defined sequential circuit element in the routing domain to a first
`signal-pass node of a common interconnect matrix connecting all the
`programmable logic blocks together via no circuit element other than one or
`more switch elements and to simultaneously connect an output of the logic
`circuit element to a second signal-pass node of the common interconnect
`matrix.
`
`2.
`
`“via no circuit element other than one or more switch elements” / “via
`no circuit element other than one or more pass gates”
`
`Claim Language
`
`HDSS’s Construction
`
`Microchip’s Construction
`
`Using only wires and pass
`transistor switches.
`
`“via no circuit
`element other than
`one or more switch
`elements”
`(’299: 1)
`
`“via no circuit
`element other than
`one or more pass
`gates”
`(’299: 5, 7–9, 13, 14,
`16)
`
`A “circuit element” is a
`combinatorial-logic or sequential-
`logic element or combinations
`thereof.
`
`A “pass gate” is a controllable
`connection implemented using a
`transistor.
`
`Plain and ordinary meaning for
`Microchip’s proposed phrases,
`subject to those constructions.
`
`Microchip does not dispute HDSS’s proposed construction for “pass gate.” Consequently,
`
`it appears the parties’ disagreement concerning this phrase is limited to the meaning of “circuit
`
`element.” HDSS’s proposed construction tracks how “circuit element” is used in the patent, while
`
`Microchip’s proposed construction is untethered to intrinsic evidence.
`
`
`
`Microchip faults HDSS for proposing to define “circuit element” using the patent’s
`
`explanation of a “defined circuit element.” See ECF No. 38, at 14. But the patent does precisely
`
`the same thing, repeatedly using “circuit element” and “defined circuit element” interchangeably.
`
`See, e.g., ’299 Patent, Abstract (referring to “enabling access to defined circuit elements in the
`
`
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`9
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 14 of 38
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`domain of any Programmable Logic Block (PLB) from any other PLB in the device, by
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`incorporating a connecting means in the routing structure for selectively connecting the input or
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`output of the circuit element in the domain of the PLB to the common interconnect matrix
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`connecting all the PLBs together” (emphases added)); id. at 1:15–17 (describing “enabling access
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`to circuit elements in the domain of one Programmable Logic Block (PLB) from other PLBs”
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`(emphasis added)); id. at 1:58–60 (describing embodiment as “enabling access to defined circuit
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`elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the
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`device” (emphasis added)). And the specification explains that “defined circuit elements may be
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`combinatorial- or sequential-logic elements or combinations thereof.” Id. at 2:3–4. HDSS’s
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`proposed construction tracks that language.
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`
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`By contrast, Microchip’s proposed construction has no basis in the intrinsic evidence.
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`Neither “wires” nor “pass transistor switches” appear anywhere in the patent. Microchip argues
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`that switches and pass gates are types of circuit elements, but Microchip does not use “switches”
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`or “pass gates” to construe “circuit element.” See ECF No. 38, at 8. Instead, Microchip recites a
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`broad dictionary definition for “circuit element” (“a basic constituent part of a circuit, exclusive
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`of interconnections”), proposes the construction “using only wires and pass transistor switches,”
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`and fails to connect its proposed construction either to intrinsic or extrinsic evidence. Moreover,
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`Microchip’s proposed construction ignores Figure 8 (shown below), which diagrams an
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`embodiment of the invention and shows that the PLBs are connected not just by wires and switch
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`element 79-p (as Microchip’s proposed construction would have it), but also by Node M 80.
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`
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`10
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 15 of 38
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`
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`3.
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`“no circuit element”
`
`
`
`Claim Language
`
`HDSS’s Construction
`
`Microchip’s Construction
`
`“no circuit element”
`(’299: 1, 5, 7–9, 13,
`14, 16, 19, 23)
`
`A “circuit element” is a
`combinatorial-logic or sequential-
`logic element or combinations
`thereof.
`
`No electronic component other
`than wires.
`
`
`
`
`
`
`For the reasons above, the term “circuit element” should be defined as “a combinatorial-
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`logic or sequential-logic element or combinations thereof.” See ’299 Patent, at 2:3–4 (“The defined
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`circuit elements may be combinatorial- or sequential-logic elements or combinations thereof.”).
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`4.
`
`“the logic circuit element”
`
`Claim Language
`
`HDSS’s Construction
`
`Microchip’s Construction
`
`“the logic circuit
`element”
`(’299: 1)
`
`
`
`
`
`
`
`The sequential logic circuit
`element.
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`Alternatively, the defined
`sequential circuit element.
`
`Indefinite.
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`11
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 16 of 38
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`With respect to the term “the logic circuit element,” Microchip strains to find ambiguity
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`where none exists. That the claim uses the definite article “the” in reciting “the logic element”
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`means there must be antecedent basis for “the logic element.” See Automated Techs., Inc. v.
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`Microfil, LLC, 244 Fed. App’x 354, 359 (Fed. Cir. 2007). But the term’s meaning is apparent from
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`both the claims and the specification, so the patent informs those skilled in the art about the scope
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`of the invention with reasonable certainty.
`
`
`
`Beginning with the claim language, claim 1 refers to only one logic circuit element: “a
`
`defined sequential circuit element.” Then the claim discloses incorporating a connecting means
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`operable “to selectively connect an input of the defined sequential circuit element to a first signal-
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`pass node. . . and to simultaneously connect an output of the logic circuit element to a second
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`signal-pass node.” ’299 Patent, at 5:31–40. This parallel structure (shown side-by-side in the table
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`below) makes clear that it is this “defined sequential circuit element” to which “the logic circuit
`
`element” refers.
`
`
`
`
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`The specification supports this understanding. In summarizing the invention, the
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`specification explains, “At least one of the defined logic circuit elements is typically a sequential
`
`logic-circuit element.” ’299 Patent, at 2:5–6. And, as Microchip correctly illustrates, Figure 8
`
`(shown below) shows a flip-flop 74, a sequential logic circuit element, connected to Node M 80,
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`which is part of the common interconnect matrix.
`
`
`
`12
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`by incorporating a connecting means in the routing structure operable to . . .
`
`selectively connect
`
`and to simultaneously connect
`
`an input of
`
`an output of
`
`the defined sequential circuit
`element in the routing domain
`
`the logic circuit element
`
`to a first signal-pass node of a
`common interconnect matrix . . .
`
`to a second signal-pass node of the
`common interconnect matrix.
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`Case 6:20-cv-01092-ADA Document 39 Filed 09/10/21 Page 17 of 38
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`The prosecution history confirms this understanding. During prosecution, claims 1 and 8
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`(now claim 7) were simultaneously amended to add “[connect/connecting] an output of the logic
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`circuit element to a second signal-pass node of the common interconnect matrix.” Amendment and
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`Response dated January 30, 2006, at 2–3 (Shih Decl. Ex. A). Prior to amendment, “the logic circuit
`
`element” had already been used in claim 8 to refer to the antecedent “defined sequential logic
`
`circuit element,” so it is clear that “the logic circuit element” in claim 8 referred to “defined
`
`sequential logic circuit element.” That the “logic circuit element” language was added to claims 1
`
`and 8 simultaneously indicates that the language in claim 1 also refers to a sequential logic circuit
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`element.
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`
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`Microchip attempts to manufacture an ambiguity by suggesting that “the logic circuit
`
`element” may refer to a different logic element: the logic block providing signal A1 72, which is
`
`also connected to Node M 80. But “the logic circuit element” cannot refer to a logic block because
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`the specification and claims consistently distinguish between logic circuit elements and logic
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`blocks. See, e.g., ’299 Patent, at 1:27–28 (“each PLB [programmable logic block] includes logic-
`
`
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`13
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`Case 6:20-cv