United States Patent [19]
`Tanabe
`
`[54] VOLTAGE STEPDOWN CIRCUIT
`INCLUDING A VOLTAGE DIVIDER
`
`[75]
`
`Inventor: Akira Tanabe, Tokyo, Japan
`
`[73] Assignee: NEC Corporation, Tokyo, Japan
`
`[21] Appl. No.: 194,330
`
`[22] Filed:
`
`Feb.8, 1994
`
`[30]
`
`Foreign Application Priority Data
`
`Feb. 10, 1993
`
`[JP]
`
`Japan .................................... 5-022232
`
`Int. Cl.6
`....................................................... H03K 3/01
`[51]
`[52] U.S. Cl . .......................... 327/530; 327/306; 327/333;
`327/544; 327/546
`[58] Field of Search .............................. 307/296.1, 296.2,
`307/296.3, 296.4, 296.5, 296.6, 353, 532,
`350; 328/127; 327/530, 535, 541, 544,
`546,306,333
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,061,929
`4,754,226
`4,868,908
`5,168,174
`5,281,860
`5,304,859
`5,309,399
`5,341,050
`5,347,170
`
`12/1977 Asano .................................. 307 /296.1
`6/1988 Lusignan et al ........................ 328/127
`9/1989 Pless et al ............................... 323/267
`12/1992 Naso et al ............................ 307/296.6
`1/1994 Krenik et al ............................ 328/127
`4/1994 Arimoto ............................... 307/296.2
`5/1994 Murotani .............................. 307/296.1
`8/1994 Mellissinos et al. ................... 328/127
`9/1994 Hayakawa et al ................... 307/296.1
`
`FOREIGN PATENT DOCUMENTS
`
`0492538A2 12/1991 European Pat. Off ..
`
`I 1111111111111111 11111 11111111111111111111111111111111111 111111111111111111
`US005457421A
`[11] Patent Number:
`[ 45] Date of Patent:
`
`5,457,421
`Oct. 10, 1995
`
`2553545
`63-121467
`
`4/1985 France ................................... 328/127
`5/1988
`Japan .
`
`OTHER PUBLICATIONS
`
`T. Takeshima et al.; "A 55-ns 16-Mb DRAM with Built-in
`Self-Test Function Using Microprogram ROM"; IEEE Jour(cid:173)
`nal of Solid-State Circuits, vol. 25, No. 4, Aug. 1990, pp.
`903-911.
`
`Primary Examiner-Timothy P. Callahan
`Assistant Examiner-Kenneth B. Wells
`Attorney, Agent, or Finn-Whitham, Curtis, Whitham &
`McGinn
`
`[57]
`
`ABSTRACT
`
`A voltage step-down circuit to be built in a highly integrated
`semiconductor IC chip, including a voltage divider and a
`voltage comparator. A divided output voltage V 1NT of the
`voltage divider and a comparison reference voltage V REF are
`applied to respective input terminals (-) and (+) of the
`voltage comparator. An output signal of the voltage com(cid:173)
`parator is supplied to a control signal generator section of the
`voltage divider to generate control pulses and to control the
`connection of capacitors of a voltage divider section of the
`voltage divider with the control pulses so as to supply the
`divided output voltage V1NTto a load circuit. In this case, the
`capacitors are used as a voltage divider for generating a
`voltage for an internal circuit from an external power source
`voltage. Thus, power loss can be reduced and utilization
`efficiency of the capacitors is raised. Hence, the voltage
`step-down circuit is suitable for highly integrated semicon(cid:173)
`ductor IC chip.
`
`15 Claims, 15 Drawing Sheets
`
`1 Oa
`1 O
`,1
`,- , ----------- ' - - - - - ' - - - - - ,
`VOLTAGE DROP CIRCUIT
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`VOLTAGE DIVIDER---;--- -i 1 13
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 1 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 1 of 15
`
`5,457,421
`
`F I G. 1
`PRIOR ART
`
`123
`VREF
`
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 2 of 28
`
`

`

`U.S. Patent
`
`Oct. 1 O, 1995
`
`Sheet 2 of 15
`
`5,457,421
`
`FI G. 3a
`
`FRIOR ART
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 3 of 28
`
`

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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 4 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 4 of 15
`
`5,457,421
`
`FI G. 4a
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 5 of 28
`
`

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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 6 of 28
`
`

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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 7 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 7 of 15
`
`5,457,421
`
`F I G. 6a
`
`3
`
`VOLTAGE
`
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 8 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 8 of 15
`
`5,457,421
`
`FI G. 7a
`
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 9 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 9 of 15
`
`5,457,421
`
`FI G. 8a
`
`DIVIDER
`
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`
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 10 of 28
`
`

`

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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 11 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 11 of 15
`
`5,457,421
`
`F I G. 10
`
`VREF ------
`LEVEL
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 12 of 28
`
`

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`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 12 of 15
`
`5,457,421
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 13 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 13 of 15
`
`5,457,421
`
`F I G. 12
`
`VREF
`LEVEL
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 14 of 28
`
`

`

`I
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`
`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 14 of 15
`
`5,457,421
`
`F I G. 13 a
`,' 100
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`VOLTAGE DROP CIRCUIT
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 15 of 28
`
`

`

`U.S. Patent
`
`Oct. 10, 1995
`
`Sheet 15 of 15
`
`5,457,421
`
`F I G. 14
`
`110
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 16 of 28
`
`

`

`5,457,421
`
`1
`VOLTAGE STEPDOWN CIRCUIT
`INCLUDING A VOLTAGE DIVIDER
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a voltage drop circuit
`including a voltage divider circuit which uses capacitors,
`and more particularly to a voltage drop circuit of a low
`consumption power type of this kind suitable to be built in
`a large capacity semiconductor dynamic random access
`memory (DRAM) chip.
`
`DESCRIPTION OF THE RELATED ART
`
`5
`
`2
`and the second switch Sl32 with the earth terminal 136, and
`a fifth switch S135 for selectively coupling the connection
`point between the second switch S132 and the second
`capacitor C132 with the connection point between the third
`switch Sl33 and the third capacitor Cs, A partial output
`voltage V Dn3 obtained at the connection point between the
`third switch S133 and the third capacitor Cs is applied to the
`source electrode of the output PET 132. An ouput voltage
`V DD2 obtained from the drain electrode of the output PET
`10 132 is applied to the another input terminal ( +) of the
`comparator circuit 131 and a low voltage operational load
`circuit Z via an output terminal 133.
`In this case, the first and second switches S131 and Sl32
`and the third, fourth and fifth switches Sl33, Sl34 and S135
`15 are opened or closed in response to first and second control
`signals <I>l and <I>2, respectively.
`Next, the operation of the conventional voltage drop
`circuit 130 will now be described with reference to FIGS. 3a
`and 3b which show an equivalent circuit of the voltage
`20 divider circuit 134 and its operational waveform view,
`respectively.
`When the first control signal <I> 1 is a high level for the first
`and second switches Sl31 and Sl32 to be on and the second
`control signal <I>2 is a low level for the third, fourth and fifth
`25 switches S133, Sl34 and S135 to be off (the state shown in
`FIG. 2), the first and second capacitors C131 and C132 are
`connected in series between the power source voltage V DDI
`and the earth voltage GND and become a charged state (a
`charge in FIG. 3a). At this time, to the output PET 132, the
`30 partial output voltage V DD3 corresponding to a holding
`capacity of the third capacitor Cs is supplied and the output
`voltage V vD2 of the output PET 132 is fed to the load circuit
`Z via the output terminal 133.
`Next, when the first control signal <I>l is the low level with
`the first and second switches S131 and S132 to be off and the
`second control signal <I>2 is the high level with the third,
`fourth and fifth switches S133, Sl34 and S135 to be on, the
`first and second capacitors C131 and C132 are cut from the
`power source voltage V DDI• and the first, second and third
`40 capacitors C131, Cl32 and Cs are connected in parallel with
`each other (a discharge in FIG. 3a), and the total capacity of
`the first, second and third capacitors C131, C132 and Cs,
`which is the maximum voltage V Dv3 max is inserted
`between the source electrode of the output PET 132 and the
`45 earth voltage point 136.
`In the high level period of the second control signal <I>2,
`the output voltage V Dv2 of the PET 132 drops from the
`whole capacity V 003 max, that is, (½)·V nm to the level of
`(½)·V vm-L'i V with the passage of discharge time, and in the
`high level period of the first control signal <I>l, including the
`whole switch non-continuity period, since the output voltage
`V 002 becomes only the holding capacity of the third capaci(cid:173)
`tor Cs, its level further drops from the (½)-V Dm-L'i V (FIG.
`3b).
`In the first conventional voltage drop circuit shown in
`FIG. 1, a power loss P (V vsxlvs) due to a voltage V vs and
`a current Ins between the source and drain electrodes of the
`PET 122 is caused to bring about a rise in temperature of the
`IC chip constituting the load circuit Z.
`Similarly, in the second conventional voltage drop circuit
`shown in FIG. 2, a power loss between the source and drain
`electrodes of the PET 182 arises in the same manner as the
`first conventional voltage drop circuit to inevitably cause the
`temperature rise of the IC chip and also it is impossible to
`carry out a simultaneous charging of the first to third
`capacitors C131, C132 and Cs. Hence, the utilization effi-
`
`35
`
`A semiconductor IC chip such as a large capacity DRAM
`has a built-in voltage drop circuit for reducing power source
`voltage so as to operate internal circuits such as a memory
`cell array at a low voltage. A typical example of a voltage
`drop circuit of this kind in the prior art has a structure of a
`so-called series regulator configuration, as disclosed in a
`paper of the IEEE Journal of Solid-state Circuits, Vol. 25,
`No. 4, pp. 908-911, 1990.
`The conventional voltage drop circuit 120 is provided
`with a voltage comparator 121 and a p-type PET (field effect
`transistor) 122 to input an output of the voltage comparator
`121 at its gate electrode, as shown in FIG. 1. A comparison
`reference voltage V REF is applied to one input terminal (-)
`of the voltage comparator 121 and a power source voltage
`V DD is supplied to the source electrode of the PET 122 via
`a power source terminal 124. And a voltage VINT output
`from the drain electrode of the PET 122 is fed to another
`input terminal ( +) of the voltage comparator 121 and an
`output terminal 125.
`Between the output terminal 125 and an earth voltage
`point, a load circuit Z such as a memory circuit of the
`aforementioned semiconductor IC chip with a built-in volt(cid:173)
`age drop circuit 120 is connected. By applying the compari(cid:173)
`son reference voltage V REF and the output voltage VINT to
`the respective input terminals (-) and (+) of the voltage
`comparator 121, the circuit is controlled so that a current
`flowing in the PET 122 may increase when the output
`voltage VINT drops rather than the comparison reference
`voltage V REF> so as to obtain a low voltage supply circuit to
`the load circuit Z.
`Another example of a conventional voltage drop circuit is
`disclosed in Japanese Patent Laid-Open No. Sho 63-121467,
`as shown in FIG. 2. In this case, as shown in FIG. 2, the
`voltage drop circuit 130 has the above-described series
`regulator configuration. That is, in addition to a combination 50
`of a comparator circuit 131 and an output PET 132 for
`inputting its output at the gate electrode, there is provided a
`capacitor voltage divider circuit 134 inserted between a
`power source terminal 135 of a power source voltage V nm
`and the source electrode of the output PET 132 and one input 55
`terminal (-) of the comparator circuit 131 is connected to the
`earth voltage point. The voltage divider circuit 134 is
`comprised of one series connection circuit which includes a
`first capacitor C131 coupled with the power source terminal
`135 via a first switch Sl31, a second switch S132 and a 60
`second capacitor C132 connected to an earth terminal 136 of
`an earth voltage GND, another series connection circuit
`which includes a third switch S133 coupled with a connec(cid:173)
`tion point between the first switch S131 and the first capaci-
`tor Cl31 and a third capacitor Cs connected to the earth 65
`terminal 136, a fourth switch S134 for selectively connect(cid:173)
`ing the connection point between the first capacitor Cl31
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 17 of 28
`
`

`

`5,457,421
`
`3
`ciency of the capacitors, that is, the utilization efficiency of
`the IC chip surface area is low and it is hard to improve the
`integration degree.
`
`SUMMARY OF THE INVENTION
`
`It is therefore an object of the present invention to provide
`a voltage drop circuit with a capacitor voltage divider circuit
`base in view of the aforementioned problems of the prior art,
`which is capable of preventing a consumption power loss
`and heat generation and stabilizing divided output voltages
`and which is suitable for high integration degree of a
`semiconductor IC chip.
`In accordance with one aspect of the present invention,
`there is provided a voltage drop circuit to be built in a 15
`semiconductor integrated circuit chip including a first ter(cid:173)
`minal for inputting an external power source voltage, a
`second terminal to be maintained to a reference voltage, and
`an internal circuit having a predetermined function, con(cid:173)
`nected to the first and second terminals, the voltage drop 20
`circuit dropping the external power source voltage and
`applying a dropped voltage to the internal circuit, compris(cid:173)
`ing: (A) a voltage divider circuit including: (a) first and
`second capacitors having an equal capacity; (b) two pairs of
`first switch elements which are inserted between one elec- 25
`trodes of the first and second capacitors and the first terminal
`and between another electrodes of the first and second
`capacitors and the second terminal and which are selectively
`conducted in response to a control signal; (c) a pair of
`second switch elements which are inserted between one 30
`electrode of the first capacitor and another electrode of the
`second capacitor and between another electrode of the first
`capacitor and one electrode of the second capacitor and
`which are selectively conducted in response to the control
`signal; (d) a pair of third switch elements which are inserted 35
`in series between one electrode of the first capacitor and one
`electrode of the second capacitor and are selectively con(cid:173)
`ducted in response to the control signal; (e) an output
`terminal connected to a connection point between the pair of
`third switch elements and to the internal circuit; and (f) 40
`control signal generating means for generating the control
`signals for controlling conduction states of the first, second
`and third switch elements so that the first and second
`capacitors are alternately charged by the external power
`source voltage supplied from the first terminal and are 45
`alternately discharged to the internal circuit from the output
`terminal in a complementary manner to the charging; and
`(B) connection control signal generating means for gener(cid:173)
`ating a connection control signal for controlling the genera(cid:173)
`tion of the control signals in the control signal generating 50
`means in response to a comparison result between a dis(cid:173)
`charge output to the internal circuit and a predetermined
`comparison reference voltage.
`In the voltage drop circuit, the connection control signal
`generating means includes voltage comparator means hav(cid:173)
`ing first and second input terminals; voltage dividing means
`connected to the first terminal for dividing the external
`power source voltage to generate the comparison reference
`voltage: and wiring means for connecting the first input
`terminal of the voltage comparator means to the output
`terminal and the second input terminal of the voltage com(cid:173)
`parator means to the voltage dividing means.
`The control signals are constructed so as not to overlap in
`front and rear edge portions of the alternate charge and 65
`discharge periods of the first and second capacitors.
`The internal circuit is a large capacity dynamic random
`
`4
`access memory including a memory cell array for inputting
`a precharge voltage in response to a precharge control pulse
`synchronizing with a front edge of a read cycle and the
`output terminal is connected to a sense amplifier of the
`5 dynamic random access memory. A fourth switch element is
`inserted between the first terminal and the output terminal
`and is selectively conducted in response to the precharge
`control pulse.
`The internal circuit is a circuit of a large capacity dynamic
`10 random access memory which has a heavy-load operational
`period operable by a relatively heavy-current and a light(cid:173)
`load operational period operable by a relatively light-current
`and which is tends to vary an output voltage on the output
`terminal. A supplementary voltage comparator means com(cid:173)
`pares the output voltage with a supplementary comparison
`reference voltage lower than the comparison reference volt-
`age, and a switch element is inserted between the first
`terminal and the output terminal and is selectively conducted
`in response to an output of the supplementary voltage
`comparator means.
`In the voltage drop circuit, a frequency counter is con(cid:173)
`nected to the output of the supplementary voltage compara(cid:173)
`tor means so as to detect the heavy-load operational period
`and the light-load operational period and detects repeat
`frequency of a pulse output appearing on the output of the
`supplementary voltage comparator means, and controller
`controls the supplementary voltage comparator means to
`selectively become an operational state in response to the
`output of the frequency counter and to cause the output to be
`supplied to the switch element.
`The control signal generating means includes a first
`bistable circuit for inputting the output of the voltage
`comparator means at one of a pair of input terminals, a
`second bistable circuit which inputs a pair of outputs of the
`first bistable circuit at a pair of input terminals and supplies
`its output as the connection control signal to the voltage
`dividing means and a logic circuit which gives a delay to the
`connection control signal and executes a pulse width con(cid:173)
`version to supply a pulse width converted signal to another
`of the pair of input terminals of the first bistable circuit.
`In the voltage drop circuit, at least one delay circuit is
`connected to an output of the voltage comparator means and
`outputs a delay connection control signal for giving a
`predetermined delay to the connection control signal and at
`least one subordinate voltage divider circuit has substan(cid:173)
`tially the same construction as the voltage divider circuit,
`including first and second terminals connected to the corre(cid:173)
`sponding first and second output terminals of the voltage
`divider circuit, and which inputs the delay connection con(cid:173)
`trol signal by control signal generating means corresponding
`to the control signal generating means of the voltage divider
`circuit.
`In the voltage drop circuit, three delay circuits and three
`55 subordinate voltage divider circuits can be provided.
`In the voltage drop circuit of the present invention, the
`voltage of the external power source voltage supplied to the
`semiconductor IC chip is divided by the voltage divider
`circuit of the capacitors to obtain a divided output voltage to
`60 be supplied to the internal circuit, and there is no power loss.
`Hence, there is no temperature increase of the IC chip.
`Further, the charge and discharge of a plurality of capacitors
`constituting the voltage divider circuit can be executed at the
`same time and thus the utilization efficiency of the capacitors
`is raised. As a result, the occupying area of the capacitors on
`the IC chip is reduced and this contributes to improvement
`of the integration degree of the whole IC chip.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1041
`Page 18 of 28
`
`

`

`5,457,421
`
`5
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The objects, features and advantages of the present inven(cid:173)
`tion will become more apparent from the consideration of
`the following detailed description, taken in conjunction with
`the accompanying drawings, in which:
`FIG. 1 is a block diagram of one conventional voltage
`drop circuit;
`FIG. 2 is a block diagram of another conventional voltage
`drop circuit;
`FIG. 3a is a circuit diagram showing an equivalent circuit
`of the conventional circuit shown in FIG. 2 and FIG. 3b is
`a time chart for explaining an operation of the conventional
`circuit shown in FIG. 2;
`FIG. 4a is a block diagram of a first embodiment of a
`voltage drop circuit according to the present invention and
`'FIG. 4b is a block diagram of a control signal generator used
`in the circuit shown in FIG. 4a;
`FIG. Sa is a circuit diagram showing an equivalent circuit
`of a voltage divider constituting a part of the circuit shown
`in FIG. 4a and FIG. Sb is a time chart for explaining an
`operation of the circuit shown in FIG. 4a;
`FIG. 6a is a block diagram of a second embodiment of a
`voltage drop circuit according to the present invention and 25
`FIG. 6b is a time chart for explaining an operation of the
`circuit shown in FIG. 6a:
`FIG. 1a is a block diagram of a third embodiment of a
`voltage drop circuit according to the present invention and
`FIG. 1b is a time chart for explaining a operation of the 30
`circuit shown in FIG. 7a;
`FIG. 8a is a block diagram of a fourth embodiment of a
`voltage drop circuit according to the present invention and
`FIG. Sb is a time chart for explaining an operation of the
`circuit shown in FIG. Sa;
`FIG. 9 is a block diagram of a fifth emvbodiment of a
`voltage drop circuit according to the present invention;
`FIG. 10 is a time chart for explaining an operation of the
`circuit shown in FIG. 9;
`FIG. 11 is a block diagram of a sixth embodiment of a
`voltage drop circuit according to the present invention;
`FIG. 12 is a time chart for explaining an operation of the
`circuit shown in FIG. 11;
`FIG. 13a is a block diagram of a seventh embodiment of 45
`a voltage drop circuit according to the present invention and
`FIG. 13b is a time chart for explaining an operation of the
`circuit shown in FIG. 13a; and
`FIG. 14 is a schematic diagram showing a rough arrange(cid:173)
`ment of the fifth embodiment of the vo