Preliminary Information
`
`TM
`
`AMD Athlon
`Processor
`Data Sheet
`
`Rev: G
`Publication # 21016
`Issue Date: December 1999
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 1 of 106
`
`

`

`Preliminary Information
`
`© 1999 Advanced Micro Devices, Inc. All rights reserved.
`The contents of this document are provided in connection with Advanced
`Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
`warranties with respect to the accuracy or completeness of the contents of
`this publication and reserves the right to make changes to specifications and
`product descriptions at any time without notice. No license, whether express,
`implied, arising by estoppel or otherwise, to any intellectual property rights
`is granted by this publication. Except as set forth in AMD’s Standard Terms
`and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
`any express or implied warranty, relating to its products including, but not
`limited to, the implied warranty of merchantability, fitness for a particular
`purpose, or infringement of any intellectual property right.
`
`AMD’s products are not designed, intended, authorized or warranted for use
`as components in systems intended for surgical implant into the body, or in
`other applications intended to support or sustain life, or in any other applica-
`tion in which the failure of AMD’s product could create a situation where per-
`sonal injury, death, or severe property or environmental damage may occur.
`AMD reserves the right to discontinue or make changes to its products at any
`time without notice.
`
`Trademarks
`AMD, the AMD logo, AMD Athlon, and combinations thereof, 3DNow!, AMD-751, and AMD-756 are trademarks
`of Advanced Micro Devices, Inc.
`
`MMX is a trademark of Intel Corporation.
`
`Alpha is a trademark of Digital Equipment Corporation.
`
`Other product names used in this publication are for identification purposes only and may be trademarks of
`their respective companies.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 2 of 106
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`

`

`Preliminary Information
`
`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Contents
`
`Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
`
`About This Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
`
`Part One
`
`2
`
`3
`4
`
`5
`6
`
`3
`AMD Athlon™ Processor Family
`1
`Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
`1.1
`AMD Athlon™ Processor Microarchitecture Summary . . . . . 2
`Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
`2.1
`Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
`2.2
`Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
`2.3
`AMD Athlon™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 5
`Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
`Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
`4.1
`Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
`Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
`Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
`Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
`Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 13
`Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
`Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
`Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`6.1
`The AMD Athlon™ System Bus . . . . . . . . . . . . . . . . . . . . . . . 23
`6.2
`Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`Clock Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
`Voltage Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`Frequency Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`OD Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`CLKFWD Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`SYSCLK, SYSCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`6.7
`Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`6.8
`Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`6.9
`6.10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`6.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`iii
`
`4.2
`
`6.3
`6.4
`6.5
`6.6
`
`Contents
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`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Preliminary Information
`
`7
`
`8
`
`Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`7.1
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`7.2
`Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`7.3
`AMD Athlon™ Processor Card-Edge Signal Listing . . . . . . . 41
`Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`Standard AMD Athlon™ Processor Products. . . . . . . . . . . . . . . . . . . 49
`
`Part Two
`
`10
`
`11
`12
`13
`14
`
`51
`AMD Athlon Processor Model 2
`9
`Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`9.1
`AMD Athlon™ Processor Microarchitecture Summary . . . . 54
`Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`10.2
`Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`10.3 AMD Athlon™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . 57
`Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
`Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`14.1
`The AMD Athlon™ System Bus . . . . . . . . . . . . . . . . . . . . . . . 67
`14.2
`Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`Clock Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`14.3 Voltage Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`14.4
`Frequency Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`14.5 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`14.6
`Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`14.7 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
`14.8 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
`14.9
`Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
`14.10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`14.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`15 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`15.1
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`15.2 AMD Athlon™ Processor Card-Edge Signal Listing . . . . . . . 76
`Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`Standard AMD Athlon™ Processor Products. . . . . . . . . . . . . . . . . . . 83
`Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . 85
`
`16
`
`iv
`
`Contents
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
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`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`List of Figures
`
`Part One
`
`Figure 1.
`
`Typical AMD Athlon™ Processor System Block Diagram . . . . . 3
`
`Figure 2.
`
`Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
`
`Figure 3. AMD Athlon Processor Power Management States . . . . . . . . . 11
`
`Figure 4.
`
`Example System Bus Disconnection Sequence . . . . . . . . . . . . . 15
`
`Figure 5.
`
`Exiting Stop Grant State/Bus Reconnection Sequence . . . . . . 16
`
`Figure 6.
`
`System Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
`
`Figure 7.
`
`Processor Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`
`Figure 8.
`
`Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
`
`Figure 9. AMD Athlon Processor Module Dimensions—Front View . . . 36
`
`Figure 10. AMD Athlon Processor Module Dimensions—Plate Side
`View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
`
`Figure 11. AMD Athlon Processor Module Dimensions—Side View . . . . 38
`
`Figure 12. AMD Athlon Processor Module Dimensions—Edge View. . . . 38
`
`Figure 13. Card Edge Dimensions—Thermal Plate Side View . . . . . . . . . 39
`
`Figure 14. Card Edge Dimensions (Detail) . . . . . . . . . . . . . . . . . . . . . . . . . 40
`
`Part Two
`
`Figure 15. Typical AMD Athlon Processor System Block Diagram. . . . . . 55
`
`Figure 16. Logic Symbol Diagram for AMD Athlon Processor Model 2 . . 61
`
`List of Figures
`
`vii
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`AMD Athlon™ Processor Data Sheet
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`21016G/0—December 1999
`
`Preliminary Information
`
`viii
`
`List of Figures
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`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`List of Tables
`
`Part One
`
`Table 1.
`Table 2.
`Table 3.
`Table 4.
`
`Pin-Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
`AMD Athlon™ System Bus and Legacy Interface Signals . . . . . 6
`AMD Athlon Processor Power Management States . . . . . . . . . 14
`AMD Athlon Processor Special Cycle Command
`Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
`AMD Athlon Processor Interface Signal Groupings . . . . . . . . . 24
`Table 5.
`Source-Synchronous Clock Signal Groups . . . . . . . . . . . . . . . . . 24
`Table 6.
`Voltage ID Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`Table 7.
`Signal and Clock Layout and Termination Requirements. . . . 26
`Table 8.
`Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`Table 9.
`Table 10. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`Table 11.
`Typical and Maximum Power Dissipation . . . . . . . . . . . . . . . . . 29
`Table 12. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`Table 13. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Table 14. AMD Athlon Processor Module Dimensions . . . . . . . . . . . . . . . 35
`Table 15. Notes for Dimension Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`Table 16. AMD Athlon Processor Signals Ordered by Pin Number. . . . . 41
`Table 17. AMD Athlon Processor Signals Ordered by Pin Name. . . . . . . 44
`Table 18. AMD Athlon Processor Signals Ordered by
`Physical Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`Table 19. Valid Ordering Part Number Combinations . . . . . . . . . . . . . . . 49
`
`Part Two
`
`Pin-Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Table 20.
`Table 21. AMD Athlon System Bus and Legacy Interface Signals. . . . . . 58
`Table 22. AMD Athlon Processor Interface Signal Groupings . . . . . . . . . 68
`Table 23.
`Source-Synchronous Clock Signal Groups . . . . . . . . . . . . . . . . . 68
`Table 24. Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
`Table 25. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
`Table 26.
`Typical and Maximum Power Dissipation . . . . . . . . . . . . . . . . . 71
`Table 27. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`
`List of Tables
`
`ix
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`AMD Athlon™ Processor Data Sheet
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`21016G/0—December 1999
`
`Preliminary Information
`
`Table 28. AMD Athlon Processor Signals Ordered by Pin Number. . . . . 76
`Table 29. AMD Athlon Processor Signals Ordered by Pin Name. . . . . . . 79
`Table 30. AMD Athlon Processor Signals Ordered by Physical
`Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
`Table 31. Valid Ordering Part Number Combinations . . . . . . . . . . . . . . . 83
`Table 32. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
`Table 33. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
`
`x
`
`List of Tables
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`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`Revision History
`
`Date
`August 1999
`
`Rev
`D
`
`August 1999
`
`October 1999
`
`E
`
`F
`
`December 1999
`
`G
`
`Description
`
`Initial public release
`Revised VCC_CORE minimum value from 1.4V to 1.5V in Table 9, “Operating Ranges,” on page 28.
`Revised information in Table 10, “Absolute Ratings,” on page 28.
`Revised information in Table 11, “Typical and Maximum Power Dissipation (Model 1),” on page 29.
`Added the 700 MHz AMD Athlon™ processor to Table 11, “Typical and Maximum Power
`Dissipation (Model 1),” on page 29 and Table 19, “Valid Ordering Part Number Combinations,” on
`page 49.
`Revised Table 12, “DC Characteristics (Model 1),” on page 30 and Table 13, “AC Characteristics,” on
`page 32.
`Divided book into Part One and Part Two. Part One provides information about the AMD Athlon™
`processor family (Model 1 and Model 2), and Part Two provides information specific to the
`AMD Athlon processor Model 2 (0.18-micron process technology).
`Revisions to Part One:
`In Chapter 6, “Electrical Data” on page 23:
`I Expanded information in the “Termination” section starting on page 26, including the addition
`of Table 8, “Signal and Clock Layout and Termination Requirements”.
`I Revised maximum rating in Table 10, “Absolute Ratings,” on page 28.
`I Revised Stop Grant values in Table 11, “Typical and Maximum Power Dissipation (Model 1),” on
`page 29.
`I Added ICC values and notes 7 and 8 to Table 12, “DC Characteristics (Model 1),” on page 30.
`In Chapter 7, “Mechanical Data” on page 35, added # to SCHECK[2]# and SCHECK[7]# in signal
`Tables 16, 17, and 18 starting on page 41.
`
`Revision History
`
`xi
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`AMD Athlon™ Processor Data Sheet
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`21016G/0—December 1999
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`Preliminary Information
`
`xii
`
`Revision History
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`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`About This Data Sheet
`
`The AMD Athlon™ processor data sheet supports the Model 1 and Model 2 versions
`of the AMD Athlon processor family. Model 1 refers to the AMD Athlon
`manufactured in the 0.25-micron process technology and Model 2 refers to the
`AMD Athlon manufactured in the 0.18-micron process technology. The data sheet is
`divided into two parts. Part One (chapters 1–8) contains information that pertains to
`the entire AMD Athlon processor family and information specific to the Model 1. Part
`Two (chapters 9–16) contains information regarding new specifications and
`differences that pertain only to Model 2 as compared to Model 1.
`
`About This Data Sheet
`
`1
`
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`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Preliminary Information
`
`2
`
`About This Data Sheet
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
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`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`Part One
`
`AMD Athlon™
`Processor Family
`
`The AMD Athlon processor data sheet supports the Model 1
`and Model 2 versions of the AMD Athlon processor family.
`Model 1 refers to the AMD Athlon manufactured with
`0.25-micron process technology and Model 2 refers to the
`AMD A t hl o n m a nufa ct u re d wit h 0 .1 8 -mi c ron p ro ce s s
`technology. Part One (chapters 1–8) contains information that
`pertains to the entire AMD Athlon desktop family and
`information specific to Model 1. For information about Model 2,
`see Part Two, “AMD Athlon™ Processor Model 2” on page 51.
`
`Part One
`
`AMD Athlon™ Processor Family
`
`3
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`AMD Athlon™ Processor Data Sheet
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`21016G/0—December 1999
`
`Preliminary Information
`
`4
`
`AMD Athlon™ Processor Family
`
`Part One
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`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`1
`
`Overview
`
`The AMD Athlon™ processor powers the next generation in
`computing platforms, delivering the ultimate performance for
`cutting-edge applications and an unprecedented computing
`experience.
`
`The AMD Athlon processor is the first member of a new family
`of seventh-generation AMD processors designed to meet the
`computation-intensive requirements of cutting-edge software
`applications running on high-performance desktop systems,
`workstations, and servers.
`
`The AMD Athlon processor is the world’s most powerful x86
`processor, delivering the highest integer, floating-point and 3D
`multimedia performance for applications running on x86
`system platforms. The AMD Athlon provides industry-leading
`processing power for cutting-edge software applications,
`including digital content creation, digital photo editing, digital
`video, image compression, video encoding for streaming over
`t h e i n t e r n e t , s o f t DV D, c o m m e rc i a l 3 D m o d e l i n g ,
`workstation-class computer-aided design (CAD), commercial
`desktop publishing, and speech recognition. It also offers the
`scalability and ‘peace-of-mind’ reliability that IT managers and
`business users require for enterprise computing.
`
`The AMD Athlon processor features the industry's first
`seventh-generation x86 microarchitecture, which is designed to
`support the growing processor and system bandwidth
`requirements of emerging software, graphics, I/O, and memory
`technologies. The AMD Athlon processor's high-speed
`execution core includes multiple x86 instruction decoders, a
`dual-ported 128-Kbyte split level-one (L1) cache, three
`independent integer pipelines, three address calculation
`pipelines, and the x86 industry's first superscalar, fully
`pipelined, out-of-order, three-way floating-point engine. The
`floating-point engine is capable of delivering 2.4 gigaflops
`(Gflops) of single-precision and more than 1 Gflop of
`double-precision floating-point results at 600 MHz, for superior
`performance on numerically complex applications.
`
`The AMD Athlon processor microarchitecture incorporates
`enhanced 3DNow!™ technology, a high-performance cache
`architecture, and a 200-MHz, 1.6-Gigabyte per second system
`bus—the first bus of its kind for x86 system platforms. Based on
`1
`Overview
`
`Chapter 1
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 15 of 106
`
`

`

`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Preliminary Information
`
`the Alpha™ EV6 interface protocol licensed from Digital
`Equipment Corporation, the AMD Athlon system bus combines
`the latest technological advances, such as point-to-point
`topology, source-synchronous packet-based transfers, and
`low-voltage signaling, to provide the most powerful, scalable
`bus available for any x86 processor.
`
`The AMD Athlon processor is binary-compatible with existing
`x86 software and backwards compatible with applications
`optimized for MMX™ and 3DNow! instructions. Using a data
`format and single-instruction multiple-data (SIMD) operations
`based on the MMX instruction model, the AMD Athlon
`processor can produce as many as four, 32-bit, single-precision
`floating-point results per clock cycle, potentially resulting in
`2.4 Gflops at 600 MHz (fully scalable). The enhanced 3DNow!
`technology implemented in the AMD Athlon includes new
`integer multimedia instructions and software-directed data
`movement instructions for optimizing such applications as
`digital content creation and streaming video for the internet, as
`well as new instructions for digital signal processing
`(DSP)/communications applications.
`
`1.1
`
`AMD Athlon™ Processor Microarchitecture Summary
`
`The following features summarize the AMD Athlon processor
`microarchitecture:
`I The industry’s first nine-issue, superpipelined, superscalar
`x86 processor microarchitecture designed for high clock
`frequencies
`I Multiple x86 instruction decoders
`pipelined
`fully
`I Three
`out-of-order,
`superscalar,
`floating-point execution units, which execute all x87
`(floating-point), MMX and 3DNow! instructions
`I Three out-of-order, superscalar, pipelined integer units
`I Three
`out-of-order,
`superscalar,
`pipelined
`address
`calculation units
`I 72-entry instruction control unit
`I Advanced dynamic branch prediction
`I Enhanced 3DNow! technology with new instructions to
`enable improved integer math calculations for speech or
`video encoding and improved data movement for internet
`plug-ins and other streaming applications
`
`2
`
`Overview
`
`Chapter 1
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 16 of 106
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`

`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`I 200-MHz AMD Athlon system bus (scalable beyond 400
`MHz) enabling leading-edge system bandwidth for data
`movement-intensive applications
`an
`featuring
`I High-performance
`cache
`architecture
`integrated 128-Kbyte L1 cache and a programmable,
`high-speed backside L2 cache interface
`
`The AMD Athlon processor delivers s uper ior system
`performance in a cost-effective, industry-standard form factor.
`The AMD Athlon processor is compatible with motherboards
`based on AMD’s Slot A connector (mechanically compatible
`with the existing SC242 infrastructure), which leverages
`commonly available chassis, power supply, and thermal
`solutions. Figure 1 shows a typical AMD Athlon processor
`system block diagram.
`
`AMD Athlon™
`
`Processor
`
`
`
`AMD-751™
`System
`Controller
`
`
`
`AMD-756™
`Peripheral Bus
`Controller
`
`AGP Bus
`
`Memory Bus
`
`PCI Bus
`
` AGP
`
`DRAM
`
` LAN
`
`SCSI
`
`ISA Bus
`
`BIOS
`
`USB
`
`Dual EIDE
`
`System
`Management
`
`Figure 1. Typical AMD Athlon™ Processor System Block Diagram
`
`Chapter 1
`
`Overview
`
`3
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 17 of 106
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`

`

`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Preliminary Information
`
`4
`
`Overview
`
`Chapter 1
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 18 of 106
`
`

`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`2
`
`2.1
`
`Interface Signals
`
`Overview
`
`The AMD Athlon system bus architecture is designed to deliver
`unprecedented data movement bandwidth for next-generation
`x86 platforms, as well as the high performance required by
`enterprise-class application software. The system bus
`architecture consists of three high-speed channels (a
`unidirectional processor request channel, a unidirectional
`probe channel, and a 72-bit bidirectional data channel,
`including 8-bit error code correction [ECC] protection),
`source-synchronous clocking, and a packet-based protocol. In
`addition, the system bus supports several control, clock, and
`legacy signals. The interface signals use a HSTL-like,
`low-voltage swing signaling technology contained within the
`Slot A mechanical connector, which is mechanically compatible
`with the industry-standard SC242 connector.
`
`2.2
`
`Signaling Technology
`
`The AMD Athlon system bus uses a variation of the low-voltage,
`JEDEC HSTL signaling technology, which has been enhanced
`to provide larger noise margins, reduced ringing, and variable
`voltage levels. The signals are open-drained and require
`termination to a supply that provides the High signal level. The
`HSTL+ inputs use differential receivers, which require a
`reference voltage (VREF). The reference signal is used by the
`receivers to determine if a signal is asserted or deasserted by
`the source. Termination resistors are placed at both ends of the
`interface and are used to provide the High signal level and to
`control reflections on the interface.
`
`2.3
`
`AMD Athlon™ System Bus Signals
`
`Table 2 on page 6 shows the AMD Athlon system bus signals
`and legacy interface signals. Table 1 on page 6 shows the
`pin-type definitions used in the Type column of Table 2.
`
`Chapter 2
`
`Interface Signals
`
`5
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 19 of 106
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`

`

`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Preliminary Information
`
`Table 1.
`
`Pin-Type Definitions
`
`Mnemonic
`I
`O
`I/O
`
`OD
`
`PP
`VCCCORE
`
`Definition
`Standard input pin to the processor
`Standard output pin from the processor
`Bidirectional, three-state input/output pin
`Open-drain structure that allows multiple devices to share the
`pin in a wired-OR configuration
`Push/Pull structure driven by a single source
`AMD Athlon processor core voltage
`
`Table 2.
`
`AMD Athlon™ System Bus and Legacy Interface Signals
`
`Signal Name
`
`Type
`
`Level
`
`Number
`of Pins
`
`Description
`
`A20M#
`
`CLKFWDRST
`
`CONNECT
`
`COREFB+
`COREFB–
`
`FERR
`
`FID[3:0]
`
`IGNNE#
`
`INIT#
`
`INTR
`
`NMI
`
`6
`
`I
`
`I
`
`I
`
`O
`
`O
`
`O
`
`I
`
`I
`
`I
`
`I
`
`OD
`VCCCORE
`OD
`VCCCORE
`OD
`VCCCORE
`PP
`VCCCORE
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`1
`
`1
`
`1
`
`2
`
`1
`
`4
`
`1
`
`1
`
`1
`
`1
`
`A20M# is an input from the system used to simulate address
`wrapping around in the 20-bit 8086.
`CLKFWDRST resets clock-forward circuitry for both the system
`and processor.
`CONNECT is an input from the system used for power
`management and clock-forward initialization at reset.
`
`COREFB+ and COREFB– are outputs to the system that provide
`AMD Athlon processor core voltage feedback to the system.
`
`FERR is an output to the system that is asserted for any
`unmasked numerical exception independent of the NE bit in
`CR0.
`The FID[3:0] signals are outputs to the system that report the
`multiplier used on the system clock (SYSCLK) producing the
`AMD Athlon processor core clock.
`IGNNE# is an input from the system that tells the processor to
`ignore numeric errors.
`INIT# is an input from the system that resets the integer registers
`without affecting the floating-point registers or the internal
`caches. Execution starts at 0FFFF FFF0h.
`INTR is an input from the system that causes the processor to
`start an interrupt acknowledge transaction that fetches the 8-bit
`interrupt vector and starts execution at that location.
`NMI is an input from the system that causes a non-maskable
`interrupt.
`
`Interface Signals
`
`Chapter 2
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 20 of 106
`
`

`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`Table 2.
`
`AMD Athlon™ System Bus and Legacy Interface Signals (continued)
`
`Signal Name
`
`Type
`
`Level
`
`Number
`of Pins
`
`Description
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`OD
`VCCCORE
`OD
`VCCCORE
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`OD
`VCCCORE
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`OD
`VCCCORE
`
`PROCRDY
`
`PWROK
`
`RESET#
`
`SADDIN[14:2]#
`
`SADDINCLK#
`
`SADDOUT[14:2]#
`
`SADDOUTCLK#
`
`SCHECK[7:0]#
`
`SDATA[63:0]#
`
`SDATAINCLK[3:0]#
`
`SDATAINVAL#
`
`O
`
`I
`
`I
`
`I
`
`I
`
`O
`
`O
`
`I/O
`
`I/O
`
`I
`
`I
`
`SDATAOUTCLK[3:0]#
`
`O
`
`I
`
`I
`
`SDATAOUTVAL#
`
`SFILLVAL#
`
`Chapter 2
`
`1
`
`1
`
`1
`
`13
`
`1
`
`13
`
`1
`
`8
`
`64
`
`4
`
`1
`
`4
`
`1
`
`1
`
`PROCRDY is an output to the system and is used for power
`management and source-synchronous clock initialization at
`reset.
`PWROK is an input from the system indicating that the core
`power is within specified limits.
`RESET# is an input from the system that initializes and resets the
`processor and invalidates cache blocks.
`SADDIN[14:2]# is the unidirectional system probe and data
`movement command channel from the system.
`SADDINCLK# is the single-ended source-synchronous clock for
`SADDIN[14:2]# and is driven by the system.
`SADDOUT[14:2]# is the unidirectional processor request channel
`to the system. It is used to transfer processor requests or probe
`responses to the system.
`SADDOUTCLK# is the single-ended source-synchronous clock
`for SADDOUT[14:2]# driven by the processor.
`SCHECK[7:0]# contain the ECC bits for data transfers on
`SDATA[63:0]#.
`SDATA[63:0]# is the bidirectional channel between the processor
`and system for data movement.
`SDATAINCLK[3:0]# is the single-ended forwarded clock driven
`by the system to transfer data on SDATA[63:0]#. Each 16-bit data
`word is skewed-aligned with this clock.
`SDATAINVAL# is driven by the system to pace the data into the
`processor. SDATAINVAL# can be used to introduce an arbitrary
`number of cycles between octawords into the processor.
`SDATAOUTCLK[3:0]# is the single-ended source-synchronous
`clock driven by the processor to transfer data on SDATA[63:0]#.
`Each 16-bit data word on SDATA[63:0]# is skewed-aligned with
`this clock.
`SDATAOUTVAL# is driven by the system to pace the data from
`the processor. SDATAOUTVAL# can be used to introduce an
`arbitrary number of cycles between quadwords from the
`processor.
`SFILLVAL# validates a data transfer to the processor. The system
`may tie this pin to the asserted state (validating all fills). The
`processor samples SFILLVAL# at the first or second data beat.
`
`Interface Signals
`
`7
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 21 of 106
`
`

`

`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Preliminary Information
`
`Table 2.
`
`AMD Athlon™ System Bus and Legacy Interface Signals (continued)
`
`Signal Name
`
`Type
`
`Level
`
`Number
`of Pins
`
`Description
`
`SMI#
`
`STPCLK#
`
`SYSCLK
`SYSCLK#
`
`VCC2SEL
`
`VID[3:0]
`
`I
`
`I
`
`I
`
`O
`
`O
`
`OD
`VCCCORE
`OD
`VCCCORE
`
`OD
`VCCCORE
`OD
`VCCCORE
`
`1
`
`1
`
`2
`
`1
`
`4
`
`SMI# is an input that causes the processor to enter the system
`management mode.
`STPCLK# is an input that causes the processor to enter a lower
`power mode and issue a Stop Grant special cycle.
`SYSCLK and SYSCLK# are differential input clock signals
`provided to the processor’s PLL from a system-clock generator.
`VCC2SEL is an output to the system that indicates the required
`core voltage for the L2 SRAM. High=2.5V, Low=3.3V.
`The VID[3:0] signals are outputs to the motherboard that
`indicate the required VCCCORE voltage for the processor.
`
`8
`
`Interface Signals
`
`Chapter 2
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 22 of 106
`
`

`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`3
`
`Logic Symbol Diagram
`
`Clock
`
`SYSCLK
`
`SYSCLK#
`
`AMD Athlon™
`Processor
`
`VID[3:0]
` COREFB+
` COREFB–
` PWROK
` VCC2SEL
`
`FID[3:0]
`
` FERR
` IGNNE#
` INIT#
` INTR
` NMI
` A20M#
` SMI#
`
`Voltage
`Control
`
`Frequency
`Control
`
`Legacy
`
`
`
`Data
`
`Probe/SysCMD
`
`Request
`
`Power
`Management
`and Initialization
`
`SDATA[63:0]#
`SDATAINCLK[3:0]#
`SDATAOUTCLK[3:0]#
`SCHECK[7:0]#
`SDATAINVAL#
`SDATAOUTVAL#
` SFILLVAL#
`
`SADDIN[14:2]#
`SADDINCLK#
`
`SADDOUT[14:2]#
`SADDOUTCLK#
`
`PROCRDY
`CLKFWDRST
`CONNECT
`STPCLK#
`RESET#
`
`Figure 2. Logic Symbol Diagram
`
`Chapter 3
`
`Logic Symbol Diagram
`
`9
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 23 of 106
`
`

`

`AMD Athlon™ Processor Data Sheet
`
`21016G/0—December 1999
`
`Preliminary Information
`
`10
`
`Logic Symbol Diagram
`
`Chapter 3
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1036
`Page 24 of 106
`
`

`

`21016G/0—December 1999
`
`AMD Athlon™ Processor Data Sheet
`
`Preliminary Information
`
`4
`
`4.1
`
`Power Management
`
`Power Management States
`
`The AMD Athlon processor uses multiple advanced power
`states to place the processor in reduced power modes. These
`power states are used to enhance processor performance,
`minimize power dissipation, and provide a balance between
`performance and power (see “Power Dissipation” on pag