United States Patent (19)
`Kikinis et al.
`
`USOO5919262A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,919,262
`Jul. 6, 1999
`
`54) VARIABLE-VOLTAGE CPU VOLTAGE
`REGULATOR
`75 Inventors: Dan Kikinis, Saratoga; Pascal Dornier,
`Sunnyvale, both of Calif.
`73 Assignee: Elonex I.P. Holdings, Ltd., London,
`United Kingdom
`
`21 Appl. No.: 09/017,049
`22 Filed:
`Feb. 2, 1998
`Related U.S. Application Data
`62 Division of application No. 08/753,262, Nov. 12, 1996, Pat.
`No. 5,774,734, which is a continuation of application No.
`08/319,817, Oct. 7, 1994, abandoned.
`(51) Int. Cl." ........................................................ G06F 1/26
`52 U.S. Cl. ..................
`713/300; 323/282; 323/351
`58 Field of Search ............................. 713/300; 323/351,
`323/282,281, 352, 353, 354
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,419,619 12/1983 Jindrick et al. ......................... 323/257
`
`4.509,128 4/1985 Coppola et al. .......................... 702/61
`5,294.879 3/1994 Freeman et al.
`... 322/23
`5,429,959
`7/1995 Smayling ................................ 438/234
`5. 1. St. .
`35.
`2- - -2
`CIIIl Cal. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`5,552,696 9/1996 Trainor et al. .......................... 323/275
`37: FC G.I.O.357.6
`Primary Examiner Ayaz R. Sheikh
`Assistant Examiner Rupal D. Dharia
`Attorney, Agent, or Firm Donald R. Boys
`57
`ABSTRACT
`An integrated CPU has an on-board Switching Voltage
`regulator with an electrically-erasable programmable read
`only memory electronically accessible for Storing a feedback
`reference coefficient for control. In further embodiments,
`output voltage is tuned via a second EEPROM storing an
`electronically accessible value in concert with a Solid-State
`resistor ladder. In other embodiments, Signals on interrupt
`lines to the CPU are monitored to provide a prewarning of
`impending activity by the CPU requiring dramatically
`increased current flow. In yet other embodiments, Solid State
`circuitry is provided to reduce or eliminate capacitors used
`for dealing with input current surges to the CPU.
`9 Claims, 7 Drawing Sheets
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`Voltage
`Regulator
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`Power Source (PSU)
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`Early Warning Signals
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`Event Logic
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`1
`VARIABLE-VOLTAGE CPU VOLTAGE
`REGULATOR
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`5,919,262
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`2
`SUMMARY OF THE INVENTION
`In a preferred embodiment of the present invention, a
`Switching Voltage regulator has an electrically erasable
`programmable read-only memory unit (EEPROM or E) for
`Storing a coefficient for feedback loop Voltage regulation.
`The coefficient is adjusted by clocking a Serial data Stream
`into a register until a desired value for the feedback coef
`ficient is reached, then storing the value in the EEPROM by
`means of an input line.
`In another embodiment, the adjustment potentiometer
`used in prior art devices is replaced by an external Ef and a
`resistor ladder to adjust output Voltage.
`In various embodiments, regulator apparatus according to
`the invention is implemented on a motherboard, in a multi
`chip CPU package, and integrated in a single chip CPU.
`There are also several embodiments to deal with current
`Surges, reducing or eliminating capacitors conventionally
`required. In yet another embodiment, the Voltage regulator
`receives a pre-warning based on a wakeup mechanism
`according to the invention.
`The invention provides vastly improved efficiency and
`regulation, reaction time, reduced line losses, and reduced
`probability of failure under rapidly changing circumstances,
`than may be found in current art.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a CPU voltage regulator in
`Current art.
`FIG. 2 is a block diagram of a CPU voltage regulator
`according to an embodiment of the present invention.
`FIG.3 is a Schematic of a Switching voltage regulator chip
`with a resistor or potentiometer as used in current art.
`FIG. 4 is a partly schematic diagram of a CPU voltage
`regulator replacing the current art potentiometer of the
`regulator of FIG. 3 with an external EEPROM and a resistor
`ladder.
`FIG. 5 is a block diagram of an enhanced embodiment of
`the present invention showing a prewarning System based on
`a wakup mechanism.
`FIG. 6 shows an embodiment using a Synchronous digital
`buck converter.
`FIG. 7 shows an embodiment incorporating a series of
`dummy capacitors, controlled by a EEPROM for slowing
`the rise time of the Switching regulator and inductor to match
`the CPU rise time.
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`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`FIG. 2 shows a Switching Voltage regulator 11 with an
`erasable EPROM (E) 13 that holds a coefficient for feed
`back loop Voltage regulation. To adjust the output value of
`the regulator, a Serial data Stream can be clocked into a
`register 15 until the desired value is obtained. At this point,
`that value can be stored in the E by means of a line not
`shown. The Stored value can be read permanently and is
`easily changed again, if required, without manual adjust
`ment.
`In FIG. 4 the potentiometer of FIG. 3 is replaced by an
`external Ef 19 and an R-ladder 21 to adjust the output
`Voltage. Data and clock values are input to register 23 upon
`System initialization. The circuit can be tuned for optional
`voltage for the CPU, and then the E is programmed.
`This circuit may be implemented on a motherboard, in a
`multi-chip CPU package, or integrated in a Single-chip CPU.
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`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`The present application is a divisional application from
`application 08/753,262 Nov. 12, 1996, which is a U.S. Pat.
`No. 5,774,734 which is a continuation of application from
`application 08/319,817 Oct. 7, 1994, now abandoned.
`FIELD OF THE INVENTION
`The present invention is in the area of general-purpose
`computerS Such as desktop computers and portable
`computers, and pertains in particular to Supplying regulated
`electrical power to central processing units (CPUs) and other
`computer elements.
`BACKGROUND OF THE INVENTION
`In the development of power Supplies and power man
`agement for computer Systems, as in most technologies, new
`concepts and products bring with them new problems, and
`Sometimes older problems are exacerbated. Supplying
`power to CPUs on computer motherboards is a case in point.
`As CPUs have gotten faster and more powerful, they have
`also increased in load requirements and in total power
`consumed. Moreover, efforts have been made to reduce the
`Voltage required for microprocessors used in and for CPUs.
`At lower Voltage, Such as 3.3 volts now required by Some
`commercially available microprocessors, instead of the tra
`ditional 5 volts, Voltage regulation becomes more important.
`Voltage regulation is more important with newer micro
`processors also because of the higher power, hence higher
`current, and the speed with which events transpire in modern
`computers. A high-power microprocessor Suddenly
`activated, with immediate processing activity as well, gen
`erates a relatively high rate of change of current with respect
`to time, which can (and does) seriously effect the Voltage
`Supplied, unless adequate Steps are taken to avoid or manage
`the transient circumstances.
`In current art there are three fundamental implementations
`of variable-voltage CPU voltage regulators:
`1. Regulator in power Supply. This implementation is not
`accurate, its cross-regulation is not good, and on line
`losses are too high.
`2. Line regulator on motherboard. This method is cost
`effective, but efficiency is low and reaction Speed is
`poor.
`3. Switching regulator on motherboard. Efficiency
`improves, but the cost is high and reaction Speed
`remains poor.
`FIG. 1 shows a voltage regulator and dual-voltage CPU in
`current technology. A power Source (the power Supply unit)
`supplies 12-volt and 5-volt output. A 5-volt CPU uses power
`directly from the PSU. A 3.3-volt CPU requires conversion
`through the Voltage regulator.
`In all current art, the best accuracy without manual
`adjustment is 3% or worse. Improving accuracy below a 3%
`tolerance increases the cost unacceptably and needs con
`tinual manual adjustment-not acceptable requirements in a
`personal computer.
`FIG. 3 ShowS details of a Switching Voltage regulator chip
`with a resistor or potentiometer, as used in current art.
`What is clearly needed is improved methods and appara
`tus for regulating Voltage to CPUs to improve regulation,
`control line losses, improve reaction time (speed), and to
`improve efficiency.
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`5,919,262
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`3
`It has Several different enhancements to reduce or eliminate
`the capacitorS required to deal with the current Surge that
`occurs when the CPU goes from idle (typically in the
`milliamp range) to active (typically in a range of multiple
`amperes), in approximately 100 ns.
`FIG. 5 shows the first enhancement. Voltage regulator 25
`receives a prewarning based on a wake-up mechanism 27.
`Signals on interrupt lines (NMI. INT, SMI) to CPU 29 are
`Sensed and combined with Some logic (e.g., PAL). The
`resulting lines Senda warning on path 31 to Voltage regulator
`25 of imminent activity by the CPU, with dramatically
`increased current requirements. Thus the Voltage regulator
`can take countermeasures in anticipation of CPU activity.
`Second and third enhancements may be used when the
`first enhancement is in place. In FIG. 6 the Second enhance
`ment uses a Synchronous digital Buck converter running on
`a divided CPU clock. To allow the prewarning logic to work
`properly, the divider must be Synchronized as well.
`The third enhancement (see FIG. 7) uses a series of
`dummy capacitors 33, controlled by the Ef, to slow the rise
`time of the Switching regulator and inductor to match the
`CPU rise time.
`It will be apparent to those with skill in the art that there
`are many alterations that may be made without departing
`from the Spirit and Scope of the invention. There are, for
`example, many equivalent ways the circuitry elements might
`be arranged to produce essentially the same result, and there
`are many ways IC elements might be arranged as well.
`What is claimed is:
`1. A voltage regulated CPU for a general-purpose
`computer, comprising:
`a CPU portion; and
`a Switching Voltage regulator portion having a primary
`input and a regulated output connected to the CPU,
`35
`wherein the Switching Voltage regulator portion com
`prises:
`Switching circuitry connected between the primary
`input and the regulated output, for altering Voltage at
`the regulated output; and
`adjustment circuitry including a magnitude Stored in a
`programmable non-volatile memory, the adjustment
`circuitry connected to the Switching circuitry and to
`the regulated output;
`wherein the adjustment circuitry controls the Switching
`circuitry to provide a Voltage magnitude at the regul
`lated output according to the Stored magnitude;
`wherein the adjustment circuitry further comprises a
`digital register Settable by a Serial data Stream, and
`transfer circuitry for transferring a digital value from
`the digital register to the digital memory, whereby the
`Voltage magnitude at the regulated output may be
`raised or lowered by resetting the digital value in the
`digital register and transferring the digital register value
`to the programmable non-volatile memory;
`wherein the digital value controls a resistor ladder
`(R-ladder) to manage feedback Voltage to the adjust
`ment circuitry.
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`4
`2. A voltage-regulated CPU as in claim 1 further com
`prising a wakeup logic circuit coupled to interrupt lines to
`the CPU and to the voltage regulator, wherein interrupt
`activity is signaled to the Voltage regulator So the Voltage
`regulator may prepare for incipient CPU activity.
`3. A voltage-regulated CPU as in claim 2 wherein the
`Switching circuitry comprises a buck converter, and wherein
`the wakeup logic circuit controls a divided CPU clock
`connected to the CPU and to the buck converter.
`4. A Voltage-regulated CPU as in claim 3 comprising a Set
`of capacitors in the buck converter, the Set of capacitors
`Switched in as needed by output from the programmable
`non-volatile memory to slow rise time of the Switching
`voltage regulator to match rise time of the CPU portion.
`5. A Switching Voltage regulator having a primary input
`and a regulated output, comprising:
`Switching circuitry connected between the primary input
`and the regulated output, for altering Voltage at the
`regulated output; and
`adjustment circuitry including an electrically erasable
`programmable read-only memory (EEPROM), the
`adjustment circuitry connected to the Switching cir
`cuitry and to the regulated output;
`wherein the adjustment circuitry controls the Switching
`circuitry to provide a Voltage magnitude at the regul
`lated output according to a value Stored in the
`EEPROM;
`wherein the adjustment circuitry further comprises a
`digital register Settable by a Serial data Stream, and
`transfer circuitry for transferring a digital value from
`the digital register to the EEPROM, whereby the volt
`age magnitude at the regulated output may be raised or
`lowered by resetting the digital value in the digital
`register and transferring the digital register value to the
`EEPROM;
`wherein the digital value controls a resistor ladder
`(R-ladder) to manage feedback Voltage to the adjust
`ment circuitry.
`6. A Switching Voltage regulator as in claim 5 further
`comprising a wakeup logic circuit coupled to the Voltage
`regulator, and having input lines configured to couple to
`interrupt lines to a CPU, wherein interrupt activity is Sig
`nalled to the Voltage regulator So the Voltage regulator may
`prepare for incipient CPU activity.
`7. A Switching Voltage regulator as in claim 6 wherein the
`Switching circuitry comprises a buck converter, and wherein
`the wakeup logic circuit controls a divided CPU clock
`connectable to a CPU and connected to the buck converter.
`8. A Switching Voltage regulator as in claim 7 comprising
`a set of capacitors in the buck converter, the Set of capacitors
`Switched in as needed by output from the EEPROM to slow
`rise time of the Switching Voltage regulator to match rise
`time of the CPU.
`9. A Switching Voltage regulator as in claim 5 wherein the
`regulator and all its elements are integrated on a Single
`Semiconductor chip.
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