IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`HD SILICON SOLUTIONS LLC,
`
`
`
`
`
`Plaintiff
`
`v.
`
`Civil Action No. 6:20-cv-1092-ADA
`
`MICROCHIP TECHNOLOGY INC.,
`
`PATENT CASE
`
`Defendant.
`
`JURY TRIAL DEMANDED
`
`
`MICROCHIP’S INITIAL INVALIDITY CONTENTIONS
`
`Pursuant to the Parties’ Stipulated May 25, 2021 Scheduling Order (ECF 26), Microchip
`
`Technology Inc. (“Microchip”) hereby provides its Invalidity Contentions for U.S. Patent Nos.
`
`7,260,731 (the “’731 patent”); 7,870,404 (the “’404 patent”); 7,810,002 (the “’002 patent”);
`
`7,154,299 (the “’299 patent”); 7,302,619 (the “’619 patent”); 6,774,033 (the “’033 patent”)
`
`(collectively, the “Asserted Patents”). Plaintiff HD Silicon Solutions LLC (“HDSS” or
`
`“Plaintiff”) has asserted the following claims:
`
` claims 1, 4, 6, 8 of the ’731 patent;
`
` claims 1, 3, 5, 6, 11, 14, 15, 16, 18, 19, 21 of the ’404 patent;
`
` claims 1, 2, 3, 4, 5, 6, 8, 9, 11, 12, 15, 16, 17, 18, 19 of the ’002 patent;
`
` claims 1–16, 18, 19, 23, 24, 25 of the ’299 patent;
`
` claims 1, 2, 3, 6, 10, 11, 12, 13, 14, 17, 21 22, 24, 26, 27, 28, 29, 30, 31 of the
`
`’619 patent; and
`
` claims 1, 2, 5, 8, 10, 13, 17 of the ’033 patent (collectively, the “asserted
`
`claims”).
`
`Microchip makes the following invalidity contentions based upon its current knowledge,
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1056
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`its current understanding of HDSS’ infringement contentions served on May 4, 2021, and its
`
`investigations to date. Microchip’s investigation into the facts is ongoing, general fact discovery
`
`has not yet been opened in this case, and claim construction has not yet commenced. Microchip
`
`has not completed its investigation of the facts relating to this case, discovery in this action, or its
`
`preparation for trial. This disclosure is without prejudice to Microchip’s right to produce
`
`evidence of additional prior art references or its right to supplement or amend the disclosures
`
`made herein.
`
`I.
`
`IDENTIFICATION OF PRIOR ART
`A.
`Prior Art Patents and Publications
`
`Microchip contends that the asserted claims are invalid under 35 U.S.C. §§ 102 and/or
`
`103 based on the following prior art patent publications. These patent publications constitute
`
`prior art under 35 U.S.C. § 102, and their patent numbers, countries of origin, and dates of
`
`publication and/or issue are included on the face of those documents. The filing dates listed
`
`below are simply the filing dates of the identified patents or patent publication; they may have
`
`earlier effective filing dates. Microchip reserves the right to supplement this list as it learns in
`
`the course of discovery of other prior art patent publications that would anticipate and/or render
`
`the asserted claims obvious.
`
`1.
`
`The ’731 patent
`
` NEC Electronics, Inc., “1990 Single-Chip Microcontroller Databook” (May 1990)
`
`(“NEC-Databook”).
`
` U.S. Patent No. 6,748,545 to Helms et al. (“Helms”).
`
` U.S. Patent No. 4,716,354 to Hacker (“Hacker”).
`
` Thomas Burd et al., “A Dynamic Voltage Scaled Microprocessor System,” in
`
`Digest of Technical Papers, 2000 IEEE Int. Solid-State Circuits Conf. (Feb. 2000)
`
`-2-
`
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`(“Burd”).
`
` U.S. Patent No. 6,092,207 to Kolinski et al., (“Kolinski”).
`
` U.S. Patent No. 5,919,262 to Kikinis et al. (“Kikinis”).
`
` Dieter Knollman, “Designing with Op Amps: Single-Formula Technique Keeps it
`
`Simple,” EDN (March 2, 1998) (“Knollman”).
`
` Advanced Configuration and Power Interface Specification, Rev. 1.0 (Dec. 22,
`
`1996) (the “ACPI standard” or the “ACPI”).
`
` U.S. Patent No. 5,565,761 to Hwang (“Hwang”).
`
` U.S. Patent No. 5,627,460 to Bazinet et al. (“Bazinet”).
`
` U.S. Patent No. 6,785,829 to George et al. (“George”).
`
` U.S. Patent No. 6,772,356 to Qureshi et al. (“Qureshi”).
`
`2.
`
`The ’404 patent
`
` NEC Electronics, Inc., “1990 Single-Chip Microcontroller Databook,” (May
`
`1990) (“NEC-Databook”).
`
` Anthony J. Stratakos, “High-Efficiency Low-Voltage DC-DC Conversion for
`
`Portable Applications,” Univ. of California, Berkeley, Ph.D. Dissertation (1998)
`
`(“Stratakos”).
`
` Advanced Configuration and Power Interface Specification, Rev. 1.0 (Dec. 22,
`
`1996) (the “ACPI standard” or the “ACPI”).
`
` Allan Baril, “Using Windows NT in Real-Time Systems,” in Proceedings of the
`
`Fifth IEEE Real-Time Technology and Applications Symposium (RTAS '99)
`
`(1999) (“Baril”).
`
` PCI Local Bus Specification, Rev. 2.2 (1998) (the “PCI Standard”).
`
`-3-
`
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` A. Chandrakasan, V. Gutnik, and T. Xanthopoulos, “Data Driven Signal
`
`Processing: An Approach for Energy Efficient Computing,” 1996 International
`
`Symposium on Low Power Electronics and Design, pp. 347-352 (1996).
`
` L. Nielsen and J. Sparso, “Low-Power Operation Using Self-Timed Circuits and
`
`Adaptive Scaling of the Supply Voltage,” 2 IEEE Transactions on Very Large
`
`Scale Integration (VLSI) Sys., pp. 391-97 (Dec. 1994).
`
` W. Namgoong, M. Yu, and T. Meng, “A High-Efficiency Variable-Voltage
`
`CMOS Dynamic dc-dc Switching Regulator,” IEEE International Solid-State
`
`Circuits Conference, pp. 380-81, 489 (Apr. 1997).
`
` G. Wei and M. Horowitz, “A Low Power Switching Supply for Self-Clocked
`
`Systems,” 1996 International Symposium on Low Power Electronics and Design,
`
`pp. 313-17 (1996).
`
`3.
`
`The ’002 patent
`
` U.S. Patent No. 7,248,069 to Moyer (“Moyer”) (filed August 11, 2003).
`
` U.S. Patent Publ. 2003/0177373 to Moyer (“Moyer ’373”) (filed March 18, 2002).
`
` U.S. Patent No. 7,444,668 to Moyer (“Moyer ’668”) (filed May 29, 2003).
`
` U.S. Patent Publ. 2003/0172214 to Moyer (“Moyer ’214”) (filed March 8, 2002).
`
` U.S. Patent Publ. 2003/0204801 to Tkacik (filed April 30, 2002).
`
` U.S. Patent No. 7,228,440 to Giles (“Giles”) (filed December 20, 2002).
`
` U.S. Patent No. 7,117,352 to Giles (“Giles ’352”) (filed December 20, 2002).
`
` WO 2004/046916 A2 to Watt (“Watt”) (filed October 27, 2002).
`
` U.S. Patent No. 7,149,862 to Tune (filed September 3, 2004).
`
` U.S. Patent No. 7,849,310 to Watt (“Watt ’310) (filed November 17, 2003).
`
`-4-
`
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` U.S. Patent Publ. 2004/0128507 to McKenney (filed December 30, 2002).
`
` U.S. Patent Publ. 2001/0016916 to Mayer (filed on February 6, 2001).
`
` U.S. Patent No. 8,255,700 to Kitariev (filed June 29, 2004).
`
` U.S. Patent No. 7,461,407 to Little (filed February 4, 2005).
`
` European Patent Application No. EP 1 443 338 A1 to Ravenhill (filed February 3,
`
`2003).
`
` A. Menezes et al., Handbook of Applied Cryptography (1996).
`
` B. Schneier, Applied Cryptography (2d. ed. 1996).
`
`
`
`Information Technology Laboratory, National Institute of Standards and
`
`Technology, The Keyed-Hash Message Authentication Code (HMAC), (FIPS Pub.
`
`198, March 6, 2002).
`
` National Institute of Standards and Technology, Entity Authentication Using
`
`Public Key Cryptography (FIPS Pub. 196, February 18, 1997).
`
` W. Barksdale, Practical Computer Data Communications (Plenum Press, New
`
`York, 1st ed. 1986).
`
` J. Labrosse, Embedded Systems Building Blocks (R&D Books, 2d. ed. 2000).
`
` J. Rabaey et al., Digital Integrated Circuits | A Design Perspective (Pearson
`
`Education, Inc., 2d. ed. 2003).
`
` D. Lewin et al., Design of Logic Systems (Springer-Science and Business Media,
`
`B.V., 2d. ed. 1992).
`
` Gartner, Inc., The Gartner Glossary of Information Technology Acronyms and
`
`Terms (May 2003).
`
` National Communications System Technology and Standards Division,
`
`-5-
`
`
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`Telecommunications: Glossary of Telecommunication Terms (Federal Standard
`
`1037C, August 7, 1996).
`
`
`
`IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1-2001
`
`(2001).
`
` S. Ravi et al., Security in Embedded Systems: Design Challenges, ACM
`
`Transactions on Embedded Computing Systems, Vol. 3, No. 3, (August 2004).
`
` Mukhopadhyay et al., CryptoScan: A Secured Scan Chain Architecture,
`
`Proceedings of the 14th Asian Test Symposium (2005).
`
` Yang et al., Secure Scan: A Design-for-Test Architecture for Crypto Chips, DAC
`
`2005 (2005).
`
` Yang et al., Scan Based Side Channel Attack on Dedicated Hardware
`
`Implementations of Data Encryption Standard, ITC International Test Conference
`
`(2004).
`
`4.
`
`The ’299 patent
`
` U.S. Patent No. 5,457,410 to Ting (filed August 3, 1993).
`
` U.S. Patent No. 6,034,547 to Pani et al. (filed September 4, 1996).
`
` U.S. Patent No. 5,990,702 to Agrawal (filed December 22, 1997).
`
`5.
`
`The ’619 patent
`
` U.S. Patent No. 7,278,083 to Haswell et al. (filed June 27, 2003).
`
` U.S. Patent No. 7,290,179 to Lempel et al. (filed December 01, 2003).
`
` U.S. Patent No. 7,395,489 to Itou et al. (filed January 13, 2003).
`
` U.S. Patent No. 5,500,950 to Becker et al. (filed January 29, 1993).
`
` U.S. Patent No. 6,804,799 to Zuraski et al. (filed June 26, 2001).
`
`-6-
`
`
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`

`6.
`
`The ’033 patent
`
` U.S. Patent No. 5,847,463 to Trivedi, et al. (filed August 22, 1997).
`
` U.S. Patent No. 6,534,401 to Joo et al. (filed April 27, 2000).
`
` U.S. Patent No. 5,807,779 to Liaw (filed July 30, 1997).
`
` U.S. Patent No. 6,160,296 to Violette et al. (filed June 22, 1999).
`
` U.S. Patent No. 6,879,043 to Matsumoto et al. (filed August 7, 2001).
`
` A Comparison of TiN Processes for CVD W /TiN Gate Electrode on 3nm Gate
`
`Oxide, International Electron Devices Meeting 459-462, IEEE (1997) (Yang)
`
`(available to the public as of December 10, 1997).
`
`B.
`
`Prior Art Systems and/or Knowledge
`
`Microchip contends that the asserted claims of the asserted patents are invalid under 35
`
`U.S.C. §§ 102 and/or 103 based on the following items offered for sale or publicly used or
`
`known. Microchip incorporates by reference and reserves the right to rely upon any prior art
`
`items and/or knowledge disclosed by or referred to in any of the prior art patents or prior art
`
`publications identified above in Section I.A. Because Microchip has not yet completed
`
`discovery in this case, Microchip reserves the right to supplement this disclosure with facts,
`
`documents, or other information learned at a later point through third-party discovery or other
`
`further investigation. For example, Microchip will request and receive documents from third
`
`parties that are believed to have knowledge, documentation, and/or corroborating evidence
`
`concerning some of the prior art listed in Microchip’s charts and/or additional prior art. The
`
`table below identifies exemplary products that anticipate or render obvious certain Asserted
`
`Claims of the Asserted Patents.
`
`-7-
`
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`

`

`1.
`
`The ’731 patent
`
` NEC PD751xx/75P1xx Microcomputers (as evidenced at least by NEC
`
`Electronics, Inc., “1990 Single-Chip Microcontroller Databook,” (May 1990)
`
`(“NEC-Databook”)).
`
` The H8/3067 Series H8-3067 F-ZTAT product (as described in Hitachi Ltd.,
`
`“H8/3067 Series H8/3067 F-ZTATTM Hardware Manual, Rev. 3.0,” (February 22,
`
`1999) (“Hitachi-H8-3067-Datasheet”)).
`
` Maxim MAX1652–MAX1655 High-Efficiency, PWM, Step-Down DC-DC
`
`Controllers (as evidenced by Maxim Integrated Inc., “High-Efficiency, PWM,
`
`Step-Down DC-DC Controllers in 16-Pin QSOP, MAX1652–MAX1655,” Rev. 1
`
`(Jul. 1998) (“Maxim-165X-Datasheet”)).
`
` MAX1710-MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers (as
`
`evidenced by Maxim Integrated, Inc., “High-Speed, Digitally Adjusted Step-
`
`Down Controllers for Notebook CPUs, MAX1710/MAX1711,” Rev. 0 (Nov.
`
`1998) (“Maxim-171X-Datasheet”) and Maxim Integrated, Inc., “MAX1711
`
`Voltage Positioning Evaluation Kit,” Rev. 0 (Nov. 1999) (“Maxim 1711-Kit”)).
`
` TPS5210 Programmable Synchronous-Buck Regulator Controller (as evidenced
`
`by Texas Instruments, Inc., “TPS5210 Programmable Synchronous-Buck
`
`Regulator Controller,” (May 1999) (“TI-TPS5210-Datasheet”)).
`
` AMD Athlon Processor 1999 (as evidenced by Advanced Micro Devices, Inc.,
`
`“AMD Athlon Processor Datasheet,” Rev. G (1999) (“Athlon-99-Datasheet”) and
`
`Advanced Micro Devices, Inc., “AMD 756 Peripheral Bus Control Datasheet,”
`
`Rev. B (August 1999) (“AMD-756-Datasheet”)).
`
`-8-
`
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`

` AMD Athlon Processor 2000 (as evidenced by Advanced Micro Devices, Inc.,
`
`“AMD Athlon Processor Module Datasheet, Rev. M (June 2000) (“Athlon-00-
`
`Datasheet”) and AMD-756-Datasheet”).
`
`
`
`Intel Mobile Pentium® II Processor (as evidenced by Intel, Inc., “Mobile
`
`Pentium® II Processor at 233, 266, and 300 MHz” (1998) (“Pentium-Datasheet”)).
`
` Additional products pending the commencement of fact discovery.
`
`2.
`
`The ’404 patent
`
` NEC PD751xx/75P1xx Microcomputers (as evidenced by NEC Electronics, Inc.
`
`“1990 Single-Chip Microcontroller Databook” (May 1990) (“NEC-Databook”)).
`
` AMD Athlon Processor 1999 (as evidenced by Advanced Micro Devices, Inc.,
`
`“AMD Athlon Processor Datasheet,” Rev. G (1999) (“Athlon-99-Datasheet”) and
`
`Advanced Micro Devices, Inc., “AMD 756 Peripheral Bus Control Datasheet,”
`
`Rev. B (August 1999) (“AMD-756-Datasheet”)).
`
` AMD Athlon Processor 2000 (as evidenced by Advanced Micro Devices, Inc.,
`
`“AMD Athlon Processor Module Datasheet, Rev. M” (June 2000) (“Athlon-00-
`
`Datasheet”) and (“AMD-756-Datasheet”)).
`
` The H8/3067 Series H8-3067 F-ZTAT product (as described in Hitachi Ltd.,
`
`“H8/3067 Series H8/3067 F-ZTATTM Hardware Manual, Rev. 3.0,” (February 22,
`
`1999) (“Hitachi-H8-3067-Datasheet”)).
`
`
`
`Intersil Voltage Regulation System based on HIP6302 (as described in Intersil
`
`Corp., “HIP6302 Datasheet, File Number 4766” (2000) (“HIP6302-Datasheet”))
`
` Additional products pending the commencement of fact discovery.
`
`-9-
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`3.
`
`The ’002 patent
`
` Freescale Semiconductor i.MX processors, as evidenced by at least the following:
`o Freescale i.MX31 and i.MX31L Multimedia Applications Processors
`
`Datasheet (2005) (“i.MX31 Datasheet”).
`o Freescale i.MX31 and i.MX31L Multimedia Applications Processors
`
`Product Brief, Rev. 0.6 (06/2005) (“i.MX31 Product Brief”).
`o Freescale MCIMX31 and MCIMX31L Multimedia Applications
`
`Processors Reference Manual, Rev. 1 (2/2006) (“i.MX31 Reference
`
`Manual”).
`o A. Ashkenazi, Freescale Whitepaper, Security Features in the i.MX31 and
`
`i.MX31L Multimedia Applications Processors, Rev. 0.0 (06/2005)
`
`(“Ashkenazi i.MX31 Whitepaper”).
`o A. Ashkenazi, Securing Smartphones from the Inside Out, Freescale
`
`Semiconductor Israel, Design Seminars 2005 Proceedings, embedded
`
`systems conference San Francisco 2005, 3G Cellular Design Seminar,
`
`session 3GC-702; March 2005 (“Ashkenazi Conference Paper”).
`o A. Ashkenazi, Your Smartphone Data May Be at Risk, EE Times, June 2,
`
`2005 (“Ashkenazi EE Times Article”).
`
` Dallas Semiconductor / Maxim MAXQ Microcontrollers, as evidenced by at least
`
`the following:
`o Dallas Semiconductor / Maxim, MAXQ2000 Low Power LCD
`
`Microcontroller Datasheet, Rev 0, 10/04 (“MAXQ2000 Datasheet”).
`o Maxim Integrated Application Note, Programming in the MAXQ
`
`-10-
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`Environment (“MAXQ Application Note”).
`o Maxim Integrated, MAXQ Family User’s Guide, Rev. 6 (9/2008)
`
`(“MAXQ User Guide”).
`
` Texas Instruments TMS470R1x Microcontrollers, as evidenced by at least the
`
`following:
`o TMS470R1VF48C JTAG Security Module (JSM) Reference Guide, Texas
`
`Instruments Literature Number SPNU245 (February 2005) (“JSM
`
`Reference Guide”).
`o TMS470R1x Memory Security Module Reference Guide, Texas
`
`Instruments Literature Number SPNU243 (October 2005) (“MSM
`
`Reference Guide”).
`o TMS470R1VF478 16/32-Bit RISC Flash Microcontroller Datasheet,
`
`Texas Literature Number SPNS082D (Jan. 2004, Revised Jan. 2006)
`
`(“TMS470R1VF478 Datasheet”).
`o TMS470R1VF48C/VF48B 16/32-Bit RISC Flash Microcontroller
`
`Datasheet, Texas Literature Number SPNS093D (May 2004, Revised Feb.
`
`2006) (“TMS470R1VF48C/VF48B Datasheet”).
`
` M. Michael et al., The NS16550A: UART Design and Application Considerations
`
`(National Semiconductor Corp., AN-491 July 1987)
`
` Nintendo GameCube and the IBM Gekko Processor, as evidenced by at least the
`
`following:
`o IGN, https://www.ign.com/articles/2000/08/24/gamecube-full-specs (last
`
`visited June 26, 2021).
`
`-11-
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`

`o ZDNet, https://www.zdnet.com/article/whats-inside-the-gamecube/ (last
`
`visited June 26, 2021).
`o IBM Gekko RISC Microprocessor User’s Manual, Version 1.2, p. 8-38
`
`(May 25, 2000) (“Gekko boundary-scan interface is a fully-compliant
`
`implementation of the IEEE 1149.1a-1993 standard. This section describes
`
`Gekko’s IEEE 1149.1a-1993 (JTAG) interface.”).
`o A. Shimpi, Hardware Behind the Consoles – Part II: Nintendo’s
`
`GameCube (December 7, 2001) (available at
`
`http://www.anandtech.com/print/858/).
`
` Additional products pending the commencement of fact discovery, including but
`
`not limited to:
`o Texas Instruments OMAP processors. See, e.g., Texas Instruments,
`
`OMAP 2423 Processor, Texas Instruments SWPU087B; OMAP Platform
`
`Security Features, Texas Instruments White Paper SWPT0008 (July
`
`2003).
`o Products by Infineon or Corrent Corporation, including Infineon
`
`Microcontrollers (such as the XC800) implementing is On-Chip Debug
`
`Support module. Infineon, CS166S On Chip Debug Support User’s
`
`Manual, V. 1.1 (August 2001); Infineon, XC800 Microcontroller Family
`
`User’s Manual, V. 0.1, (January 2005).
`o Atmel SAM Microcontrollers. JTAG and scan features were added to
`
`Atmel SAM devices at least by 2004, though Microchip’s investigation is
`
`ongoing. Microchip reserves the right to assert Atmel SAM devices as
`
`-12-
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`prior art in response to information learned through such discovery, or in
`
`response to HDSS’s infringement positions.
`o Fact discovery is not yet opened, and Microchip reserves the right to
`
`obtain information and documents from other manufactures, such as
`
`manufactures of trusted platforms (e.g., Broadcom, Dell Computer,
`
`Fujitsu, Hewlett-Packard, IBM, Intel, Lenovo, National Semiconductor,
`
`NTRU, Softex, STMicroelectronics, Utimaco Safeware AG, Wave
`
`Systems) or the assignees of any patents or patent publications identified
`
`herein as prior art, and to supplement these contentions on that basis.
`
`4.
`
`The ’299 patent
`
` Xilinx XC6200 Series Field Programmable Gate Arrays (“XC6200”) as
`
`evidenced by the following, at least by July 15, 1996.
`o Xilinx, XC6200 Field Programmable Gate Arrays, Version 1.10 (Apr. 24,
`
`1997) (“XC6200 Datasheet”).
`o Reiner Hartenstein et al., Designing for Xilinx XC6200 FPGAs (Aug. 31,
`
`1998) (“Hartenstein”).
`o Mark L. Chang, et al., Modern FPGA Basics: the Xilinx XC6200 clip, the
`
`software tools and the board development tools (“Chang”).
`o Xilinx, The Programmable Logic Data Book, Version 1.01 (July 15, 1996)
`
`(“1996 Data Book”).
`
` Xilinx Xilinx XC3000 Series Field Programmable Gate Arrays (“XC3000”) as
`
`evidenced by the following, at least by February 28, 1997.
`o Xilinx, XC3000 Series Field Programmable Gate Arrays, Version 3.1
`
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`(Nov. 9, 1998) (“XC3000 Datasheet”).
`o Peter Alfke et al., XC3000 Series Technical Information, Xilinx, Version
`
`1.0 (Nov. 24, 1997) (“XAPP 024”).
`o Peter Alfke, Configuration Issues: Power-up, Volatility, Security, Battery
`
`Back-up, Xilinx, Version 1.1 (Nov. 24, 1997) (“XAPP 092”)
`o Xilinx Lowers the Cost of XC3000 Performance, EE Times (Jul. 15, 1996)
`
`(“1996 Data Book”).
`
` Xilinx Virtex-II Series Field Programmable Gate Arrays (“Virtex-II”) as
`
`evidenced by the following, at least by January 15, 2001.
`o Xilinx, Virtex-II 1.5V Field Programmable Gate Arrays, Version 1.9 (Sep.
`
`26. 2002) (“Virtex-II Datasheet”).
`o Brandon Blodget et al., Partial and Dynamically Reconfiguration of Xilinx
`
`Virtex-II FPGAs, LECTURE NOTES IN COMPUTER SCIENCE, Vol. 3203
`
`(2004) (“Blodget”).
`o C.C. Yui et al., SEU Mitigation Testing of Xilinx Virtex II FPGAs, 2003
`
`IEEE Radiation Effects Data Workshop (Jul. 25, 2003) (“Yui”).
`o Xilinx, Xilinx Virtex-II FPGAs Launch New Era of Digital Design (Jan.
`
`15, 2001), available at
`
`http://ebook.pldworld.com/_Semiconductors/XILINX/DataSource%20CD
`
`-ROM/Rev.3%20(Q1-
`
`2001)/documents/www.xilinx.com/prs_rls/vtx2ship.htm (“Virtex-II Press
`
`Release”).
`
` Actel MX Family Field Programmable Gate Arrays (“Actel MX”) as evidence by
`
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`at least January 6, 1998.
`o Actel, 40MX and 42MX FPGA Families, Version 5.0 (Feb. 2001) (“MX
`
`Datasheet”).
`o Actel, Benefits of the MX Family of Devices, (Sep. 1998) (“MX Note”).
`o Actel Announces Fastest MX Family Device, EE TIMES (Jan. 7, 1998)
`
`available at https://www.eetimes.com/actel-announces-fastest-mx-family-
`
`device/# (“Actel Article”).
`
` Altera Flex Series Programmable Logic Devices (“Altera Flex”), as evidence by
`
`the following, at least by January 7, 1998.
`o Altera, Flex 10K Embedded Programmable Logic Family, Ver 3.13 (Oct.
`
`1998) (“Flex 10K Datasheet”)
`o Altera Ships 200,000-Gate Flex 10K Device with Enhanced Features, EE
`
`TIMES (Dec. 17, 1998) available at https://www.eetimes.com/altera-ships-
`
`200000-gate-flex-10k-device-with-enhanced-features/# (“Altera Article”).
`o Amir Masoud Gharehbaghi, Digital System Design Lecture 7: Altera
`
`FPGAs, Sharif University of Technology (“Masoud”).
`o Altera, Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices, ver.
`
`1.03 (May 2000) (“Altera Note”).
`
` Additional products pending the commencement of fact discovery.
`
`5.
`
`The ’619 patent
`
` AMD Opteron™ Processor, as evidenced by the following at least by April 2003.
`o The AMD OpteronTM Processor Data Sheet, Publication # 23932,
`
`Revision 3.00, April 2003.
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`o The AMD Opteron Processor for Multiprocessor Servers, by Keltcher et
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`al. in IEEE Micro (Volume: 23, Issue: 2, March-April 2003).
`o AMD x86-64 Architecture Programmer’s Manual, Volume 2: System
`
`Programing, Publication No. 24593, Revision 3.11, December 2005.
`
` Additional products pending the commencement of fact discovery.
`
`6.
`
`The ’033 patent
`
` Prior art methods and processes developed and/or practiced by the assignees of
`
`each of the references listed above in Section I.A.6, and by third parties practicing
`
`or using those methods and processes.
`
` Additional products pending the commencement of fact discovery, including but
`
`not limited to Texas Instruments, Inc., Micron Technology, Inc., Applied
`
`Materials, Inc., KLA-Tencor Corporation, Matsushita Electric Industrial Co.,
`
`United Microelectronics Corporation, Taiwan Semiconductor Manufacturing
`
`Company, Ltd., GlobalFoundries, Inc., Cypress Semiconductor Corporation,
`
`Renesas Electronics Corporation, Integrated Silicon Solution Inc., GSI
`
`Technology Inc., Integrated Device Technology, Inc., Samsung Semiconductor,
`
`and any of their successors, predecessors, or affiliates.
`
`II.
`
`STATEMENT OF ANTICIPATION AND OBVIOUSNESS
`A.
`Anticipation of the Asserted Claims
`
`The asserted claims are invalid under 35 U.S.C. § 102 as being anticipated by the
`
`individual prior art references presented in Section I. Single items of prior art that anticipate the
`
`asserted claims of the asserted patents are cited and described in the claim charts attached hereto
`
`as Exhibits A-1‒A-4, B-1‒B-3, C-1‒C-7, D-1‒D-7, E-1‒E-4, and F-1‒F-3. These claim charts
`
`provide citations to portions of the above references, illustrating how the prior art explicitly
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`discloses every element of the asserted claims. To the extent any element is not provided by an
`
`expressly enabling disclosure by the referenced prior art, the elements of the asserted claims
`
`would still be the inherent result of putting into practice the systems and methods described by
`
`the prior art referenced herein and/or obvious, as set forth below.
`
`B.
`
`Obviousness of the Asserted Claims
`
`In addition to the discussion above, and to the extent not anticipated, the asserted claims
`
`are invalid under 35 U.S.C. § 103 as obvious to a person of ordinary skill in the art (“POSITA”)
`
`of the relevant technology. In the event a particular prior art reference identified above in
`
`Section II does not anticipate one of the asserted claims, the reference, alone or in combination
`
`with one or more of the other references disclosed herein, renders the claim obvious. Items of
`
`prior art that render obvious the asserted claims of the asserted patents are cited and described in
`
`the claim charts attached as Exhibits A-1‒A-4, B-1‒B-3, C-1‒C-7, D-1‒D-7, E-1‒E-4, and F-1‒
`
`F-3. The identification of certain combinations of prior art does not exclude other combinations
`
`and is without prejudice to Microchip’s right to rely on additional specific combinations as well
`
`as to detail and explain such combinations. Moreover, to the extent a particular prior art
`
`reference identified above in Section I does not anticipate one of the asserted claims, the
`
`reference, alone or in combination with the knowledge of a person having ordinary skill in the
`
`relevant art, renders the claim obvious.
`
`Microchip further believes that no showing of a specific motivation to combine prior art
`
`is required to combine the references disclosed above, as each combination of prior art would
`
`have no unexpected result, and at most would simply represent a known alternative to one of
`
`ordinary skill in the art. See KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 415–18 (2007)
`
`(rejecting the Federal Circuit’s “rigid” application of the teaching, suggestion, or motivation to
`
`combine test, instead espousing an “expansive and flexible” approach). The Supreme Court held
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`that a person of ordinary skill in the art is “a person of ordinary creativity, not an automaton” and
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`“in many cases a person of ordinary skill will be able to fit the teachings of multiple patents
`
`together like pieces of a puzzle.” Id. at 420–21. Nevertheless, in addition to the other
`
`information contained herein, Microchip hereby identifies various motivations and reasons to
`
`combine the cited art.
`
`Clear and logical rationale to combine any of the references identified above in Section I
`
`with others exists from the prior art references themselves, as well as from common knowledge,
`
`common sense, predictability, expectations, industry trends, design incentives or need, market
`
`demand or pressure, market forces, obviousness to try, the nature of the problem faced, and/or
`
`knowledge possessed by a person of ordinary skill. Microchip reserves the right to rely on the
`
`knowledge of those skilled in the art, the testimony of expert witnesses, and/or other prior art, to
`
`show that it would have been obvious to include the allegedly missing limitation(s) and to
`
`explain the motivation(s) to combine the prior art element(s).
`
`Moreover, some of the cited works of prior art cross-reference and discuss one another,
`
`further illustrating the close relationship among them and providing the motivation to combine
`
`the innovations these references disclose. At most, the claimed inventions of the asserted patents
`
`were nothing more than the obvious combination of familiar elements, yielding entirely
`
`predictable results.
`
`If and to the extent HDSS challenges the correspondence of any of these references to
`
`particular elements of the respective asserted claims, Microchip reserves the right to supplement
`
`these contentions to identify with additional particularity motivation to combine references with
`
`one another. Microchip may rely upon a subset of combined references depending upon the
`
`Court’s claim construction and upon further investigation.
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`III. GROUNDS FOR INVALIDITY UNDER SECTIONS 101 AND 112
`A.
`35 U.S.C. § 101: Subject Matter Eligibility
`
`To meet the requirements of 35 U.S.C. § 101, a patent may generally be granted for “any
`
`new and useful process, machine, manufacture, or composition of matter” or any improvement
`
`thereof. Because the claims of the asserted patents are directed to an abstract idea and (2) the
`
`elements of the claims—both individually and as ordered combinations—fail to transform the
`
`nature of the claims into a patent- eligible application of the abstract idea, one or more of the
`
`asserted claims are invalid for failing to claim patent-eligible subject matter. Alice Corp. Pty.
`
`Ltd. v. CLS Bank Int’l, 573 U.S. 208 (2014).
`
`1.
`
`The ’002 patent
`
`Each of the Asserted Claims of the ’002 patent are invalid as directed to ineligible subject
`
`matter under Section 101. The Asserted Claims claim no more than the abstract idea of
`
`providing security by verifying a password. That the Asserted Claims recite computer specific
`
`terms (such as scan interfaces, secure processors, and the like) does not alter this conclusion;
`
`rather, they merely specify a technological environment for practicing the abstract idea of
`
`password protection, rather than an actual improvement to the underlying technology. See BSG
`
`Tech, 899 F.3d at 1286-87; Customedia Techs., 951 F.3d at 1364-65.
`
`The claims also contain no inventive concepts that would transform these abstract ideas
`
`into patentable subject matter. A claimed invention’s use of the ineligible concept to which it is
`
`directed cannot supply the inventive concept that renders the invention “significantly more” than
`
`that ineligible concept. BSG Tech, 899 F.3d at 1290-91. “Nor, in addressing the second step
`
`of Alice, does claiming the improved speed or efficiency inherent with applying the abstract idea
`
`on a computer provide a sufficient inventive concept.” Intellectual Ventures I LLC v. Capital One
`
`Bank (USA), 792 F.3d 1363, 1367 (Fed. Cir. 2015). Here, setting aside the abstract idea of
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`password protection itself, the Asserted Claims claim no more than the improved speed or
`
`efficiency inherent with applying the abstract idea on a computer or in a known technological
`
`environment. The Asserted Claims do not, for example, discuss improvements to, for example,
`
`scan-chain technology or secure processors.
`
`District Courts and the Federal Circuit have invalidated claims under similar facts. See,
`
`e.g., Prism Techs. LLC v. T-Mobile USA, Inc., 696 F. App’x 1014, 1017 (Fed. Cir. 2017)
`
`(“T-Mobile argues that the asserted claims recite ineligible subject matter because they: (1) are
`
`directed to the abstract idea of controlling access to resources; and (2) are non-inventive because
`
`they recite generic computer hardware running generic computer software that performs the
`
`abstract functions routine to the process of restricting access. We agree.”); StrikeForce Techs., Inc.
`
`v. SecureAuth Corp., No. LACV1704314JAKSKX, 2017 WL 8808122, at *6 (C.D. Cal. Dec. 1,
`
`2017), aff'd, 753 F. App'x 914 (Fed. Cir. 2019) (“A consideration of the existing in-band and out-
`
`of-band authentication systems and
`
`long-established, non-computer-based methods for
`
`transmitting, processing and authenticating sensitive data shows that the Asserted Claims are not
`
`specifically directed to an improvement in computer functionality. Instead, they simply apply these
`
`familiar processes in the context of the use of computers that are connected to the internet.”);
`
`Universal Secure Registry LLC v. Apple Inc., 469 F. Supp. 3d 231, 240 (D. Del. 2020) (claim
`
`directed to “[a] system for authenticating a user for enabling a transaction” and accomplished using
`
`generic components was not patentable subject matter); Twilio, Inc. v. Telesign Corp., 249 F. Supp.
`
`3d 1123, 1157 (N.D. Cal. 2017) (“Claim 1 recites the broad concept of authentication that is
`
`untethered to any specific means of implementing it—it only requires a determination that the
`
`‘account identifier is valid.’ . . . Thus, even with the additional requirement of “determining
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`whether the account identifier [of the external system] is valid,” claim 1 is directed to an abstract
`
`i