Preliminary Information
`
`TM
`
`AMD Athlon
`Processor Module
`Data Sheet
`
`Publication # 21016
`Issue Date: June 2000
`
`Rev: M
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 1 of 74
`
`

`

`Preliminary Information
`
`© 2000 Advanced Micro Devices, Inc. All rights reserved.
`The contents of this document are provided in connection with Advanced
`Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
`warranties with respect to the accuracy or completeness of the contents of
`this publication and reserves the right to make changes to specifications and
`product descriptions at any time without notice. No license, whether express,
`implied, arising by estoppel or otherwise, to any intellectual property rights
`is granted by this publication. Except as set forth in AMD’s Standard Terms
`and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
`any express or implied warranty, relating to its products including, but not
`limited to, the implied warranty of merchantability, fitness for a particular
`purpose, or infringement of any intellectual property right.
`
`AMD’s products are not designed, intended, authorized or warranted for use
`as components in systems intended for surgical implant into the body, or in
`other applications intended to support or sustain life, or in any other applica-
`tion in which the failure of AMD’s product could create a situation where per-
`sonal injury, death, or severe property or environmental damage may occur.
`AMD reserves the right to discontinue or make changes to its products at any
`time without notice.
`
`Trademarks
`AMD, the AMD logo, AMD Athlon, and combinations thereof, 3DNow!, AMD-751, and AMD-756 are trademarks
`of Advanced Micro Devices, Inc.
`
`MMX is a trademark of Intel Corporation.
`
`Digital and Alpha are trademarks of Digital Equipment Corporation.
`
`Other product names used in this publication are for identification purposes only and may be trademarks of
`their respective companies.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
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`Preliminary Information
`
`AMD Athlon™ Processor Module Data Sheet
`
`21016M/0—June 2000
`
`Contents
`
`Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
`
`1
`
`2
`
`3
`4
`
`5
`6
`
`4.2
`
`About This Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
`Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
`1.1
`AMD Athlon™ Processor Microarchitecture Summary . . . . . 5
`Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
`2.1
`Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
`2.2
`Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
`2.3
`AMD Athlon System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 8
`Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
`Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`4.1
`Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
`Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 15
`Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
`Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
`Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`6.1
`The AMD Athlon System Bus . . . . . . . . . . . . . . . . . . . . . . . . . 23
`6.2
`Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`Clock Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
`Voltage Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`Frequency Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`OD Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`CLKFWD Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`SYSCLK, SYSCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`6.7
`Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`6.8
`Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`6.9
`6.10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`6.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
`6.12
`Southbridge AC and DC Characteristics . . . . . . . . . . . . . . . . 35
`6.13 APIC Pin AC and DC Characteristics . . . . . . . . . . . . . . . . . . . 37
`6.14
`Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . 37
`
`6.3
`6.4
`6.5
`6.6
`
`Contents
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`AMD Athlon™ Processor Module Data Sheet
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`21016M/0—June 2000
`
`Preliminary Information
`
`7
`
`8
`
`Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`7.1
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`7.2
`Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`7.3
`AMD Athlon Processor Card-Edge Signal Listing . . . . . . . . . 45
`Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`Standard AMD Athlon Processor Products . . . . . . . . . . . . . . . . . . . . 53
`Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . 57
`Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s63
`
`iv
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`Contents
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`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`List of Figures
`
`Figure 1.
`
`Typical AMD Athlon™ Processor System Block Diagram . . . . . 6
`
`Figure 2.
`
`Logic Symbol Diagram for AMD Athlon Processor . . . . . . . . . 11
`
`Figure 3. AMD Athlon Processor Power Management States . . . . . . . . . 13
`
`Figure 4.
`
`Example System Bus Disconnection Sequence . . . . . . . . . . . . . 17
`
`Figure 5.
`
`Exiting Stop Grant State/Bus Reconnection Sequence . . . . . . 18
`
`Figure 6.
`
`System Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`
`Figure 7.
`
`Processor Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
`
`Figure 8.
`
`Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
`
`Figure 9. AMD Athlon Processor Module Dimensions—Front View . . . 40
`
`Figure 10. AMD Athlon Processor Module Dimensions—Plate Side
`View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
`
`Figure 11. AMD Athlon Processor Module Dimensions—Side View . . . . 42
`
`Figure 12. AMD Athlon Processor Module Dimensions—Edge View. . . . 42
`
`Figure 13. Card Edge Dimensions—Thermal Plate Side View . . . . . . . . . 43
`
`Figure 14. Card Edge Dimensions (Detail) . . . . . . . . . . . . . . . . . . . . . . . . . 44
`
`Figure 15. OPN Example for the AMD Athlon Processor Model 2 . . . . . . 53
`
`Figure 16. OPN Example for the AMD Athlon Processor Model 4 . . . . . . 54
`
`List of Figures
`
`v
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`Preliminary Information
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`List of Figures
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`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
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`Preliminary Information
`
`List of Tables
`
`Pin-Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
`Table 1.
`AMD Athlon™ System Bus and Legacy Interface Signals . . . . . 8
`Table 2.
`AMD Athlon Processor Power Management States . . . . . . . . . 16
`Table 3.
`AMD Athlon Processor Interface Signal Groupings . . . . . . . . . 24
`Table 4.
`Source-Synchronous Clock Signal Groups . . . . . . . . . . . . . . . . . 24
`Table 5.
`Voltage ID Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`Table 6.
`Signal and Clock Layout and Termination Requirements. . . . 26
`Table 7.
`Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`Table 8.
`Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`Table 9.
`Table 10. VCC_CORE Power and Current for Model 1, Model 2, and
`Model 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`Table 11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Table 12. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
`Table 13.
`Southbridge AC and DC Characteristics . . . . . . . . . . . . . . . . . . 35
`Table 14. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 37
`Table 15. AMD Athlon Processor Module Dimensions . . . . . . . . . . . . . . . 39
`Table 16. Notes for Dimension Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`Table 17. AMD Athlon Processor Signals Ordered by Pin Number. . . . . 45
`Table 18. AMD Athlon Processor Signals Ordered by Pin Name. . . . . . . 48
`Table 19. AMD Athlon Processor Signals Ordered by Physical
`Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
`Table 20. Valid Ordering Part Number Combinations for Model 1. . . . . 55
`Table 21. Valid Ordering Part Number Combinations for Model 2. . . . . 55
`Table 22. Valid Ordering Part Number Combinations for Model 4. . . . . 56
`Table 23. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`Table 24. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`
`List of Tables
`
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`21016M/0—June 2000
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`Preliminary Information
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`viii
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`List of Tables
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`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`Revision History
`
`Date
`
`Rev
`
`June 2000
`
`M
`
`May 2000
`
`March 2000
`
`L
`
`K
`
`February 2000
`
`J
`
`February 2000
`
`I
`
`Description
`Added information about the AMD Athlon™ processor Model 4 to the following chapters:
`I “About This Data Sheet” on page 1.
`I Chapter 1, “Overview” on page 3.
`I Chapter 6, “Electrical Data” on page 23.
`I Chapter 8, “Ordering Information” on page 53.
`Revised SADDIN and SADDOUT information in Chapter 3, “Logic Symbol Diagram” on page 11.
`Added “Signal and Power-Up Requirements” on page 37.
`Revised Chapter 5, “Thermal Design” on page 21.
`Non-public version
`Added information about the 950-MHz AMD Athlon processor in the following tables:
`I Table 10, “VCC_CORE Power and Current for Model 1, Model 2, and Model 4,” on page 30
`I Table 21, “Valid Ordering Part Number Combinations for Model 2,” on page 55
`Revised information about the 900-MHz and 1-GHz (1000 MHz) AMD Athlon processor in Table 21,
`“Valid Ordering Part Number Combinations for Model 2,” on page 55.
`Added information about the 900-MHz and 1-GHz (1000 MHz) AMD Athlon processor in the
`following chapters:
`I In Chapter 1, “Overview” on page 3.
`I In Chapter 6, “Electrical Data” on page 23 in the following tables:
`Table 8, “Operating Ranges,” on page 28
`Table 10, “VCC_CORE Power and Current for Model 1, Model 2, and Model 4,” on page 30
`Table 11, “DC Characteristics,” on page 32
`I
`I Chapter 8, “Ordering Information” on page 53.
`Added information about the 850-MHz AMD Athlon processor in the following chapters:
`I In Chapter 1, “Overview” on page 3.
`I In Chapter 6, “Electrical Data” on page 23 in the following tables:
`Table 8, “Operating Ranges,” on page 28
`Table 10, “Typical and Maximum Power Dissipation for Model 2—Part One,” on page 31
`Table 11, “DC Characteristics,” on page 32
`I
`I Chapter 8, “Ordering Information” on page 53.
`Reorganized entire book by merging Part One and Part Two together to integrate Model 2 and
`Model 1 information.
`Revised Power Supply Current Maximum values for 550-MHz through 800-MHz Model 2
`processors in Table 11, “DC Characteristics,” on page 32.
`Revised Power Supply Current Maximum values Model 1processors in Table 14, “DC
`Characteristics for Model 1,” on page 34.
`
`I
`
`I
`
`I
`
`I
`
`Revision History
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`AMD Athlon™ Processor Module Data Sheet
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`21016M/0—June 2000
`
`Preliminary Information
`
`Date
`
`Rev
`
`January 2000
`
`H
`
`December 1999
`
`G
`
`October 1999
`
`F
`
`August 1999
`
`August 1999
`
`E
`
`D
`
`I
`
`I
`
`Description
`Added information about the 800-MHz AMD Athlon processor in the following chapters:
`I In Chapter 14, “Electrical Data” on page 65 in the following tables:
`Table 23, “Operating Ranges,” on page 68
`Table 25, “Typical and Maximum Power Dissipation (Model 2),” on page 69
`Table 26, “DC Characteristics (Model 2),” on page 70
`I
`I In Chapter 16, “Ordering Information” on page 81.
`Changed the value of pullup resistors from 68-ohms to 47-ohms in the “Termination” section
`starting on page 24, Table 7, “Signal and Clock Layout and Termination Requirements,” on page
`24, and Figure 8, “Test Circuit” on page 31.
`Revised the maximum thermal power values for all Model 2 processors in Table 25, “Typical and
`Maximum Power Dissipation (Model 2),” on page 69.
`Divided book into Part One and Part Two. Part One provides information about the AMD Athlon™
`processor family (Model 1 and Model 2), and Part Two provides information specific to the
`AMD Athlon processor Model 2 (0.18-micron process technology).
`Revisions to Part One:
`In Chapter 6, “Electrical Data” on page 21:
`I Expanded information in the “Termination” section starting on page 24, including the addition
`of Table 7, “Signal and Clock Layout and Termination Requirements”.
`I Revised maximum rating in Table 9, “Absolute Ratings,” on page 26.
`I Revised Stop Grant values in Table 10, “Typical and Maximum Power Dissipation (Model 1),” on
`page 27.
`I Added ICC values and notes 7 and 8 to Table 11, “DC Characteristics (Model 1),” on page 28.
`In Chapter 7, “Mechanical Data” on page 33, added # to SCHECK[2]# and SCHECK[7]# in signal
`Tables 15, 16, and 17 starting on page 39.
`Added the 700 MHz AMD Athlon™ processor to Table 10, “Typical and Maximum Power
`Dissipation (Model 1),” on page 27 and Table 18, “Valid Ordering Part Number Combinations,” on
`page 47.
`Revised Table 11, “DC Characteristics (Model 1),” on page 28 and Table 12, “AC Characteristics,” on
`page 30.
`Revised VCC_CORE minimum value from 1.4V to 1.5V in Table 8, “Operating Ranges,” on page 26.
`Revised information in Table 9, “Absolute Ratings,” on page 26.
`Revised information in Table 10, “Typical and Maximum Power Dissipation (Model 1),” on page 27.
`Initial public release
`
`x
`
`Revision History
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`21016M/0—June 2000
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`AMD Athlon™ Processor Module Data Sheet
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`Preliminary Information
`
`About This Data Sheet
`
`This AMD Athlon™ processor data sheet describes the technical specifications of the
`AMD Athlon processor family designed for the Slot A mechanical connector. The
`processor module may include either the AMD Athlon processor Model 1, Model 2, or
`Model 4. For more information about determining the Model number and features of
`an AMD Athlon processor module, see the AMD Processor Recognition Application
`Note, order# 20734 and the AMD Athlon Processor Revision Guide, order# 22557.
`
`For information about the PGA versions of the AMD Athlon processor, see the
`AMD Athlon™ Processor PGA Data Sheet, order#23792.
`
`About This Data Sheet
`
`1
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`AMD Athlon™ Processor Module Data Sheet
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`21016M/0—June 2000
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`Preliminary Information
`
`2
`
`About This Data Sheet
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`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`1
`
`Overview
`
`The AMD Athlon™ processor powers the next generation in
`computing platforms, delivering the ultimate performance for
`cutting-edge applications and an unprecedented computing
`experience.
`
`The AMD Athlon™ processor family continues to deliver
`leading-edge processor performance for high-performance
`desktop systems, workstations, and servers. The newest
`member of the AMD Athlon processor family integrates a
`high-performance, full-speed 256-Kbyte Level-Two (L2) cache.
`Achieving frequencies of 1-GHz (1000 MHz), the AMD Athlon
`processor is the world’s most powerful x86 processor, delivering
`the highest integer, floating-point and 3D multimedia
`performance for applications running on x86 system platforms.
`All AMD Athlon processors provide industry-leading processing
`power for cutting-edge software applications, including digital
`content creation, digital photo editing, digital video, image
`compression, video encoding for streaming over the internet,
`soft DVD, commercial 3D modeling, workstation-class
`computer-aided design (CAD), commercial desktop publishing,
`and speech recognition. It also offers the scalability and
`‘peace-of-mind’ reliability that IT managers and business users
`require for enterprise computing.
`
`The AMD Athlon processor family features the industry's first
`seventh-generation x86 microarchitecture, which is designed to
`support the growing processor and system bandwidth
`requirements of emerging software, graphics, I/O, and memory
`technologies. The AMD Athlon processor's nine-issue
`superpipelined microarchitecture includes multiple full x86
`instruction decoders, a high-performance cache architecture,
`three independent integer units, three address calculation
`units, and the x86 industry's first superscalar, fully pipelined,
`out-of-order, three-way floating-point unit. The floating-point
`unit is c apable of delivering 4 gigaflops (Gf lops) of
`single-precision and more than 2 Gflops of double-precision
`floating-point results at 1 GHz, for superior performance on
`numerically complex applications.
`
`Chapter 1
`
`Overview
`
`3
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`AMD Athlon™ Processor Module Data Sheet
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`21016M/0—June 2000
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`Preliminary Information
`
`Only the AMD Athlon processor microarchitecture incorporates
`Enhanced 3DNow!™ technology and the industry’s first
`200-MHz, 1.6-Gigabyte per second front-side bus (FSB)—the
`fastest system bus for x86 platforms.
`
`AMD’s Enhanced 3DNow! technology includes additional
`instructions to the popular 3DNow! instruction set. It consists of
`new integer multimedia instructions and software-directed
`data movement instructions for optimizing such applications as
`digital content creation and streaming video for the internet, as
`well as new instructions for digital signal processing
`(DSP)/communications applications.
`
`Based on the high-performance Alpha™ EV6 interface protocol
`licensed from Digital Equipment Corporation, the AMD Athlon
`system bus combines the latest technological advances, such as
`point-to-point topology, source-synchronous packet-based
`transfers, and low-voltage signaling, to provide the most
`powerful, scalable bus available for any x86 processor.
`
`The AMD Athlon processor is binary-compatible with existing
`x86 software and backwards compatible with applications
`optimized for MMX™ and 3DNow! instructions. Using a data
`format and single-instruction multiple-data (SIMD) operations
`based on the MMX instruction model, the AMD Athlon
`processor can produce as many as four, 32-bit, single-precision
`floating-point results per clock cycle, potentially resulting in
`4 Gflops at 1 GHz (fully scalable).
`
`The AMD Athlon processors are implemented in AMD’s
`advanced 0.18-micron process technology to achieve maximum
`performance and scalability.
`
`For information about the PGA versions of the AMD Athlon
`processor, see the AMD Athlon™ Processor PGA Data Sheet,
`order#23792.
`
`4
`
`Overview
`
`Chapter 1
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`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`1.1
`
`AMD Athlon™ Processor Microarchitecture Summary
`
`The following features summarize the AMD Athlon processor
`microarchitecture:
`I Nine-issue, superpipelined, superscalar x86 processor
`microarchitecture designed
`to achieve high
`clock
`frequencies
`I Multiple full x86 instruction decoders
`pipelined
`fully
`I Three
`out-of-order,
`superscalar,
`floating-point execution units, which execute all x87
`(floating-point), MMX, 3DNow!, and Enhanced 3DNow!
`instructions
`I Three out-of-order, superscalar, pipelined integer units and
`and three address calculation units
`I 72-entry instruction control unit
`I Advanced dynamic branch prediction
`I Enhanced 3DNow! technology
`I A 200-MHz AMD Athlon system bus (scalable beyond 400
`MHz) enabling leading-edge system bandwidth for data
`movement-intensive applications
`I High-performance cache architecture including a split
`128-Kbyte L1 cache, an integrated 256-Kbyte L2 cache
`(external 512-Kbyte L2 cache for Model 1 and Model 2), and
`a large dual-level, split Translation Look-aside Buffer (TLB)
`
`AMD is committed to delivering reliable, high-performance,
`and cost-effective solutions to its customers for all applications
`and configurations. The AMD Athlon processor continues to
`deliver superior system performance for systems from desktops
`to servers. Figure 1 on page 6 shows a typical AMD Athlon
`processor system block diagram.
`
`Chapter 1
`
`Overview
`
`5
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 15 of 74
`
`

`

`AMD Athlon™ Processor Module Data Sheet
`
`21016M/0—June 2000
`
`Preliminary Information
`
`AMD Athlon™
`
`Processor
`
`System
`
`Controller
`(Northbridge)
`
`
`
`Peripheral Bus
`Controller
`(Southbridge)
`
`AGP Bus
`
`Memory Bus
`
`PCI Bus
`
` AGP
`
`DRAM
`
` LAN
`
`SCSI
`
`ISA Bus
`
`BIOS
`
`USB
`
`Dual EIDE
`
`System
`Management
`
`Figure 1. Typical AMD Athlon™ Processor System Block Diagram
`
`6
`
`Overview
`
`Chapter 1
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 16 of 74
`
`

`

`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`2
`
`2.1
`
`Interface Signals
`
`Overview
`
`The AMD Athlon™ system bus architecture is designed to
`deliver unprecedented data movement bandwidth for
`next-generation x86 platforms, as well as the high performance
`required by enterprise-class application software. The system
`bus architecture consists of three high-speed channels (a
`unidirectional processor request channel, a unidirectional
`probe channel, and a 72-bit bidirectional data channel,
`including 8-bit error code correction [ECC] protection),
`source-synchronous clocking, and a packet-based protocol. In
`addition, the system bus supports several control, clock, and
`legacy signals. The interface signals use a HSTL-like,
`low-voltage swing signaling technology contained within the
`Slot A mechanical connector, which is mechanically compatible
`with the industry-standard SC242 connector.
`
`2.2
`
`Signaling Technology
`
`The AMD Athlon system bus uses a variation of the low-voltage,
`JEDEC HSTL signaling technology, which has been enhanced
`to provide larger noise margins, reduced ringing, and variable
`voltage levels. The signals are open-drained and require
`termination to a supply that provides the High signal level. The
`HSTL+ inputs use differential receivers, which require a
`reference voltage (VREF). The reference signal is used by the
`receivers to determine if a signal is asserted or deasserted by
`the source. Termination resistors are placed at both ends of the
`interface and are used to provide the High signal level and to
`control reflections on the interface.
`
`Chapter 2
`
`Interface Signals
`
`7
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 17 of 74
`
`

`

`AMD Athlon™ Processor Module Data Sheet
`
`21016M/0—June 2000
`
`Preliminary Information
`
`2.3
`
`AMD Athlon™ System Bus Signals
`
`Table 2 on page 8 shows the AMD Athlon system bus signals
`and legacy interface signals. Table 1 shows the pin-type
`definitions used in the Type column of Table 2. Signals with
`pound signs (#) are active Low.
`
`Table 1.
`
`Pin-Type Definitions
`
`Mnemonic
`I
`O
`I/O
`
`OD
`
`PP
`
`Definition
`Standard input pin to the processor
`Standard output pin from the processor
`Bidirectional, three-state input/output pin
`Open-drain structure that allows multiple devices to share the
`pin in a wired-OR configuration
`Push/Pull structure driven by a single source
`
`Table 2.
`
`AMD Athlon™ System Bus and Legacy Interface Signals
`
`Signal Name
`
`Type
`
`Level
`
`Number
`of Pins
`
`Description
`
`A20M#
`
`CLKFWDRST
`
`CONNECT
`
`COREFB+
`COREFB–
`
`FERR
`
`FID[3:0]
`
`IGNNE#
`
`INIT#
`
`Note:
`*
`
`8
`
`I
`
`I
`
`I
`
`O
`
`O
`
`O
`
`I
`
`I
`
`OD
`
`OD
`
`OD
`
`PP
`
`OD
`
`OD
`
`OD
`
`OD
`
`1
`
`1
`
`1
`
`2
`
`1
`
`4
`
`1
`
`1
`
`A20M# is an input from the system used to simulate address
`wrapping around in the 20-bit 8086.
`CLKFWDRST resets clock-forward circuitry for both the system
`and processor.
`CONNECT is an input from the system used for power
`management and clock-forward initialization at reset.
`
`COREFB+ and COREFB– are outputs to the system that provide
`AMD Athlon processor core voltage feedback to the system.
`FERR is an output to the system that is asserted for any
`unmasked numerical exception independent of the NE bit in
`CR0.
`The FID[3:0] signals are outputs to the system that report the
`multiplier used on the system clock (SYSCLK) producing the
`AMD Athlon processor core clock.
`IGNNE# is an input from the system that tells the processor to
`ignore numeric errors.
`INIT# is an input from the system that resets the integer
`registers without affecting the floating-point registers or the
`internal caches. Execution starts at 0FFFF FFF0h.
`
`The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
`
`Interface Signals
`
`Chapter 2
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 18 of 74
`
`

`

`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`Table 2.
`
`AMD Athlon™ System Bus and Legacy Interface Signals (continued)
`
`Signal Name
`
`Type
`
`Level
`
`Number
`of Pins
`
`Description
`
`INTR
`
`NMI
`
`PICCLK*
`
`PICD[1:0]#*
`
`PROCRDY
`
`PWROK
`
`RESET#
`
`SADDIN[14:2]#
`
`SADDINCLK#
`
`SADDOUT[14:2]#
`
`SADDOUTCLK#
`
`SCHECK[7:0]#
`
`SDATA[63:0]#
`
`SDATAINCLK[3:0]#
`
`SDATAINVAL#
`
`I
`
`I
`
`I
`
`I
`
`O
`
`I
`
`I
`
`I
`
`I
`
`O
`
`O
`
`I/O
`
`I/O
`
`I
`
`I
`
`OD
`
`OD
`
`PP
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`1
`
`1
`
`1
`
`2
`
`1
`
`1
`
`1
`
`13
`
`1
`
`13
`
`1
`
`8
`
`64
`
`4
`
`1
`
`INTR is an input from the system that causes the processor to
`start an interrupt acknowledge transaction that fetches the
`8-bit interrupt vector and starts execution at that location.
`NMI is an input from the system that causes a non-maskable
`interrupt.
`PICCLK is an input clock that is required for operation of the
`APIC bus.
`PICD[1:0]# are bidirectional signals that are used by the APIC
`bus, and must be connected to all APIC data pins on all devices
`of the APIC bus.
`PROCRDY is an output to the system and is used for power
`management and source-synchronous clock initialization at
`reset.
`PWROK is an input from the system indicating that the core
`power is within specified limits.
`RESET# is an input from the system that initializes and resets
`the processor and invalidates cache blocks.
`SADDIN[14:2]# is the unidirectional system probe and data
`movement command channel from the system.
`SADDINCLK# is the single-ended source-synchronous clock for
`SADDIN[14:2]# and is driven by the system.
`SADDOUT[14:2]# is the unidirectional processor request
`channel to the system. It is used to transfer processor requests
`or probe responses to the system.
`SADDOUTCLK# is the single-ended source-synchronous clock
`for SADDOUT[14:2]# driven by the processor.
`SCHECK[7:0]# contain the ECC bits for data transfers on
`SDATA[63:0]#.
`SDATA[63:0]# is the bidirectional channel between the
`processor and system for data movement.
`SDATAINCLK[3:0]# is the single-ended forwarded clock driven
`by the system to transfer data on SDATA[63:0]#. Each 16-bit
`data word is skewed-aligned with this clock.
`SDATAINVAL# is driven by the system to pace the data into the
`processor. SDATAINVAL# can be used to introduce an arbitrary
`number of cycles between octawords into the processor.
`
`Note:
`*
`
`The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
`
`Chapter 2
`
`Interface Signals
`
`9
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 19 of 74
`
`

`

`AMD Athlon™ Processor Module Data Sheet
`
`21016M/0—June 2000
`
`Preliminary Information
`
`Table 2.
`
`AMD Athlon™ System Bus and Legacy Interface Signals (continued)
`
`Signal Name
`
`Type
`
`Level
`
`Number
`of Pins
`
`Description
`
`SDATAOUTCLK[3:0]#
`
`O
`
`OD
`
`SDATAOUTVAL#
`
`SFILLVAL#
`
`SMI#
`
`STPCLK#
`
`SYSCLK
`SYSCLK#
`
`VCC2SEL
`
`VID[3:0]
`
`I
`
`I
`
`I
`
`I
`
`I
`
`O
`
`O
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`OD
`
`SDATAOUTCLK[3:0]# is the single-ended source-synchronous
`clock driven by the processor to transfer data on
`SDATA[63:0]#. Each 16-bit data word on SDATA[63:0]# is
`skewed-aligned with this clock.
`SDATAOUTVAL# is driven by the system to pace the data from
`the processor. SDATAOUTVAL# can be used to introduce an
`arbitrary number of cycles between quadwords from the
`processor.
`SFILLVAL# validates a data transfer to the processor. The
`system may tie this pin to the asserted state (validating all fills).
`The processor samples SFILLVAL# at the first or second data
`beat.
`SMI# is an input that causes the processor to enter the system
`management mode.
`STPCLK# is an input that causes the processor to enter a lower
`power mode and issue a Stop Grant special cycle.
`SYSCLK and SYSCLK# are differential input clock signals
`provided to the processor’s PLL from a system-clock generator.
`VCC2SEL is an output to the system that indicates the required
`core voltage for the L2 SRAM. High=2.5V, Low=3.3V.
`The VID[3:0] signals are outputs to the motherboard that
`indicate the required VCC_CORE voltage for the processor.
`
`4
`
`1
`
`1
`
`1
`
`1
`
`2
`
`1
`
`4
`
`Note:
`*
`
`The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
`
`10
`
`Interface Signals
`
`Chapter 2
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 20 of 74
`
`

`

`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`3
`
`Logic Symbol Diagram
`
`
`
`Data
`
`Probe/SysCMD
`
`Request
`
`Power
`Management
`and Initialization
`
`SDATA[63:0]#
`SDATAINCLK[3:0]#
`SDATAOUTCLK[3:0]#
`SCHECK[7:0]#
`SDATAINVAL#
`SDATAOUTVAL#
` SFILLVAL#
`
`SADDIN[14:1]#
`SADDINCLK#
`
`SADDOUT[14:0]#
`SADDOUTCLK#
`
`PROCRDY
`CLKFWDRST
`CONNECT
`STPCLK#
`RESET#
`
`Clock
`
`SYSCLK
`
`SYSCLK#
`
`AMD Athlon™
`Processor
`
`VID[3:0]
` COREFB+
` COREFB–
` PWROK
` VCC2SEL
`
`FID[3:0]
`
` FERR
` IGNNE#
` INIT#
` INTR
` NMI
` A20M#
` SMI#
`
`Voltage
`Control
`
`Frequency
`Control
`
`Legacy
`
`*PICCLK
`*PICD[1:0]#
`
`APIC*
`
`Note:
`*
`
`The industry-standard APIC signals, PICCLK and
`PICD[1:0]#, are not available on Model 1.
`
`Figure 2. Logic Symbol Diagram for AMD Athlon™ Processor
`
`Chapter 3
`
`Logic Symbol Diagram
`
`11
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 21 of 74
`
`

`

`AMD Athlon™ Processor Module Data Sheet
`
`21016M/0—June 2000
`
`Preliminary Information
`
`12
`
`Logic Symbol Diagram
`
`Chapter 3
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1037
`Page 22 of 74
`
`

`

`21016M/0—June 2000
`
`AMD Athlon™ Processor Module Data Sheet
`
`Preliminary Information
`
`4
`
`4.1
`
`Power Management
`
`Power Management States
`
`The AMD Athlon™ processor uses multiple advanced power
`states to place the processor in reduced power modes. These
`power states are used to enhance processor performance,
`minimize power dissipation, and provide a b