`
`
`
`
`FEATURES
`250 ps propagation delay input to output
`50 ps propagation delay dispersion
`Differential ECL compatible outputs
`Differential latch control
`Robust input protection
`Input common-mode range −2.0 V to +3.0 V
`Input differential range ±5 V
`ESD protection >3 kV HBM, >200 V MM
`Power supply sensitivity > 65 dB
`200 ps minimum pulsewidth
`5 GHz equivalent input rise time bandwidth
`Typical output rise/fall of 165 ps
`
`APPLICATIONS
`High speed instrumentation
`Scope and logic analyzer front ends
`Window comparators
`High speed line receivers and signal restoration
`Threshold detection
`Peak detection
`High speed triggers
`Patient diagnostics
`Disk drive read channel detection
`Hand-held test instruments
`Zero-crossing detectors
`Clock drivers
`Automatic test equipment
`
`
`
`Dual Ultrafast
`Voltage Comparator
`ADCMP566
`
`FUNCTIONAL BLOCK DIAGRAM
`
`
`NONINVERTING
`INPUT
`
`INVERTING
`INPUT
`
`ADCMP566
`
`Q OUTPUT
`
`Q OUTPUT
`
`LATCH ENABLE
`INPUT
`
`LATCH ENABLE
`INPUT
`
`Figure 1.
`
`03633-0-001
`
`
`
`
`GENERAL DESCRIPTION
`The ADCMP566 is an ultrafast voltage comparator fabricated
`on Analog Devices’ proprietary XFCB process. The device
`features 250 ps propagation delay with less than 35 ps overdrive
`dispersion. Overdrive dispersion, a particularly important
`characteristic of high speed comparators, is a measure of the
`difference in propagation delay under differing overdrive
`conditions.
`
`A fast, high precision differential input stage permits consis-
`tent propagation delay with a wide variety of signals in the
`common-mode range from −2.0 V to +3.0 V. Outputs are
`complementary digital signals fully compatible with ECL 10 K
`and 10 KH logic families. The outputs provide sufficient drive
`current to directly drive transmission lines terminated in 50 Ω
`to −2 V. A latch input is included, which permits tracking,
`track-and-hold, or sample-and-hold modes of operation.
`
`The ADCMP566 is available in a 32-lead LFCSP package.
`
`Rev. 0
`Information furnished by Analog Devices is believed to be accurate and reliable.
`However, no responsibility is assumed by Analog Devices for its use, nor for any
`infringements of patents or other rights of third parties that may result from its use.
`Specifications subject to change without notice. No license is granted by implication
`or otherwise under any patent or patent rights of Analog Devices. Trademarks and
`registered trademarks are the property of their respective owners.
`
`
`
`
`
`One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
`Tel: 781.329.4700
`www.analog.com
`Fax: 781.326.8703
`© 2003 Analog Devices, Inc. All rights reserved.
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`
`
`TABLE OF CONTENTS
`Specifications..................................................................................... 3
`Absolute Maximum Ratings............................................................ 5
`Thermal Considerations.............................................................. 5
`ESD Caution.................................................................................. 5
`Pin Configuration and Function Descriptions............................. 6
`Timing Information ......................................................................... 8
`Application Information.................................................................. 9
`Clock Timing Recovery............................................................... 9
`
`
`
`REVISION HISTORY
`
`Revision 0: Initial Version
`
`Optimizing High Speed Performance ........................................9
`Comparator Propagation Delay Dispersion ..............................9
`Comparator Hysteresis .............................................................. 10
`Minimum Input Slew Rate Requirement................................ 10
`Typical Application Circuits ..................................................... 11
`Typical Performance Characteristics ........................................... 12
`Outline Dimensions....................................................................... 14
`Ordering Guide .......................................................................... 14
`
`Rev. 0 | Page 2 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`SPECIFICATIONS
`Table 1. ADCMP566 ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.)
`Parameter
`Symbol
`Condition
`Min
`Typ
`Max
`DC INPUT CHARACTERISTICS (See Note)
`
`
`
`
`
`Input Common-Mode Range
`VCM
`
`−2.0
`
`+3.0
`Input Differential Voltage
`
`
`−5
`
`+5
`Input Offset Voltage
`VOS
`
`−5.0
`±1.0
`+5.0
`Input Offset Voltage Channel Matching
`
`
`
`±1.0
`
`Offset Voltage Tempco
`DVOS/dT
`
`
`10.0
`
`Input Bias Current
`IBC
`
`−10
`+24
`+42
`Input Bias Current Tempco
`
`
`
`10.0
`
`Input Offset Current
`
`
`−8.0
`±0.5
`+8.0
`Input Capacitance
`CIN
`
`
`0.75
`
`Input Resistance, Differential Mode
`
`
`
`100
`
`Input Resistance, Common Mode
`
`
`
`600
`
`Open Loop Gain
`
`
`
`60
`
`Common-Mode Rejection Ratio
`CMRR
`VCM = −2.0 V to +3.0 V
`
`69
`
`Hysteresis
`
`
`
`±1.0
`
`LATCH ENABLE CHARACTERISTICS
`
`
`
`
`
`Latch Enable Common-Mode Range
`VLCM
`
`−2.0
`
`0
`Latch Enable Differential Input Voltage
`VLD
`
`0.4
`
`2.0
`Input High Current
`
`@ 0.0 V
`−12
`+6
`+12
`Input Low Current
`
`@ −2.0 V
`−12
`+6
`+12
`Latch Setup Time
`tS
`250 mV overdrive
`
`50
`
`Latch to Output Delay
`tPLOH, tPLOL
`250 mV overdrive
`
`250
`
`Latch Pulsewidth
`tPL
`250 mV overdrive
`
`150
`
`Latch Hold Time
`tH
`250 mV overdrive
`
`75
`
`OUTPUT CHARACTERISTICS
`
`
`
`
`
`Output Voltage—High Level
`VOH
`ECL 50 Ω to −2.0 V
`−1.06
`
`−0.81
`Output Voltage—Low Level
`VOL
`ECL 50 Ω to −2.0 V
`−1.95
`
`−1.65
`Rise Time
`tR
`20% to 80%
`
`170
`
`Fall Time
`tF
`20% to 80%
`
`140
`
`AC PERFORMANCE
`
`
`
`
`
`Propagation Delay
`tPD
`1 V overdrive
`
`240
`
`Propagation Delay
`tPD
`20 mV overdrive
`
`290
`
`Propagation Delay Tempco
`
`
`
`0.5
`
`
`
`
`±10
`
`Prop Delay Skew—Rising Transition to
`Falling Transition
`Within Device Propagation Delay Skew—
`Channel to Channel
`Propagation Delay Dispersion vs.
`Duty Cycle
`Propagation Delay Dispersion vs.
`Overdrive
`Propagation Delay Dispersion vs.
`Overdrive
`Propagation Delay Dispersion vs.
`Slew Rate
`
`
`
`
`
`
`
`
`
`
`
`Propagation Delay Dispersion vs.
`Common-Mode Voltage
`Equivalent Input Rise Time Bandwidth
`
`
`
`BW
`
`
`
`ADCMP566
`
`
`
`Unit
`
`V
`V
`mV
`mV
`µV/°C
`µA
`nA/°C
`µA
`pF
`kΩ
`kΩ
`dB
`dB
`mV
`
`V
`V
`µA
`µA
`ps
`ps
`ps
`ps
`
`V
`V
`ps
`ps
`
`ps
`ps
`ps/°C
`ps
`
`ps
`
`ps
`
`ps
`
`ps
`
`ps
`
`ps
`
`MHz
`
`
`
`
`
`
`
`
`
`
`
`±10
`
`±10
`
`35
`
`50
`
`50
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5
`
`5000
`
`
`
`
`
`
`
`1 MHz, 1 ns tR, tF
`
`50 mV to 1.5 V
`
`20 mV to 1.5 V
`
`0 V to 1 V swing,
`20% to 80%,
`50 and 600 ps tR, tF
`1 V swing,
`−1.5 V to 2.5 VCM
`0 V to 1 V swing,
`20% to 80%,
`50 ps tR, tF
`
`Rev. 0 | Page 3 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`
`
`Parameter
`AC PERFORMANCE (continued)
`Toggle Rate
`Minimum Pulsewidth
`
`Symbol
`
`
`PW
`
`Unit to Unit Propagation Delay Skew
`POWER SUPPLY
`Positive Supply Current
`Negative Supply Current
`Positive Supply Voltage
`Negative Supply Voltage
`Power Dissipation
`Power Dissipation
`Power Supply Sensitivity—VCC
`Power Supply Sensitivity—VEE
`
`
`
`IVCC
`IVEE
`VCC
`VEE
`
`
`PSSVCC
`PSSVEE
`NOTE: Under no circumstances should the input voltages exceed the supply voltages.
`
`
`Condition
`
`>50% output swing
`∆tpd from 10 ns to
`200 ps < ±25 ps
`
`
`@ +5.0 V
`@ −5.2 V
`Dual
`Dual
`Dual, without load
`Dual, with load
`
`
`
`Min
`
`
`
`
`
`
`9
`60
`4.75
`−4.96
`375
`
`
`
`
`Typ
`
`5
`200
`
`±10
`
`13
`70
`5.0
`−5.2
`450
`550
`68
`85
`
`Max
`
`
`
`
`
`
`18
`85
`5.25
`−5.45
`525
`
`
`
`
`Unit
`
`Gbps
`ps
`
`ps
`
`mA
`mA
`V
`V
`mW
`mW
`dB
`dB
`
`
`
`
`
`Rev. 0 | Page 4 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`
`
`ADCMP566
`
`
`
`Input
`Voltages
`
`Output
`Temperature
`
`ABSOLUTE MAXIMUM RATINGS
`Table 2. ADCMP566 Absolute Maximum Ratings
`
`Parameter
`Rating
`−0.5 V to +6.0 V
`Supply
`Positive Supply Voltage
`(VCC to GND)
`Voltages
`Negative Supply Voltage
`(VEE to GND)
`Ground Voltage Differential
`Input Common-Mode
`Voltage
`Differential Input Voltage
`Input Voltage,
`Latch Controls
`Output Current
`Operating Temperature,
`Ambient
`Operating Temperature,
`Junction
`Storage Temperature Range
`
`THERMAL CONSIDERATIONS
`The ADCMP566 LFCSP 32-lead package option has a θJA
`(junction-to-ambient thermal resistance) of 27.2°C/W in
`still air.
`
`
`
`−6.0 V to +0.5 V
`
`−0.5 V to +0.5 V
`−3.0 V to +4.0 V
`
`−7.0 V to +7.0 V
`VEE to 0.5 V
`
`30 mA
`−40°C to +85°C
`
`125°C
`
`−65°C to +150°C
`
`
`Stress above those listed under Absolute Maximum Ratings may
`cause permanent damage to the device. This is a stress rating only
`and functional operation of the device at these or any other
`conditions above those indicated in the operational sections of this
`specification is not implied. Exposure to absolute maximum rating
`conditions for extended periods may affect device reliability.
`
`
`
`ESD CAUTION
`ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
`the human body and test equipment and can discharge without detection. Although this product features
`proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
`electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
`degradation or loss of functionality.
`
`
`
`
`
`
`Rev. 0 | Page 5 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`
`
`PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
`
`24
`VEE
`23 NC
`22 VEE
`21 VCC
`20 VCC
`19 VEE
`18 NC
`17 VEE
`
`
`
`
`25GND
`26QA
`27QA
`28GND
`29
`NC
`30LEA
`31LEA
`32GND
`
`PIN 1
`INDICATOR
`ADCMP566
`TOP VIEW
`(Not to Scale)
`
`GND16
`QB15
`QB14
`GND13
`NC12
`LEB11
`LEB10
`GND9
`
`NC = NO CONNECT
`
`12345678
`
`GND
`–INA
`+INA
`VCC
`VCC
`+INB
`–INB
`GND
`
`03633-0-002
`
`Figure 2. ADCMP566 Pin Configuration
`
`
`
`Table 3. ADCMP566 Pin Descriptions
`Pin No.
`Mnemonic
`Function
`1
`GND
`Analog Ground
`2
`−INA
`Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
`in conjunction with the noninverting A input.
`Noninverting analog input of the differential input stage for Channel A. The noninverting A input must
`be driven in conjunction with the inverting A input.
`Positive Supply Terminal
`Positive Supply Terminal
`Noninverting analog input of the differential input stage for Channel B. The noninverting B input must
`be driven in conjunction with the inverting B input.
`Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven
`in conjunction with the noninverting B input.
`Analog Ground
`Analog Ground
`One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the
`output will track changes at the input of the comparator. In the latch mode (logic high), the output will
`reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
`in conjunction with LEB.
`One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the
`output will track changes at the input of the comparator. In the latch mode (logic low), the output will
`reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
`in conjunction with LEB.
`No Connect. Leave pin unconnected.
`Digital Ground
`One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the
`noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
`in the compare mode). See the LEB description (Pin 11) for more information.
`One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the
`noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
`in the compare mode). See the LEB description (Pin 11) for more information.
`Digital Ground
`Negative Supply Terminal
`No Connect. Leave pin unconnected.
`Negative Supply Terminal
`Positive Supply Terminal
`Positive Supply Terminal
`
`3
`
`4
`5
`6
`
`7
`
`8
`9
`10
`
`11
`
`12
`13
`14
`
`15
`
`16
`17
`18
`19
`20
`21
`
`+INA
`
`VCC
`VCC
`+INB
`
`−INB
`
`GND
`GND
`LEB
`
`LEB
`
`NC
`GND
`QB
`
`QB
`
`GND
`VEE
`NC
`VEE
`VCC
`VCC
`
`Rev. 0 | Page 6 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`Mnemonic
`VEE
`NC
`VEE
`GND
`QA
`
`QA
`
`GND
`NC
`LEA
`
`LEA
`
`GND
`
`Function
`Negative Supply Terminal
`No Connect. Leave pin unconnected.
`Negative Supply Terminal
`Digital Ground
`One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
`noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
`in the compare mode). See the LEA description (Pin 30) for more information.
`One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the
`noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
`in the compare mode). See the LEA description (Pin 30) for more information.
`Digital Ground
`No Connect. Leave pin unconnected.
`One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
`output will track changes at the input of the comparator. In the latch mode (logic low), the output will
`reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
`in conjunction with LEA.
`One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
`output will track changes at the input of the comparator. In the latch mode (logic high), the output will
`reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
`in conjunction with LEA.
`Analog Ground
`
`
`
`
`Pin No.
`22
`23
`24
`25
`26
`
`27
`
`28
`29
`30
`
`31
`
`32
`
`
`
`
`Rev. 0 | Page 7 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`
`
`TIMING INFORMATION
`
`LATCH ENABLE
`
`LATCH ENABLE
`
`DIFFERENTIAL
`INPUT VOLTAGE
`
`VIN
`
`Q OUTPUT
`
`Q OUTPUT
`
`
`
`tH
`
`tS
`
`VOD
`
`tPDL
`
`tPDH
`
`tF
`
`tR
`
`Figure 3. System Timing Diagram
`
`
`tPL
`
`tPLOH
`
`tPLOL
`
`50%
`
`VREF ± VOS
`
`50%
`
`50%
`
`03633-0-003
`
`tPDL
`
`Input to output
`low delay
`
`Symbol Timing
`tH
`Minimum
`hold time
`
`tPL
`
`tS
`
`tR
`
`tF
`
`Minimum
`latch enable
`pulsewidth
`Minimum
`setup time
`
`Output rise
`time
`
`Output fall
`time
`
`VOD
`
`Voltage
`overdrive
`
`
`
`
`
`Description
`Minimum time after the negative
`transition of the Latch Enable
`signal that the input signal must
`remain unchanged to be acquired
`and held at the outputs
`Minimum time that the Latch
`Enable signal must be high to
`acquire an input signal change
`Minimum time before the
`negative transition of the Latch
`Enable signal that an input signal
`change must be present to be
`acquired and held at the outputs
`Amount of time required to
`transition from a low to a high
`output as measured at the 20%
`and 80% points
`Amount of time required to
`transition from a high to a low
`output as measured at the 20%
`and 80% points
`Difference between the
`differential input and reference
`input voltages
`
`Rev. 0 | Page 8 of 16
`
`The timing diagram in Figure 3 shows the ADCMP566 compare
`and latch features. Table 4 describes the terms in the diagram.
`Table 4. Timing Descriptions
`Symbol Timing
`Description
`tPDH
`Input to output
`Propagation delay measured from
`high delay
`the time the input signal crosses
`the reference (± the input offset
`voltage) to the 50% point of an
`output low-to-high transition
`Propagation delay measured from
`the time the input signal crosses
`the reference (± the input offset
`voltage) to the 50% point of an
`output high-to-low transition
`Propagation delay measured from
`the 50% point of the Latch Enable
`signal low-to-high transition to
`the 50% point of an output low-
`to-high transition
`Propagation delay measured from
`the 50% point of the Latch Enable
`signal low-to-high transition to
`the 50% point of an output high-
`to-low transition
`
`Latch enable
`to output high
`delay
`
`Latch enable
`to output low
`delay
`
`tPLOH
`
`tPLOL
`
`
`
`
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`
`
`
`
`APPLICATION INFORMATION
`The ADCMP566 comparators are very high speed devices.
`Consequently, high speed design techniques must be employed
`to achieve the best performance. The most critical aspect of any
`ADCMP566 design is the use of a low impedance ground plane.
`A ground plane, as part of a multilayer board, is recommended
`for proper high speed performance. Using a continuous
`conductive plane over the surface of the circuit board can create
`this, allowing breaks in the plane only for necessary signal
`paths. The ground plane provides a low inductance ground,
`eliminating any potential differences at different ground points
`throughout the circuit board caused by ground bounce. A
`proper ground plane also minimizes the effects of stray
`capacitance on the circuit board.
`
`It is also important to provide bypass capacitors for the power
`supply in a high speed application. A 1µF electrolytic bypass
`capacitor should be placed within 0.5 inches of each power
`supply pin to ground. These capacitors will reduce any potential
`voltage ripples from the power supply. In addition, a 10 nF
`ceramic capacitor should be placed as close as possible from the
`power supply pins on the ADCMP566 to ground. These
`capacitors act as a charge reservoir for the device during high
`frequency switching.
`
`The LATCH ENABLE input is active low (latched). If the
`latching function is not used, the LATCH ENABLE input
`should be grounded (ground is an ECL logic high), and the
`complementary input, LATCH ENABLE, should be tied to
`−2.0 V. This will disable the latching function.
`
`Occasionally, one of the two comparator stages within the
`ADCMP566 will not be used. The inputs of the unused
`comparator should not be allowed to float. The high internal
`gain may cause the output to oscillate (possibly affecting the
`comparator that is being used) unless the output is forced into a
`fixed state. This is easily accomplished by ensuring that the two
`inputs are at least one diode drop apart, while also appropriately
`connecting the LATCH ENABLE and LATCH ENABLE inputs
`as described above.
`
`The best performance is achieved with the use of proper ECL
`terminations. The open emitter outputs of the ADCMP566 are
`designed to be terminated through 50 Ω resistors to −2.0 V, or
`any other equivalent ECL termination. If a −2.0 V supply is not
`available, an 82 Ω resistor to ground and a 130 Ω resistor to
`−5.2 V provide a suitable equivalent. If high speed ECL signals
`must be routed more than a centimeter, microstrip or stripline
`techniques may be required to ensure proper transition times
`and prevent output ringing.
`
`ADCMP566
`
`CLOCK TIMING RECOVERY
`Comparators are often used in digital systems to recover clock
`timing signals. High speed square waves transmitted over a
`distance, even tens of centimeters, can become distorted due to
`stray capacitance and inductance. Poor layout or improper
`termination can also cause reflections on the transmission line,
`further distorting the signal waveform. A high speed
`comparator can be used to recover the distorted waveform
`while maintaining a minimum of delay.
`
`OPTIMIZING HIGH SPEED PERFORMANCE
`As with any high speed comparator amplifier, proper design and
`layout techniques should be used to ensure optimal perform-
`ance from the ADCMP566. The performance limits of high
`speed circuitry can easily be a result of stray capacitance,
`improper ground impedance, or other layout issues.
`
`Minimizing resistance from source to the input is an important
`consideration in maximizing the high speed operation of the
`ADCMP566. Source resistance in combination with equivalent
`input capacitance could cause a lagged response at the input,
`thus delaying the output. The input capacitance of the
`ADCMP566 in combination with stray capacitance from an
`input pin to ground could result in several picofarads of
`equivalent capacitance. A combination of 3 kΩ source resistance
`and 5 pF of input capacitance yields a time constant of 15 ns,
`which is significantly slower than the sub 500 ps capability of
`the ADCMP566. Source impedances should be significantly less
`than 100 Ω for best performance.
`
`Sockets should be avoided due to stray capacitance and induc-
`tance. If proper high speed techniques are used, the ADCMP566
`should be free from oscillation when the comparator input
`signal passes through the switching threshold.
`
`COMPARATOR PROPAGATION
`DELAY DISPERSION
`The ADCMP566 has been specifically designed to reduce
`propagation delay dispersion over an input overdrive range of
`100 mV to 1 V. Propagation delay overdrive dispersion is the
`change in propagation delay that results from a change in the
`degree of overdrive (how far the switching point is exceeded by
`the input). The overall result is a higher degree of timing
`accuracy since the ADCMP566 is far less sensitive to input
`variations than most comparator designs.
`
`Propagation delay dispersion is a specification that is important
`in critical timing applications such as ATE, bench instruments,
`and nuclear instrumentation. Overdrive dispersion is defined
`
`Rev. 0 | Page 9 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`
`as the variation in propagation delay as the input overdrive
`conditions are changed (Figure 4). For the ADCMP566,
`overdrive dispersion is typically 35 ps as the overdrive is
`changed from 100 mV to 1 V. This specification applies for
`both positive and negative overdrive since the ADCMP566 has
`equal delays for positive and negative going inputs.
`
`The 35 ps propagation delay overdrive dispersion of the
`ADCMP566 offers considerable improvement of the 100 ps
`dispersion of other similar series comparators.
`
`
`1.5V OVERDRIVE
`
`INPUT VOLTAGE
`
`Q OUTPUT
`
`20mV OVERDRIVE
`
`VREF ± VOS
`
`DISPERSION
`
`03633-0-004
`Figure 4. Propagation Delay Dispersion
`
`
`COMPARATOR HYSTERESIS
`The addition of hysteresis to a comparator is often useful in a
`noisy environment or where it is not desirable for the compara-
`tor to toggle between states when the input signal is at the
`switching threshold. The transfer function for a comparator
`with hysteresis is shown in Figure 5. If the input voltage
`approaches the threshold from the negative direction, the
`comparator will switch from a 0 to a 1 when the input crosses
`+VH/2. The new switching threshold becomes −VH/2. The
`comparator will remain in a 1 state until the threshold −VH/2 is
`crossed coming from the positive direction. In this manner,
`noise centered on 0 V input will not cause the comparator to
`switch states unless it exceeds the region bounded by ±VH/2.
`
`Positive feedback from the output to the input is often used to
`produce hysteresis in a comparator (Figure 9). The major
`problem with this approach is that the amount of hysteresis
`varies with the output logic levels, resulting in a hysteresis that
`is not symmetrical around zero.
`
`Another method to implement hysteresis is generated by
`introducing a differential voltage between LATCH ENABLE
`and LATCH ENABLE. inputs (Figure 10). Hysteresis generated
`in this manner is independent of output swing and is symmetri-
`cal around zero. The variation of hysteresis with input voltage is
`shown in Figure 6.
`
`0
`–20
`
`–15
`
`Rev. 0 | Page 10 of 16
`
`–VH
`2
`
`
`
`0V
`
`+VH
`2
`
`INPUT
`
`1
`
`OUTPUT
`
`03633-0-005
`Figure 5. Comparator Hysteresis Transfer Function
`
`
`
`
`0
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`HYSTERESIS (mV)
`
`
`
`03633-0-006
`
`5
`
`10
`
`15
`
`–10
`–5
`0
`∆ LATCH = LE – LEB (mV)
`Figure 6. Comparator Hysteresis Transfer Function
`Using Latch Enable Input
`
`
`MINIMUM INPUT SLEW RATE REQUIREMENT
`As for all high speed comparators, a minimum slew rate must
`be met to ensure that the device does not oscillate when the
`input crosses the threshold. This oscillation is due in part to the
`high input bandwidth of the comparator and the parasitics of
`the package. Analog Devices recommends a slew rate of 5 V/µs
`or faster to ensure a clean output transition. If slew rates less
`than 5 V/µs are used, then hysteresis should be added to reduce
`the oscillation.
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`
`
`
`TYPICAL APPLICATION CIRCUITS
`
`
`ADCMP566
`
`
`
`
`VIN
`
`VREF
`
`+VREF
`
`VIN
`
`ADCMP566
`
`OUTPUTS
`
`VIN
`
`ADCMP566
`
`OUTPUTS
`
`LATCH
`ENABLE
`INPUTS
`
`–2.0V
`
`ALL RESISTORS 50Ω
`
`Figure 7. High Speed Sampling Circuits
`
`
`
`
`03633-0-007
`
`HYSTERESIS
`VOLTAGE
`
`450Ω
`
`–2.0V
`
`ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED
`
`03633-0-010
`Figure 10. Hysteresis Using Latch Enable Input
`
`
`
`
`
`
`ADCMP566
`
`OUTPUTS
`
`VIN
`
`ADCMP566
`
`30Ω
`
`30Ω
`
`50Ω
`
`50Ω
`
`127Ω
`
`127Ω
`
`–5.2V
`
`03633-0-011
`Figure 11. How to Interface an ECL Output to an
`Instrument with a 50 Ω to Ground Input
`
`
`
`
`
`
`
`–VREF
`
`ADCMP566
`
`LATCH
`ENABLE
`INPUTS
`
`–2.0V
`
`ALL RESISTORS 50Ω
`
`Figure 8. High Speed Window Comparator
`
`
`
`
`03633-0-008
`
`
`
`ADCMP566
`
`OUTPUTS
`
`R1
`
`R2
`
`–2.0V
`
`ALL RESISTORS 50Ω
`
`03633-0-009
`Figure 9. Hysteresis Using Positive Feedback
`
`
`
`VIN
`
`VREF
`
`
`
`
`
`Rev. 0 | Page 11 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`
`
`03633-0-016
`
`80
`
`15
`
`60
`
`–20
`
`0
`
`20
`40
`TEMPERATURE (°C)
`Figure 15. Input Bias Current vs. Temperature
`
`
`
`ADCMP566
`
`
`
`TYPICAL PERFORMANCE CHARACTERISTICS
`(VCC = +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.)
`
`23.4
`
`23.2
`
`23.0
`
`22.8
`
`22.6
`
`22.4
`
`22.2
`
`+IN INPUT BIAS CURRENT (µA)
`
`(+IN = 1V,–IN = 0V)
`
`22.0
`–40
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`–20
`
`HYSTERESIS (mV)
`
`
`
`
`
`03633-0-013
`
`30
`
`25
`
`20
`
`15
`
`10
`
`5
`
`INPUT BIAS CURRENT (µA)
`
`0
`–2.5
`–1.5
`–0.5
`0.5
`1.5
`2.5
`3.5
`NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V)
`
`Figure 12. Input Bias Current vs. Input Voltage
`
`
`
`2.0
`
`1.8
`
`1.6
`
`1.4
`
`1.2
`
`1.0
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`OFFSET VOLTAGE (mV)
`
`
`
`03633-0-017
`
`–15
`
`5
`
`–10
`–5
`0
`∆ LATCH = LE – LEB (mV)
`Figure 16. Hysteresis vs. ∆Latch
`
`
`
`10
`
`
`
`03633-0-014
`
`80
`
`195
`
`185
`
`175
`
`165
`
`155
`
`145
`
`135
`
`TIME (ps)
`
`–20
`
`0
`
`20
`40
`TEMPERATURE (°C)
`Figure 13. Input Offset Voltage vs. Temperature
`
`
`
`60
`
`0
`–40
`
`195
`
`185
`
`175
`
`165
`
`155
`
`145
`
`135
`
`TIME (ps)
`
`125
`–40 –30 –20 –10
`
`0
`
`
`
`03633-0-018
`
`70
`
`80
`
`90
`
`50
`
`60
`
`10
`20
`30
`40
`TEMPERATURE (°C)
`Figure 17. Fall Time vs. Temperature
`
`
`
`
`03633-0-015
`
`70
`
`80
`
`90
`
`Rev. 0 | Page 12 of 16
`
`125
`–40 –30 –20 –10
`
`0
`
`50
`
`60
`
`10
`20
`30
`40
`TEMPERATURE (°C)
`Figure 14. Rise Time vs. Temperature
`
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`
`
`
`
`
`
`
`
`
`
`
`PROPAGATION DELAY (ps)
`
`PROPAGATION DELAY ERROR (ps)
`
`
`
`03633-0-021
`
`1.9
`
`2.0
`
`Rev. 0 | Page 13 of 16
`
`1.1
`
`1.2
`
`1.3
`
`1.4
`1.5
`TIME (ns)
`Figure 20. Rise and Fall of Outputs vs. Time
`
`
`1.6
`
`1.7
`
`1.8
`
`–1.0
`
`–1.2
`
`–1.4
`
`–1.6
`
`–1.8
`
`OUTPUT RISE AND FALL (V)
`
`–2.0
`1.0
`
`ADCMP566
`
`239
`
`238
`
`237
`
`236
`
`235
`
`234
`
`233
`
`232
`
`PROPAGATION DELAY (ps)
`
`
`
`
`
`
`
`242
`
`240
`
`238
`
`236
`
`234
`
`232
`
`230
`
`228
`
`
`
`03633-0-022
`
`3
`
`
`
`03633-0-023
`
`231
`–2
`
`0
`
`–1
`0
`1
`2
`INPUT COMMON-MODE VOLTAGE (V)
`Figure 21. Propagation Delay vs. Common-Mode Voltage
`
`
`
`
`
`03633-0-019
`
`80
`
`90
`
`2.15
`
`4.15
`6.15
`PULSEWIDTH (ns)
`Figure 22. Propagation Delay Error vs. Pulsewidth
`
`
`8.15
`
`–5
`
`–10
`
`–15
`
`–20
`
`–25
`
`–30
`
`–35
`
`PROPAGATION DELAY ERROR (ps)
`
`–40
`0.15
`
`
`
`03633-0-020
`
`1.6
`
`226
`–40 –30 –20 –10
`
`0
`
`50
`
`60
`
`70
`
`10
`20
`30
`40
`TEMPERATURE (°C)
`Figure 18. Propagation Delay vs. Temperature
`
`
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`
`0
`
`0.2
`
`0.4
`
`1.2
`
`1.4
`
`0.6
`0.8
`1.0
`OVERDRIVE VOLTAGE (V)
`Figure 19. Propagation Delay Error vs. Overdrive Voltage
`
`
`
`–0.8
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`
`
`OUTLINE DIMENSIONS
`
`5.00
`BSC SQ
`
`
`
`0.60 MAX
`
`0.60 MAX
`
`PIN 1
`INDICATOR
`
`TOP
`VIEW
`
`4.75
`BSC SQ
`
`25
`24
`
`1617
`
`0.50
`BSC
`
`0.50
`0.40
`0.30
`
`12° MAX
`
`0.80 MAX
`0.65 NOM
`
`1.00
`0.90
`0.80
`
`SEATING
`PLANE
`
`0.05 MAX
`0.02 NOM
`
`0.30
`0.23
`0.18
`
`0.20 REF
`
`COPLANARITY
`0.08
`
`132
`
`89
`
`BOTTOM
`VIEW
`
`3.50
`REF
`
`PIN 1
`INDICATOR
`
`3.25
`2.70
`1.25
`
`SQ
`
`COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
`Figure 23. 32-Lead Lead Frame Chip Scale Package [LFCSP]
`(CP-32)
`Dimensions shown in millimeters
`
`
`
`
`Temperature Range
`−40°C to +85°C
`
`Package Description
`LFCSP-32
`
`Package Option
`CP-32
`
`
`
`
`
`
`
`ORDERING GUIDE
`Model
`ADCMP566BCP
`
`
`
`
`Rev. 0 | Page 14 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`
`
`
`
`Notes
`
`
`ADCMP566
`
`Rev. 0 | Page 15 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`

`

`ADCMP566
`
`
`
`Notes
`
`
`© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
`registered trademarks are the property of their respective owners.
`
`C03633–0–10/03(0)
`
`Rev. 0 | Page 16 of 16
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1019
`
`