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`

`HANDBOOK OF THIN-FILM
`DEPOSITION PROCESSES AND
`TECHNIQUES
`Principles, Methods, Equipment and
`Applications
`Second Edition
`
`Edited by
`
`Krishna Seshan
`
`Intel Corporation
`Santa Clara, California
`
`NOYES PUBLICATIONS
`WILLIAM ANDREW PUBLISHING
`Norwich, New York, U.S.A.
`
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`

`Copyright © 2002 by Noyes Publications
`No part of this book may be reproduced or
`utilized in any form or by any means, elec-
`tronic or mechanical, including photocopying,
`recording or by any information storage and
`retrieval system, without permission in writing
`from the Publisher.
`Library of Congress Catalog Card Number: 2001135178
`ISBN: 0-8155-1442-5
`Printed in the United States
`
`Published in the United States of America by
`Noyes Publications / William Andrew Publishing
`13 Eaton Avenue
`Norwich, NY 13815
`1-800-932-7045
`www.williamandrew.com
`www.knovel.com
`
`10 9 8 7 6 5 4 3 2 1
`
`Library of Congress Cataloging-in-Publication Data
`
`Handbook of Thin-Film Deposition Processes and Techniques / [edited]
`by Krishna Seshan. -- 2nd edition
`p.
`cm.
`Includes bibliographical references and index.
`ISBN 0-8155-1442-5
`1. Thin film devices -- Design and construction -- Handbooks,
`manuals, etc. I. Seshan, Krishna. II. Title.
`TK7872.T55H36
`2001135178
`621.381'72--dc19
` CIP
`
`NOTICE
`
`To the best of our knowledge the information in this publication is
`accurate; however the Publisher does not assume any responsibility
`or liability for the accuracy or completeness of, or consequences
`arising from, such information. This book is intended for informational
`purposes only. Mention of trade names or commercial products does
`not constitute endorsement or recommendation for use by the Publisher.
`Final determination of the suitability of any information or product
`for use contemplated by any user, and the manner of that use, is the
`sole responsibility of the user. We recommend that anyone intending
`to rely on any recommendation of materials or procedures mentioned
`in this publication should satisfy himself as to such suitability, and
`that he can meet all applicable safety and health standards.
`
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`

`6 T
`
`he Role Of Metrology
`And Inspection In
`Semiconductor
`Processing
`
`Mark Keefer, Rebecca Pinto, Cheri Dennison,
`and James Turlo
`
`1.0 OVERVIEW
`
`As integrated circuits (IC) are incorporated into more and more
`products, the market demand for lower cost, higher performance devices
`continues to grow. In order to design and manufacture a high performance
`integrated circuit cost-effectively, the parameters of the manufacturing
`process need to be carefully controlled: film thicknesses and material
`properties must be accurate, uniform and controlled; linewidths and edge
`profiles must fall within tight limits, and the devices need to be free of defects
`that affect yield.
`Thin film metrology and wafer inspection for defects are integral to
`controlling the semiconductor manufacturing process. Film properties,
`linewidths, and defect levels need to be measured, first to optimize the
`manufacturing process, then later to ensure that it is operating under control.
`
`241
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`242 Thin-Film Deposition Processes and Technologies
`
`This chapter explores the subjects of metrology and inspection of
`integrated circuits. After the introduction, implementation strategies for
`metrology and inspection are examined from a historical perspective. Then,
`as we anticipate increasingly complex devices having critical dimensions of
`0.18 and 0.13 µm, manufactured on 300 mm wafers, we look at how
`metrology and inspection will evolve to meet these measurement challenges,
`while simultaneously meeting increasing pressure for automation, higher
`throughput and higher reliability. In the final section we provide a technology
`reference that discusses theory of operation, equipment design principles,
`main applications, and strengths and limitations of the metrology and
`inspection systems. The sections are organized as follows:
`1.0 Overview
`2.0 Introduction to Metrology and Inspection
`3.0 Metrology and Inspection Trends: Past, Present and
`Future
`4.0 Theory of Operation, Equipment Design Principles,
`Main Applications, and Strengths and Limitations of:
`4.1 Film thickness measurement systems
`4.2 Resistivity measurement systems
`4.3 Stress measurement systems
`4.4 Defect inspection systems
`4.5 Automatic defect classification
`4.6 Defect data analysis systems
`
`2.0
`
`INTRODUCTION TO METROLOGY AND INSPECTION
`
`Metrology and inspection systems can be broadly separated into three
`main classifications by application: critical dimension (CD) and overlay
`measurements, particle and pattern defect detection, and thin film parameter
`measurement (such as resistivity, thickness and stress). The typical process-
`ing steps, and metrology and inspection equipment used to monitor and/or
`control them, are given in Table 1.
`In the semiconductor industry, the continual demand for denser
`integrated circuits with higher performance and higher speeds drives techno-
`logical advances in all facets of manufacturing. A key to the success of
`semiconductor processing is an understanding of the chemical, mechanical
`and kinetic properties of the wide range of materials used to make a typical
`circuit.
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`Chapter 6: Metrology and Inspection
`
`243
`
`Table 1. Typical Metrology and Inspection Parameters Monitored, by
`Process Step
`
`PROCESS STEP
`USED
`
`MEASURED ATTRIBUTE
`
`METROLOGY
`
`SYSTEM
`
`Si manufacturing
`
`resistivity
`
`4-point probe, eddy current
`
`Inspection of incoming
`wafers
`
`flatness
`defects:
`particles
`micro-scratches
`crystalline defects
`haze
`
`flatness tester
`defect inspection system
`
`↓
`
`Si epitaxy
`
`resistivity
`thickness
`
`4-point probe, eddy current
`FTIR
`
`Conductor deposition
`(PVD, MOCVD)
`
`resistivity
`particulate contamination
`
`4-point probe, eddy current
`defect inspection system
`
`Dielectric deposition
`(CVD)
`
`thickness, RI
`stress
`particulate contamination
`dielectric constant
`
`reflectometer, ellipsometer
`stress gauge
`defect inspection system
`C-V tester
`
`Dopant processes
`(ion implant, diffusion)
`
`uniformity
`depth profile
`
`Planarization
`
`Etch
`
`Lithography
`
`removal rate and uniformity
`local/global planarity
`slurry particles,
`micro-scratches
`
`removal rate and uniformity
`etch selectivity
`etch profile
`particulate contamination
`pattern defects
`
`critical dimension
`overlay
`pattern defects
`particulate contamination
`
`4-point probe, thermal wave, FTIR
` SIMS, SRP
`
`reflectometer, ellipsometer
`surface profiler (high resolution)
`defect inspection system
`
`reflectometer
`reflectometer
`SEM, AFM
`defect inspection system
`defect inspection system
`
`SEM
`optical overlay tool
`defect inspection system
`defect inspection system
`
`Yield monitoring
`
`correlation of metrology and
`inspection results to yield
`
`fab-wide data management
`system
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`244 Thin-Film Deposition Processes and Technologies
`
`To maintain control of the product, thin film quality is regularly
`monitored by tools that measure electrical, physical, optical and mechanical
`properties of films. Film parameters typically monitored include thickness
`and refractive index, resistivity and stress.
`Another key area for process control is the reduction of defects that
`affect production yield. Defect reduction is typically achieved through an
`iterative process that involves detection of defects, classification of defects,
`identification of the source of the yield-limiting defects, correction of the
`process to eliminate or reduce the defect mechanism, then monitoring the
`process for yield excursions. The process is iterative in that, while the process
`is monitored for defect excursions, further defect analysis is conducted in
`parallel to drive continuous improvement of the yield.
`Defect reduction is employed for five main applications:
`Inspection of bare wafers for contamination and surface
`quality, either during the wafer manufacturing process or as
`incoming material at the IC manufacturer
`Inspection of bare wafers used to monitor the cleanliness of
`process (or metrology) equipment
`Inspection of product wafers to decrease defectivity during
`the early phases of the product life cycle, and throughout the
`life cycle for continuous improvement
`Inspection of product wafers to monitor processes that introduce
`contamination, scratches or pattern defects
`(cid:127) Prediction of yield
`Specific tool sets have been developed to address each of these needs.
`Bare wafer or unpatterned wafer inspection systems are optimized for
`scanning wafers at high throughput without the constraint of coping with the
`interference of pattern signals. Inspection of patterned wafers for yield
`improvement or process monitoring requires a system that not only copes
`with pattern, but provides high capture of key defect types at reasonable
`throughput. For yield prediction, the ability to integrate defect information—
`number, type, spatial signature—with other parameters such as electrical test
`results, becomes the key. Theory of operation as well as equipment design
`principles for each of these categories of defect inspection systems are
`described in Sec. 4.0 of this chapter.
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`(cid:127)
`(cid:127)
`(cid:127)
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`

`Chapter 6: Metrology and Inspection
`
`245
`
`3.0 METROLOGY AND INSPECTION TRENDS: PAST,
`PRESENT, AND FUTURE
`
`Metrology systems have undergone tremendous changes since the
`home-built bench top characterization tools of the 1960s. Inspection systems
`have gone through similar changes, moving from manual inspection by
`operators to automated inspection tools. As the semiconductor industry has
`grown and matured, metrology and inspection systems have kept pace.
`Measurement performance—predominantly sensitivity and repeatability—
`has steadily improved. The level of automation has dramatically increased,
`beginning with automated wafer handling, then pattern recognition, remote
`operation through development of the Semiconductor Equipment Communi-
`cation Standard (SECS) protocol, development of automated algorithms that
`“learn” best measurement setups for monitoring a given product and process,
`and now automatic defect classification. These developments have sup-
`ported the growing practice of making measurements on product wafers
`(rather than designated monitor wafers), a practice driven by the increase in
`wafer diameter to 200 mm, with a consequent rise in monitor wafer cost.
`Now, increasing attention is being paid to reliability, up-time and ease-of-use
`attributes, with the goal of increasing overall effectiveness of the equipment.
`In the future, price-performance pressures on IC manufacturers will
`continue to be passed on to equipment manufacturers. The shift from off-line
`sampling to on-line control will accelerate, with increasing use of in-line and
`in situ measurements. Reliability and ease-of-use emphasis will drive the
`implementation of integrated, automated systems for measurement optimi-
`zation, data interpretation, and adaptive feedback to the process equipment.
`
`3.1 Trends in Metrology
`
`Thin film measurements have progressed from simple single layer
`thickness measurements to multiple layer thickness and refractive index
`measurements. The trend towards multiple layer measurements has been
`partially driven by the increasing use of cluster deposition systems, where no
`opportunity exists for single layer measurements. Additionally, economics
`plays a role, in that as wafer sizes increase, cost savings can be realized by
`reducing the use of monitor wafers. In many cases, measurement of a layer
`on a product wafer requires measurement of the underlying layer(s) as well.
`
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`246 Thin-Film Deposition Processes and Technologies
`
`Measurement of film quality and stoichiometry has become as impor-
`tant as film thickness control. This is especially true with the advent of plasma
`enhanced CVD films such as silicon-rich anti-reflective oxynitride layers,
`since the film properties are strong functions of the process parameters such
`as plasma energy and reactant flow rates.[1]
`At the same time, higher accuracy and tighter system-to-system
`matching are required to facilitate process transfer and reduce the time to
`start up new wafer fabs.
`In the future, significant changes in the approach to process monitoring
`will occur. The trend will be to monitor processing parameters inside the
`processing chamber, not film characteristics; that is, process variables, not
`product variables. The shift from off-line sampling to on-line control will
`continue, with increasing use of in-line and in situ measurements. Prevention
`of process excursions by process control sensors should significantly reduce
`product loss.[2] Sensors can be equipment state (mechanical, electrical),
`process state (chemical/physical, temperature) or wafer state (product
`parameter, uniformity).
`
`3.2 Trends in Defect Inspection
`
`In the 1980s the first inspection systems were entirely manual and thus
`operator-intensive. Typically operators used a bright light source, and
`conducted visual inspections of incoming silicon, then manual microscope
`inspection of production wafers at various points in the process. Data was
`only as accurate and repeatable as the operators themselves. Results from
`these inspections were commonly written on paper and stored in binders and
`cabinets. Operators manually correlated defects to yield using two sheets of
`transparency paper for map-to-map comparisons. Over the intervening years
`advancements in IC technology, as well as economic pressures, have driven
`the need for enhancements in sensitivity, throughput, repeatability and
`automation for the defect reduction process.
`In this section, we examine a few key trends in defect inspection:
`(cid:127) How the sensitivity of defect inspection systems has tracked
`critical dimensions of ICs—and how these systems are predicted
`to meet sensitivity needs for inspection of 0.18 and 0.13 µm
`devices, and beyond
`(cid:127) Challenges specific to inspecting 300 mm wafers
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`Chapter 6: Metrology and Inspection
`
`247
`
`(cid:127) Shifts in inspection strategies: from monitoring processes using
`bare wafers to using product wafers; towards differentiating
`yield-learning from in-line inspection; and looking forward to
`in situ inspection and adaptive process control
`Increasing automation of inspection equipment using automated
`wafer handling, automated data transfer, mini-environments,
`and remote operation
`(cid:127) The movement towards automated systems for measurement
`optimization, data interpretation, and adaptive feedback to the
`process equipment
`(cid:127) The growing emphasis on cost of ownership, overall equipment
`effectiveness, and ease of use
`Sensitivity Challenges as Critical Dimensions Decrease. A good
`rule of thumb in defect inspection is that the critical dimension (smallest
`linewidth) of the device determines the minimum size of defect likely to
`affect yield. At early steps in the process, defects as small as one-third the
`critical dimension can cause an electrical failure; at back-end levels, detecting
`defects about as large as the CD is sufficient to protect yield. Until recently
`DRAM devices had the smallest critical dimensions of any device on the
`market; at present, logic devices also have leading-edge critical dimensions.
`Historically manufacturers of inspection equipment watched DRAM manu-
`facturers closely, striving to stay ahead of the design rule of the next memory
`device, so that the inspection system would be able to detect yield-limiting
`defects. Today we have various industry consortia, and in particular, the
`National Technology Roadmap for Semiconductors,[3] to guide metrology
`and inspection equipment manufacturers in the design of next-generation
`inspection systems.
`Figure 1 shows a history of how the detection limit of inspection
`systems has kept ahead of the critical dimension of IC devices. Unpatterned
`wafer inspection systems currently on the market can now detect defects as
`small as 80 nm, whereas patterned-wafer systems can detect defects less
`than 100 nm.* The advances that have allowed inspection systems to
`continue to improve performance include:
`
`* Quoted detection limits are referenced to NIST-traceable polystyrene latex spheres
`of known size deposited on clean, well-polished bare silicon wafers.
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`248 Thin-Film Deposition Processes and Technologies
`
`(cid:127) New optical designs
`(cid:127) More powerful and/or shorter-wavelength light sources
`(cid:127) More accurate wafer stages
`(cid:127) Higher resolution cameras
`(cid:127) Better signal processing algorithms
`These evolutionary changes are ongoing for optical-based inspection
`systems, and the existing technology is proving to be extendible for inspection
`of 0.18 and 0.13 µm devices.
`
`Figure 1. Critical dimension of integrated circuits (upper line) determines detection limit
`specifications for defect inspection systems (wide bands). Historically, smaller defects have
`been detectable using unpatterned systems, where the additional challenge of coping with
`pattern signal is not present.
`
`An inspection technology based on scanning electron microscopy
`(SEM) is being used in addition to optical-based inspection systems for
`development of 0.25 and sub-0.25 µm processes. The biggest challenge for
`such high sensitivity inspection is providing cost-effective throughput. De-
`spite this challenge, SEM-based automated inspection systems are used in
`advanced IC lines throughout the world.
`SEM-based automated inspection systems provide two unique defect-
`detection capabilities. The first results from a SEM’s high resolution and
`large depth of focus: these systems can find small defects hidden in dense
`geometries where they can not be seen by optical microscopy. The second
`unique capability is the result of new, nontraditional SEM designs that
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`Chapter 6: Metrology and Inspection
`
`249
`
`enable a properly optimized system to see contrast differences in electri-
`cally defective IC features. A common example of this type of defect is an
`electrical fault caused by voids in the metal that fills a contact or via. Here the
`structure of the metal plugs appears correct when viewed from the top
`surface, but a cross-section reveals that the metal doesn’t fill the bottom of
`the contact hole. In this and similar cases an electron-beam inspection tool
`that is designed to maximize the charge-induced voltage contrast effect may
`detect the problem as a slight difference in contrast of the feature in the SEM
`image. This voltage contrast imaging ability has opened up new applications
`for automated defect inspection tools. For further information on this
`capability, see Ref. 4.
`Inspection Challenges for 300 mm Wafers. As pilot lines are
`coming up for production of devices on 300 mm wafers, inspection
`systems that accommodate these wafers are entering the market as well.
`Unpatterned inspection systems for 300 mm wafers have been on the
`market since early 1997, as these are required well in advance of produc-
`tion to allow process equipment vendors to develop their 300 mm equip-
`ment. Patterned wafer inspection systems are expected to be introduced in
`1998. The main challenge for inspecting 300 mm wafers is cost of
`ownership; particularly the increased footprint of the system, and the
`challenge of maintaining high throughput. Compared to a 200 mm wafer,
`a 300 mm wafer has an area 2.25 times as large, and for most equipment
`designs, throughput scales roughly linearly with inspected area. Maintain-
`ing the same wafer-per-hour throughput specifications for 300 mm as
`currently available for 200 mm wafers could be achieved in one of several
`ways:
`
`(cid:127) Evolutionary improvements to subsystems including faster
`data rates, faster scanners, less reliance on scanning the stage
`since its mass is relatively large.
`(cid:127) Revolutionary new scanning designs, such as the spinning
`wafer strategy currently employed on some high throughput
`unpatterned wafer inspection systems.
`(cid:127) Adapting the sampling strategy to inspect a sparser fraction
`of the wafer area.
`The high cost of 300 mm wafers also exerts economic pressure for
`devices to be built all the way to the edge of the wafer, and thus inspection
`closer to the wafer edge is necessary to protect yield.
`
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`250 Thin-Film Deposition Processes and Technologies
`
`3.3 Trends in Inspection Strategies
`
`Shift of Process Monitors from Bare Wafers to Production
`Wafers. Monitor wafers have been used widely for tool qualification and
`process monitoring throughout the IC manufacturing process. Bare wafers
`have been run on every shift to qualify the equipment for use. In recent years,
`focused contamination reduction efforts on the equipment have enabled a
`better understanding and control of the contribution of the process equipment
`to contamination of product wafers. Defect types and mechanisms are better
`characterized, and programs for cleaning or preventive maintenance of the
`equipment are in place. Thus the need for such rigorous equipment monitor-
`ing is predicted to decrease.
`The cost of monitor wafers has always been significant, and has
`become more so with the introduction of 200 mm wafers and the imminent
`move to 300 mm. Thus, more fabs have begun to relegate the use of monitor
`wafers to bringing up new tools and diagnosing specific contamination
`problems, while using product wafers to monitor their processes.
`Interestingly, the predicted decline in use of monitor wafers has not
`been reflected in declining sales of unpatterned wafer inspection equipment.
`The rapid expansion in the semiconductor industry during the 1990s has
`driven strong growth in unpatterned wafer inspection system sales, dominat-
`ing any effects of decreasing monitor wafer use.
`Looking Ahead to In Situ Inspection and Adaptive Process
`Control. A logical extension to process monitoring is to incorporate the
`inspection system into the process tool itself. An in situ inspection system
`could provide information to the process tool, so that when defect excursions
`are detected, the process tool could be flagged and shut down, or perhaps
`even adjusted to eliminate the defect mechanism. Having the inspection tool
`provide closed-loop control of the defectivity of the process is an example of
`adaptive process control.
`The barriers that currently exist for achieving this scenario are signifi-
`cant. At present, the capability of a stand-alone inspection system would be
`difficult to reproduce inside the economic and physical constraints of a
`process chamber. Also, understanding how to adapt a process to eliminate
`the defects detected by the inspection system is nontrivial for a team of
`experienced engineers. Designing an expert system to replace that body of
`knowledge would be a significant challenge. However, strong economic
`pressures exist to reduce the cost of the defect reduction process, and part
`of the solution may involve meeting the challenges of in situ inspection.
`
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`Chapter 6: Metrology and Inspection
`
`251
`
`An alternative approach—and another example of adaptive process
`control—is to provide tighter control of the process parameters through
`improvements to in situ environmental sensors. This more direct, causal
`means of addressing process control issues involves rapid measurement and
`feedback based on process parameters, e.g., temperature and pressure. In
`contrast, an in situ inspection system measures the effects of out-of-control
`process parameters: defects incurred on the product wafer.
`Trends in Automation of Wafer Inspection Equipment. An ongo-
`ing trend for IC inspection has been a growing emphasis on automation of the
`inspection process: automating the inspection and defect review equipment
`itself, and integrating it with yield data using defect data management
`systems. The cost of ownership of the inspection process decreases as
`automation is introduced, because trained engineers and operators can focus
`elsewhere in the fab. Repeatability and accuracy increase as the subjective
`nature of human judgment is replaced by standard algorithms. Automation
`facilitates the de-localization of a given manufacturing process, allowing the
`process to be copied exactly from fab to fab around the world. Automation
`can also support a more rapid return on investment by helping ramp a process
`to yield in a shorter time.
`Automation began with the introduction of automated wafer handling
`using mechanical robots, and has expanded its scope to include other
`subsystems within the wafer inspection and defect review tools. In an effort
`to reduce operator error and increase throughput, Optical Character Recog-
`nition (OCR) and Bar Code Reading (BCR) were incorporated into these
`tools to read lot and wafer information during automatic inspection or review
`sequences. Signal towers communicate the status of the systems through
`colored or flashing lights, and mini-environments and pods enclose the wafer
`cassette or the inspection or review tool to enhance the cleanliness of the local
`environment.
`The development of the Semiconductor Equipment Communication
`Standard (SECS) protocol allows a host computer to operate the inspection
`and review systems remotely, initiating automatic inspection and controlling
`the flow of data from the inspection tool to the review tool to the fab
`database. One benefit of this automation is the reduction of operator error in
`the selection of measurement recipes and data entry of basic lot information.
`Automated defect data management systems were introduced to
`deal with the tremendous amount of data generated by automatic defect
`inspection systems. Yield correlation is one of the primary tasks of the
`defect data management system. The newest systems automate yield
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`252 Thin-Film Deposition Processes and Technologies
`
`correlation by overlaying maps of electrical test results with defect maps,
`bringing in defect type information from review stations, then delivering
`yield statistics by process level and defect types. This information has
`given the defect reduction engineer the ability to focus quickly on the
`defect types and process layers that most affect yield.
`Defect data management systems have also adopted the use of
`statistical process control (SPC) monitors that flag out-of-control defect data.
`In a typical fab today, the inspection tools automatically feed data (defect
`count, type, intensity, spatial signature) to the data management system. The
`data management system constructs SPC charts from the incoming data and
`checks for out-of-control status (using conditions predetermined by the
`engineer). If the data are out-of-control, the system alerts the engineer by
`e-mail or pager.
`Automated transfer of data from the inspection system to the review
`station represented a tremendous step forward in automating the inspection
`process. Review stations—traditional white-light, laser confocal or SEM;
`stand-alone or incorporated into the inspection system—take the coordinates
`of the defects reported by the inspection system and automatically drive to
`those locations on the wafer. The defects are then quickly reviewed, and
`classified either manually or using automatic defect classification (discussed
`in next section). This capability led to faster and better understanding of
`defect origins and mechanisms and their impact on yield.
`Trends in Automation through Advanced Algorithms. A further
`step in automation is the use of algorithms to replace human operators for
`optimization of system parameters to create “recipes” to inspect a given level
`for a given set of defect types, and automatic defect classification (ADC).
`Advancements in these algorithms are likely to reduce cost of ownership of
`the inspection process substantially over the next few years.
`Automated Recipe Creation Procedures. When a new device and/or
`process level is inspected for the first time, a recipe has to be generated that
`contains optimized measurement parameters such as optical and signal
`processing configurations. The procedures for creating these recipes—and
`the number of parameters involved—have become more complex as inspec-
`tion technology has advanced. Thus, automation of the procedure has
`escalated in importance. Automated recipe creation is particularly important
`in an ASIC fab in which many different products are manufactured, and
`during an excursion when quick recipe creation at a nonstandard inspection
`point may be needed.
`
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`Chapter 6: Metrology and Inspection
`
`253
`
`Simply stated, automated recipe creation works by evaluating changes
`in the signal-to-noise ratio as the different optical and signal-processing
`parameters are systematically varied. A brute-force approach would try
`every combination of every parameter. For today’s complex systems, the
`number of variables would make this a cost-prohibitive task. A more elegant
`approach would make use of existing knowledge, at least to eliminate certain
`combinations of parameters, and perhaps even to find an efficient path
`through the multivariable space that arrives at a unique, repeatable solution.
`Today, automated recipe creation results in a recipe that sometimes
`can benefit from further optimization by a well-trained engineer. Improving
`automated recipe-creation algorithms is an area of focus for developers of
`wafer inspection tools, due to its importance in increasing the overall
`effectiveness of the equipment.
`Automatic Defect Classification (ADC). One of the biggest bottle-
`necks in the inspection process is classification of defects, a necessary step
`to determining and eliminating their source. At present, most defect classifi-
`cation is still manual, requiring a trained operator to judge a microscope image
`and sort defects into categories based on the operator’s experience (often
`using a reference book containing pictures of “typical” defects). This process
`is limited in speed, accuracy and repeatability, and thus does not fit well into
`an industry driven by time to market and cost control.
`For these reasons automatic defect classification (ADC) has gained
`tremendous attention of late. ADC has begun to reduce significantly the
`amount of manual classification needed, increasing the throughput of the
`classification process, and reducing subjectivity and error from operator
`classification.[5] ADC thus enables more and better analysis of defect
`information.
`The current implementation of ADC begins first by teaching the
`system to recognize the defect types by providing it with clear example
`images. Then during actual automatic classification a review microscope
`(off-line or built into the inspection tool) drives to the coordinates of the
`detected event on the wafer and re-detects the event within the field of view.
`The review station generates a digital image of the event using traditional
`optical, confocal or SEM-based techniques. The ADC algorithm then
`extracts features from the event and compares those features statistically to
`the example images. The output includes a classification for the event along
`with a goodness-of-fit value that describes the image’s similarity to the
`images from the example defects in its class.
`
`Applied Materials, Inc. Ex. 1023
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 16 of 49
`
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`254 Thin-Film Deposition Processes and Technologies
`
`The ultimate implementation of ADC would be for classification to
`happen in parallel with inspection, without having an impact on inspection
`throughput. Partial accomplishment of the goal of real-time ADC is available
`today using the techniques of real-time grouping and/or spatial signature
`analysis.
`Real-time grouping (also called real-time defect cl