Metrology needs for the semiconductor
`industry over the next decade
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`Cite as: AIP Conference Proceedings 449, 3 (1998); https://doi.org/10.1063/1.56823
`Published Online: 27 March 2008
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`Mark Melliar-Smith, and Alain C. Diebold
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`AIP Conference Proceedings 449, 3 (1998); https://doi.org/10.1063/1.56823
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`449, 3
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`© 1998 American Institute of Physics.
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`Applied Materials, Inc. Ex. 1021
`Applied v. Ocean, IPR Patent No. 6,836,691
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`Metrology Needs for the Semiconductor Industry Over the Next Decade Mark Melliar-Smith Alain C. Diebold SEMATECH • 2706 MontopoI& Drive • Austin, TX 78741 Metrology will continue to be a key enabler for the development and manufacture of future generations of integrated circuits. During 1997, the Semiconductor Industry Association renewed the National Technology Roadmap for Semiconductors (NTRS) through the 50 nm technology generation and for the first time included a Metrology Roadmap (1). Meeting the needs described in the Metrology Roadmap will be both a technological and financial challenge. In an ideal world, metrology capability would be available at the start of process and tool development, and silicon suppliers would have 450 mm wafer capable metrology tools in time for development of that wafer size. Unfortunately, a majority of the metrology suppliers are small companies that typically can't afford the additional two to three year wait for return on R&D investment. Therefore, the success of the semiconductor industry' demands that we expand cooperation between NIST, SEMATECH, the National Labs, SRC, and the entire community. In this paper, we will discuss several critical metrology topics including the role of sensor-based process control, in-line micros- copy, focused measurements for transistor and interconnect fabrication, and development needs. Improvements in in-line micros- copy must extend existing critical dimension measurements up to 100 nm generations and new methods may be required for sub 100 nm generations. Through development, existing metrology dielectric thickness and dopant dose and junction methods can be extended to 100 nm, but new and possibly in-situ methods are needed beyond 100 nm. Interconnect process control will undergo change before 100 nm due to the introduction of copper metallization, low dielectric constant interlevel dielectrics, and Dama- scene process flows. INTRODUCTION Integrated circuits (ICs) are the cornerstone of a multi- billion dollar electronics industry that is leading civilization into the 21 st century. IC technology is being driven by con- sumer demands for improved applications, such as informa- tion processing and communications, with greater capability at a constant cost. Thus, consumers have forced the histori- cal trend of a 25 to 30% cost reduction per trait function per year. More than 30 years ago, Gordon Moore observed that the number of transistors in a manufactured die increased by a factor of two every year (2). From this observation, it was postulated that the number of bits in memory chips would increase by a factor of four every three years. A 30% de- crease in feature size every three years and a 1.5x increase in chip size are two of the factors that enable the continuation of Moore's law. The other factors that have kept the industry on the historical cost reduction trend are yield improvement, wafer size increase, and overall equipment effectiveness. The cost productivity curve is shown in Fig. 1. The overwhelming cost of research and development including product development for each new technology gen- eration has forced international cooperation for the semicon- ductor industry. For example, the total cost of developing 300 ram-wafer-capable manufacturing is estimated to be more than $10 billion, and the development of 193 nm lithography C 0 0 E~ e- e- Present eature Size afer Size J Improvement "~rall Equipment Productivity r I "'- ] improvement _ II Time FIGURE 1. Historical Trend of 25-30% Annual Cost Reduction per Unit Function for the Semiconductor Industry. is estimated at around $1 billion (3). One example of coop- eration is the National Technology Roadmap for Semicon- ductors (1). The 1992, 1994, and 1997 Roadmaps provide a consensus view of the most critical technology requirements for IC manufacture with a 15 year horizon. The 1997 NTRS projects these technology needs to the 50 nm technology generation. The NTRS allows R&D organizations such as SEMATECH, SRC, MARCO, and interested national labo- CP449, Characterization and MetroIogy for ULSI Technology: 1998 International Conference edited by D. G. Seller, A. C. Diebold, W. M. Bullis, T. J. Shaffner, R. McDonald, and E. J. Waiters © 1998 The American Institute of Physics 1-56396-753-7/98/$15.00 3
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`ratories to focus their resources on the most critical require- ments and plan activities according to the industry's imple- mentation timeline (1). Metrology enables the lithography, wafer size, yield, and equipment effectiveness drivers of cost reduction, and there- fore metrology technology needs to keep pace with process technology. In addition, metrology must also enable the rapid introduction of new products which require the "ramping within ramps" such as the manufacture of higher speed ver- sions of a generation of microprocessor (4). For the first time, the 1997 version of the NTRS contains a Metrology Road- map. In this paper, we will describe the industry's metrology needs over the next ten years using the 1997 NTRS for tech- nical guidance. The 1997 NTRS describes the key challenges that the in- dustry faces if it is to keep on the historical cost-productivity curve (1). These critical industry challenges provide a means ofprioritizing metrology requirements. The overall challenges are listed below with a brief description (1): The ability to continue affordable scaling Cominue the roadmapped timeline for new technol- ogy generations Affordable lithography at and below 100 nm Move to 193 nm optical lithography and find afford- able replacements for optical lithography New materials and structures Short term: replace aluminttm/silicon dioxide intercon- nect materials with copper and low dielectric constant materials including appropriate cost saving Damascene processes; Long Term: f'md a solution for transistor design and materials for sub 100 nm technology gen- erations GHz frequency operation on- and off-chip High-frequency on-chip interconnects and off-chip packaging based interconnects must allow full utiliza- tion of increases in chip speed Metrology and test This paper describes the required metrology, and elec- trical testing of chip functionality must remain cost- effective as chip functionality increases The research and development challenge Provide an affordable infrastructure that moves tech- nology from basic research into manufacturing Metrology needs must be prioritized and developments driven to enable the key processing technology that wilt al- low us to maintain the cost reduction trend and profit mar- gins that maintain an economically healthy industry. In a per- fect world, metrology capability would be available when process tool suppliers initiate tool development for the next technology generation (1). Unfortunately, this forces the me- trology suppliers to wait three years longer than process tool suppliers for a return on their investment in new tool devel- opment. The same principle applies to changing wafer size, and time for return on investment will be longer than three years for 300 mm wafer metrology tools. The entire commu- nity must cooperate to overcome this challenge. The Metrology Roadmap describes the requirements and potential solutions for the off-line, in-line, and in-situ mea- surements. Other metrology needs are found in the Defect Reduction Technologies Roadmap. In Fig. 2, an overview of the multiple measurement requirements is depicted in terms of the fab process flow. Transistor-* ,= A Left, A Vt, x~" Interconnect-. circuit delay, \ ~ --~ °+ via resistance \ ~ =~ ¢ Leqend o:o Overlay ¢= Implant Dose (,- Gate Ox Thickness X Poly Sl Control OCD [] ILD Thickness • Contact Etch Control ¢- ILD Etch Control ~r Metal Thickness ¢ Particle/Defect Detection FIGURE 2. In-FAB Metrology Metrology is used to control fabrication processes so that integrated circuit electrical performance falls within product specifications. At the 150 nm technology generation, there will be approximately 500 process steps requiring more than 20 overlay and 35 CD measure- ments. In addition to fab process metrology, packaging metrol- ogy is covered in the 1997 NTRS. Metrology is expected to continue to migrate from off-line toward in-line and in-situ application. However, off-line measurements will continue to provid e highly detailed information that requires special capabilities. For example, transmission electron microscopy (TEM) is often the only means of analyzing small features found in modem IC's. Evolutionary improvements of cur- rent in-line metrology methods are expected to enable con- trol of implant and thin fill processes. Currently, many tran- sistor and interconnect processes are controlled using physi- cal measurements on unpattemed (test) wafers. The need for nondestructive measurements on product wafers is an addi- tional challenge for in-line metrology. Initial implementation of in-situ sensor-based process control has proven the use- fulness of this approach through improved tool throughput and reduced wafer scrap. Many of these sensors measure something that allows control of wafer level properties, of- ten indirectly. In addition to increasing their range of appli- cations, sensors are expected to evolve to provide more de-
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`tailed information on the wafer with increased spatial reso- lution (i.e., die to die uniformity). Micro-electromechanical systems (MEMS) are expected to become the smart sensors of the future (1). One visionary example is an etch chamber with a strategically located mass spectrometer on a chip with built-in circuitry for real time process control. Packaging me- trology is not as mature as wafer lab metrology, and thus there are many opportunities to implement existing technol- ogy as well as to develop appropriate new methods. The advantages of in-line measurements, such as improved analysis cycle time, have resulted in the "FAB-LAB" con- cept (5,6). The laboratories contain tools and data manage- ment/analysis systems capable of characterizing product wafers using information such as particle/defect location maps (5). The FAB-LAB is an integral part of pilot line as well as fab start-up and operation, and there are examples of FAB- LABs both inside and next to the clean room. It is interesting to note that some IC manufacturers have located tradition- ally out of the fab tools such as TEM inside clean rooms. This is one example of how the need to reduce the cycle time for product development and yield learning has driven the industry. The relationship between analysis cycle time re- quirements and the proximity of analysis tools to the fabrica- tion line has been described elsewhere (5). THE MEASUREMENT REQUIREMENTS AND FUTURE OF STATISTICAL PROCESS CONTROL Statistical Process Control (SPC) methodology is used to control each IC manufacturing process so that a majority of the fmal product has a narrow range of electrical characteris- tics. In this section, we emphasize the need for process ap- plication based evaluation of metrology tools capability for use in SPC. Automated ha-line and appropriate off-line me- trology tools are evaluated for SPC by the measurement pre- cision to process tolerance (process specification range) ra- tio criterion, P/T. The P/T should be < 10%, but 30% is often tolerated. P/T = 6o/(UL-LL) where the measurement preci- sion (variation), o, includes the short-term repeatability and long-term reproducibility, and LrL and LL are the upper and lower process limits, respectively. The P/T metric is well ac- cepted by the semiconductor industry. Determination of the true P/T ratio for the process range of interest requires careful implementation of the P/T meth- odology and reference materials with identical feature size, shape, and composition to the processed wafer being mea- sured. Often, there are no certified reference materials that meet this requirement, and P/T ratio and measurement accu- racy are determined using best available reference materials. One key example is the lack of an oxide thickness standard for sub 5 nm SiO 2 and nitrided oxides. Another aspect of true determination of P/T capability is measurement linearity. If one determines the P/T ratio for a thickness or width measurement using a reference material that has larger (or smaller) dimensions than the features be- hag measured during IC manufacture, lack of measurement linearity could result in insufficient resolution to distinguish changes over the entire process range of interest. For the sake of argument, we will call tool precision determined using in- adequate reference materials as "estimated tool precision." Often, the concept of measurement resolution is confused with "estimated tool precision." It is possible for a tool to appear to have small (i.e., good) precision and still have poor resolution. As transistor and interconnect features shrink, greater resolution is becoming more critical. The criteria for metrology tool applicability to SPC need to include both P/T and resolution. For example, we need to be able to distinguish a 2.0 nm thick transistor gate dielectric fi-om a film having 2.1 nm or 2.2 nm thickness. Another example is distinguishing a 100 nm gate electrode width (critical dimension, CD) from a 102 nm CD. SPC criteria are usually applied to physical mea- surements, but electrical measurement variability also needs to be suitably small. Another example of the varied and thus confusing usage of the term resolution is in critical dimension (CD) measure- ment by scanning electron microscopy (SEM). The micros- copy community has used two different methods to deter- mine the resolution of a scanning electron microscope (SEM). One is the width of the electron beam, and the other is the ability to distinguish two closely spaced features in an image of a well characterized test sample. Fine gold particles on a carbon background is a well accepted test sample. Despite the long history of these methods, there do not seem to be standardized (SEMI, ASTM, etc.) resolution pro- cedures. Another measure of the resolution of an SEM dedi- cated to CD measurement is its ability to distinguish repeat- edly differences in transistor gate linewidth (e.g., 100 nm fzom 102 nm). This process application based metric for reso- lution would facilitate evaluation of true SPC capability. One way to assure that the metrology tool has adequate resolution is to determine the true P/T capability by using a series of standardized, accurate reference materials over the measurement range specified by the upper and lower pro- cess limits. In Fig. 3, we depict how the multiple reference materials approach might work. We note that some measure- ments may require one suitable reference material for P/T determination.
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`(a) Bias in Product Wafer Measurements Instrument Calibration X2a~ e X2~ XI.~ XI~.~ Bias and precision changes due to non-linearity Calibration Bias 1 2 3 4 5 6 7 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 A Measurement variation (precision) of expcfimcntaUy determined values of reference materi~d FIGURE 3. Relationship between Measurement Resolution and Precision (a) Measurement non-linearities can result in bias (difference be- tween true and measured value) changes between the cali- brated value and values within the range of interest. (b) For this example let us assume that the process tolerance (also called process specifications) is from 3.0 nm to 4.6 urn. The measurement precision at 30 (variation) is shown for refer- ence materials inside the process range. The experimental P/T capability observed using reference materials 4, 5, and 6 indi- cates that a single measurement of a 4.0 nm is different from one at 3.8 nm or 4.2 nm. Thus this fictitious metrology tool can resolve those values. The tool is not able to resolve 3.4 nm from 3.6 nm at 3o. A SEMI task force will be standardizing the implementa- tion of P/T over the next several years. This type of activity can greatly improve the usefulness of the P/T metric, and perhaps it could be called the "Resolution P/T." Implemen- tation of this methodology is hampered by the lack of refer- ence materials with features (size, composition, etc.) inside the measurement range of interest. The goal of sensor-based process control is to become real time. In-line measurement tools are (when appropriate) used for run to run control. The concept of P/T must be ex- tended to allow evaluation of sensors. Sensors appear to have the interesting challenge of being required to measure pro- cess variation without the luxury of averaging over multiple measurements to improve precision. One revolutionary improvement in SPC has been the use of cumulative data sets (from the same sample, across a wa- fer, and previous samples) to greatly improve estimation of measurement precision (6, 7). A smaller estimated precision may mean that a metrology tool is capable of meeting P/T criteria for SPC without hardware improvements or it can allow reduction of process tolerances while maintaining P/T. Since this improvement was not associated with the mea- surement tool itself, it raises questions about how to evaluate improvements in metrology tools. CORRELATION OF PHYSICAL AND ELECTRICAL MEASUREMENTS IC performance and yield are ultimately evaluated by the electrical parametric and functional testing. It is possible to measure the relevant electrical properties of transistor and interconnect structures on product wafers during IC manu- facture. Clearly, this requires that the wafers have been pro- cessed to the point where a complete transistor (or intercon- nect structure) is fabricated. When the manufacturing pro- cess is mature and robust and a majority of the process flow is transferred to the next product or technology generation, electrical metrology may provide a majority of process con- trol needs. However, when excursions in process tool perfor- mance or process material quality occur, they need to be ob- served and controlled long before an electrical test can be performed. In this section, we describe several levels of cor- relating physical and electrical measurements. These levels can be described as follows: correlation of electrical and physical measurements of a specific physical feature such as gate dielectric thickness; correlation of a set of physical pa- rameters with the electrical properties of the transistor or in- terconnect structure; and correlation of die, wafer, or lot level data with yield. Since scrap prevention is one of the goals of physical, in- line metrology, physical measurement must correlate with electrical performance. The gate dielectric thickness, gate electrode critical dimension, and implant dose and profile all influence transistor electrical parameters such as threshold voltage, off current, and gate delay. Modeling of transistors provides insight into the nature of the correlation of physical parameters with electrical performance, including manufac- turing sensitivities (8).One can model the change in varia- tion of electrical parameters using device simulation and se- lected ranges of physical parameter variation. The variation of threshold voltage range with range of gate length and chan- nel implant is shown for a fixed range of gate dielectric thick- ness and other physical parameters in Fig. 4. Zeitzoff and Tasch discuss manufacturing sensitivity in these proceedings (8). Another issue is that integrated circuit development re- quires statistically significant information which can only come from electrical test. The need for early measurement capability during process tool development is highlighted by the push for more rapid ramping of pilot line yield. Delivery of well characterized process tools greatly facilitates rapid pilot line yield ramping. Bartelink is credited with initiating the field of Statistical Metrology which utilizes electrical test structures to determine across the die and across the wafer properties (9, 10). Statistical Metrology is a set of procedures designed to deconfound measurement error from true pro- cess variation. Statistical Metrology is discussed in the Pro- tess Integration, Devices, and Structures Roadmap and the Metrology Roadmap's one page contribution to that road- map (1).
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`3 Sigma V t lO 7.5 A No. A Tox=5% 5 4.5 8 11.5 15 A Lg (effect of CD variation on 180 nm transistor) used to determine the source of process defects. The defect detection and silicon materials communities have provided the customer drive for development of software systems. These software systems are typically part of the total support provided by suppliers of defect detection equipment. Some of these systems have already been generalized to include data and analysis from all metrology capability. In the future, data management systems are expected to merge into Com- puter Integrated Manufacturing (CIM) systems where their full potential can be realized (2,15). Integration of sensor- based process control, off-line and in-line metrology, and de- fect metrolog3/data management and analysis into CIM will allow true factory and electrical performance control (1, 15). FIGURE 4. Modeling Manufacturing Sensitivity for a Transistor at the 180 nm Technology Generation The 3o variation in threshold voltage is plotted as a function of the variation in gate length (critical dimension) and channel implant dose. The variation of oxide thickness was kept at 5%. Figure courtesy Tasch and Zeitzoff(8). In its most general sense, "Defect to Fault" mapping is another aspect of correlating physical phenomena with elec- trical performance (11, 12). Defect to Fault mapping/model- ing uses a hierarchical set of modeling tools that connects process and device modeling to circuit design/operation mod- eling. The concept is a generalization of the manufacturing sensitivity modeling discussed above. Defect to Fault mod- eling can be used to implement Statistical Metrology. We wilt use two examples to illustrate the different applications of "Defect to Fault" Modeling. The first type of application models the effect of parametric variations on circuit peformance. The effect of changes in average gate length on chip-level electrical performance such as circuit speed or the effect of an increased range of threshold voltages can be modeled. The second application is to yield limiting defects. A physical fault such as a short between metal lines can be placed in the circuit design, and the resulting distinctive elec- trical signature of this defect is calculated. Present genera- tion software utilizes in-line metrology including defect de- tection and electrical test data from pilot line fabrication of memory test vehicle as an experimental database. Experi- mental data are used to verify and calibrate the models. The goal of this approach is to design circuits that are less sus- ceptible to manufacturing variation and physical defects. Again, this methodology requires mature metrology capabil- ity for pilot line measurement of next generation process flows and tools. "Defect to Fault" modeling soft-ware is being de- veloped through university-industry cooperation. Pilot line and lab defect databases are another critical part of correlating physical and electrical measurements. Cumu- lative use of wafer maps often shows systematic process is- sues (13, 14). For example, adding the wafer maps from a single lot or from several lots can show clusters of defects in a particular area of the wafer (13, 14). This information is INFLUENCE OF MANUFACTURING STRATEGY ON METROLOGY IMPLEMENTATION IC manufacturers have a variety of approaches to manu- facturing that match their products. Some manufacture a very small number of similar products, such as microprocessors (or memories), with a small variety of process flows in very high volume fabs. Others manufacture a large variety of prod- ucts (such as ASICs) with several process flows at small to medium volume. The goal of many manufacturers is to send a robust, high-yielding process flow from development (pi- lot line) to fab with little or no change. This is possible when a considerable effort is made to characterize process tools and flows in a statistically significant manner. Fabs having robust process flows seem to need less in-line metrology than fabs that must alter process flows to accommodate many dif- ferent products. Manufacturing strategy has a large impact on the type of metrology tool used during manufacturing. Some metrology tools are engineering intensive. These tools provide more de- tailed information. Examples include focused ion beam (FIB) systems, scanning electron microscopes equipped with en- ergy dispersive x-ray detection (SEMfEDS), and unpattemed wafer defect detection (2). Defect autoctassification is also used in this manner (2, 15, 16). A manufacturing strategy that transfers a high yielding process flow from pilot line to volume FAB would minimize use of these tools after suc- cessful yield ramping. We also note that the need to ramp pilot line yield more rapidly is expected to push more of the detailed characterization back into process tool development (2, 15, 16). The move to eliminate setup and monitor wafers implies the use of product wafer metrology. This trend is often given as a driver for in-situ sensor-based tool control because many in-fab metrology tools use monitor wafers. 7
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`CRITICAL CHALLENGES FACING METROLOGY 111 the 1997 NTRS, the most difficult challenges for me- trology centered around the changes associated with manu- facturing before and after the 100 nm technology generation (1). Many of these challenges are due to the introduction of new materials or processes such as high-k transistor dielec- tric, copper metallization, low-k dielectrics, and Damascene (in-laid metal) processing. Other challenges are a result of shrinking device features. Indirectly this is also true for physi- cal measurements of transistor processes which must improve so that they provide the same control as electrical measure- ment of transistor parametrics. The ten most critical chal- lenges facing metrology are (1): Five Difficult Challenges for > 100 nm before 2006 Robust sensors, process controllers, and data manage- ment that allow integration of add-on sensors. Metrology for silicon wafers -- impurity detection (par- ticles, oxygen, and metallics) at levels of interest for starting materials. High-frequency dielectric constant for new ILD mate- rials -- measurement of frequency dependent dielec- tric constant of low-k interconnect materials at 5X to 10X base frequency. Metrology for new interconnect processes -- control of new process such as Damascene (in-taid metal) and copper metallization. Reference materials and standard methods for gate di- electrics, thin films, and other process needs. Five Difficult Challenges for < 100 nm beyond 2006 • In-line microscopy -- non-destructive, manufacturing capable microscopy for critical dimension measure- ment, defect detection, and analysis • Gate oxide reliability testing -- standard electrical test method for reliability of ultra thin silicon dioxide and new gate dielectric materials • Metrology tools for 450 mm wafers • 3D dopant profiling • Transistor fabrication metrology-- manufacturing ca- pable, physical in-line metrology for transistor process that provides statistical process control (SPC) required for electrical properties of the transistor. Metrology Technology Requirements Future measurement requirements are driven by the pro- cess, device, and structure requirements predicted by the fo- cused technology roadmaps from lithography, transistor (front end processes) and interconnect, and process integration road- maps. Many of these requirements cross the boundaries of the focused technology areas. Examples of this include mi- croscopy, materials and contamination characterization, and dopant characterization. Microscopy will be applied to criti- cal dimension, in-line particle and defect characterization, and defect detection. In-line and off-line dopant character- ization requirements come from NTRS sections on implant process development, modeling and simulation, and process integration. Other requirements for integration of metrology tools into the pilot line and lab computer integrated manu- facturing (CIM) systems for metrology and defect data man- agement and analysis are described in the Factory Integra- tion Roadmap and standards documents from SEMI. In Table 1, we show the Metrology Technology Requirements from the Metrology Roadmap, along with key technology require- ments from the Front End Processes (transistor fabrication processes), and Interconnect Roadmaps. The Lithography Metrology Requirements are listed in the Lithography sec- tion of this paper. We included process technology require- ments in this section to illustrate NTRS process development issues that will require advances in metrology. For example, the increase in the aspect ratio of interconnect structures will drive requirements for process control microscopy. ADVANCED MICROSCOPY DEVELOPMENT (As applied to Critical Dimension, Defect Detection, and Materials and Contamination Characterization) The Metrology Roadmap emphasizes the need to acceler- ate longer term research and development of microscopy for all areas. Microscopy is used in most metrology tools. Ex- amples of the use of microscopy include critical dimension and overlay measurement, off-line characterization, defect detection and autoclassificatiorg optical microscopes used for pattern recognition and focusing in both process and metrology tools, and failure analysis. New microscopy capa- bility is typically frrst utilized for materials characterization and then it quickly migrates to lithography applications. One example of this migration is low voltage scanning electron microscopy. The low voltage SEMs moved from off-line char- acterization of insulating materials such as ceramics into criti- cal dimension measurement. Low voltage operation required the development of new electron optics and field emission sources capable of high resolution at low electron beam en- ergies. Defect detection applications of microscopy require higher throughput, and thus microscopy developments mi- grate more slowly into this area. Clearly, microscopy research and development has cross-functional applications and is found in the main section of the Metrology Roadmap. The Metrology roadmap lists microscopy for sub 100 nm tech- nology generations as a critical metrology challenge. In this
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`TABLE 1. Metrotogy Technology Requirements Year of First Product Shipment Technology Generation Inline, nondestructive microscopy resolution (CD precision is different from resolution) (nm) Particle analysis size (on patterned wafers) (nm) Surface detection limits AI, Ti, Zn)/ (Ni, Fe, Cu, Na, Ca) atoms/cm 2) Front End (Transistor) Processes Wafer diameter (ram) Oxygen (tolerance + 1.5 ppma) ASTM '79) * Localized Light Scatterers (LLS) (includes particles) (nm) ** Composition and thickness gate dielectric (equivalent film thickness + 3o control) (nm) 2- and 3-D dopant profile spatial resolution (nm) Dopant concentration precision across concentration range)*** Interconnect Processes Pla