`FOR THE EASTERN DISTRICT OF TEXAS
`SHERMAN DIVISION
`
`OCEAN SEMICONDUCTOR LLC,
`
`Plaintiff,
`
`v.
`
`HUAWEI DEVICE USA, INC.,
`HUAWEI DEVICE CO., LTD.; and
`HISILICON TECHNOLOGIES CO.,
`LTD.,
`
`Defendants.
`
`No. 4:20-cv-991
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`Jury Trial Demanded
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`DEFENDANTS’ INVALIDITY CONTENTIONS
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`Pursuant to the Court’s Scheduling Order dated August 3, 2021, P.R. 3-3 and the Parties’
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`agreement, Defendants Huawei Device USA, Inc. (“HDU”), Huawei Device Co., Ltd. (“Huawei
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`Device”), and HiSilicon Technologies Co., Ltd. (“HiSilicon”) (collectively, “Huawei” or
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`“Defendants”) provide these Invalidity Contentions regarding U.S. Patent Nos. 6,660,651 (“the
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`’651 patent”), 6,907,305 (“the ’305 patent”), 6,725,402 (“the ’402 patent”), 6,968,248 (“the ’248
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`patent”), 7,080,330 (“the ’330 patent”), 6,836,691 (“the ’691 patent”), and 8,676,538 (“the ’538
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`patent”) (collectively, “the Asserted Patents”).
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`Plaintiff Ocean Semiconductor LLC (“Ocean”) alleges in its August 16, 2021, Preliminary
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`Disclosure of Asserted Claims and Infringement Contentions that Defendants infringe the
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`following claims of the Asserted Patents (collectively, the “Asserted Claims”):
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`Patent
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`6,660,651
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`6,907,305
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`6,725,402
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`6,968,248
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`8,676,538
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`7,080,330
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`6,836,691
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`Asserted Claims
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`Claims 19, 20, 21, 22, 23, 24, 31, 32, 34, 35, 36, 37,
`72, 73, 74, 75, 77, 78, 79, 80, 81
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`Claims 1, 2, 3, 5, 7, 10, 11
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`Claims 1, 2, 3, 4, 5, 6, 7
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`Claims 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12
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`Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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`Claims 19, 20, 21
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`Claims 1, 2, 3, 4, 5, 6, 7, 8, 9
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`Defendants reserve the right to supplement and/or amend these Invalidity Contentions
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`should Plaintiff supplement and/or amend its Preliminary Infringement Contentions or otherwise
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`-2-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`alter its theory of the case.1 Nothing in these Invalidity Contentions constitutes an admission of
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`validity as to any other non-asserted claims of the Asserted Patents.
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`As discussed below, Defendants contend that each Asserted Claim is invalid under at least
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`35 U.S.C. §§ 101, 102, 103, and/or 112.
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`A.
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`PRELIMINARY STATEMENT AND RESERVATION OF RIGHTS
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`Defendants’ Invalidity Contentions reflect its present knowledge and understanding of
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`Ocean’s Preliminary Infringement Contentions regarding the Asserted Claims. Defendants’
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`Invalidity Contentions are based on Defendants’ current knowledge, understanding, and belief as
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`to the facts and information available as of the date of these Invalidity Contentions. Defendants
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`have not yet completed their investigation, discovery, or analysis of matters relating to the
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`invalidity of the Asserted Claims, including without limitation invalidity due to on-sale or public
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`use statutory bars. In addition, Defendants’ search for prior art is ongoing. Accordingly,
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`Defendants reserve the right to amend, modify, and supplement, without prejudice, these Invalidity
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`Contentions as additional information is discovered or otherwise identified or appreciated,
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`including testimony about the scope and content of the claimed inventions or state of the prior art.
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`Defendants provide these Invalidity Contentions without waiving Defendants’ position that
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`Ocean’s Infringement Contentions do not adequately identify with sufficient specificity the basis
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`for Ocean’s contention that any accused product is manufactured by a process that meets the
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`limitations of any of the Asserted Claims. Nothing stated herein is or shall be treated as an
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`admission or suggestion that Defendants agree with Ocean regarding either the scope of any of the
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`
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`1 Including in view of any inconsistent positions Ocean may take between inter partes review
`proceedings relating to the Asserted Patents, e.g., in its preliminary responses and other briefing,
`and this litigation.
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`-3-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`Asserted Claims or the claim constructions advanced directly or implicitly by Ocean’s Preliminary
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`Infringement Contentions or in any other pleading, discovery request or response, or written or
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`verbal communications with Defendants. Additionally, nothing in these Invalidity Contentions
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`shall be treated as an admission that any accused products meet any limitation of the Asserted
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`Claims. The disclosures herein are not and should not be construed as a statement that no other
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`persons have discoverable information, that no other documents, data compilations, or tangible
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`things exist that Defendants may use to support its claims or defenses, or that no other legal theories
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`or factual bases will be pursued.
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`In the absence of a claim construction order from the Court, Defendants have based these
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`Invalidity Contentions upon their knowledge and understanding of the potential scope of the
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`Asserted Claims at this time, and, in part, upon the apparent constructions of the Asserted Claims
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`advanced by Ocean in its Preliminary Infringement Contentions. Furthermore, Ocean’s
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`Preliminary Infringement Contentions contradict how a person of ordinary skill in the art would
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`understand the Asserted Patents and the claim terms, and are vague and conclusory concerning
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`how certain claim limitations supposedly read on the accused products or activities. Thus,
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`Defendants are unable to discern Ocean’s position regarding the construction of numerous claim
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`limitations and has provided these Invalidity Contentions based in part on its present understanding
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`of Ocean’s apparent constructions. Finally, Defendants’ Invalidity Contentions do not represent
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`Defendants’ agreement or view as to the meaning of any claim term contained therein, and
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`Defendants may disagree with Ocean’s interpretation of the meaning of terms and phrases in the
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`Asserted Claims. In addition, Defendants’ Invalidity Contentions do not represent Defendants’
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`agreement or view as to whether any claim preamble is limiting.
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`-4-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`Defendants also anticipate that the Court’s construction of claim terms may significantly
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`affect the scope of the Asserted Claims. Therefore, Defendants reserve the right to supplement,
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`without prejudice, these Invalidity Contentions as appropriate depending upon the Court’s
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`construction of the Asserted Claims, any findings as to the priority date of the Asserted Patents,
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`and positions that Ocean or its expert witnesses may take concerning claim interpretation,
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`infringement, or invalidity issues.
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`Defendants provide claim charts as described herein. The claim charts reflect the theories
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`of invalidity described in each chart, including anticipation and obviousness. The suggested
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`obviousness combinations are in the alternative to Defendants’ anticipation contentions. The
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`disclosed obvious combinations are not meant to be exhaustive and should not be construed to
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`suggest that any reference does not anticipate claims of the Asserted Patents. As reflected in the
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`attached exhibits, the discussion herein, and in the references themselves, all elements of Ocean’s
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`Asserted Claims were disclosed in the art and in the general knowledge of a person of ordinary
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`skill before the Asserted Patents’ earliest possible priority date. Furthermore, one of ordinary skill
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`in the art would have readily combined their teachings. Each of the references cited herein,
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`including the identified prior art systems, or in the attached exhibits may be combined and
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`modified in several obvious ways to achieve the claimed systems and methods, including those
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`disclosed in the attached exhibits or the discussion herein.
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`Defendants further contend that various asserted claims of the Asserted Patents are invalid
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`under 35 U.S.C. § 101 for failure to claim patentable subject matter and/or under 35 U.S.C. § 112
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`for failure to satisfy the enablement, written description, and/or definiteness requirements.
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`Defendants’ contentions of invalidity under § 101 and/or § 112 are based in whole or in part on
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`their present understanding of the Asserted Claims and Ocean’s apparent construction of those
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`-5-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`claims in its Preliminary Infringement Contentions. Accordingly, Defendants’ Invalidity
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`Contentions may reflect alternative positions as to claim construction and scope of the Asserted
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`Claims. Further, by asserting grounds for invalidity based on Ocean’s apparent claim construction
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`or any other particular claim construction, Defendants are not adopting Ocean’s claim
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`construction, or admitting to the accuracy of any particular claim construction.
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`Defendants provides invalidity claim charts as exhibits as shown below:
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`Patent
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`6,660,651
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`6,907,305
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`6,725,402
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`6,968,248
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`8,676,538
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`7,080,330
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`6,836,691
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`Exhibits for Corresponding Charts
`
`A
`
`B
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`C
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`D
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`E
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`F
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`G
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`B.
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`PRIORITY AND CONCEPTION DATES FOR THE ASSERTED CLAIMS
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`In its Preliminary Infringement Contentions, Ocean contends that the Asserted Claims of
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`some Asserted Patents are entitled to priority based on the filing dates of U.S. Application No.
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`10/135,145, U.S. Application No. 12/110,798, U.S. Application No. 11/469,194, and U.S.
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`Application No. 11/469,194. Defendants dispute whether any Asserted Claim is entitled to any
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`priority date earlier than the filing dates of the applications for the Asserted Patents.
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`Ocean further contends that the alleged inventions of the Asserted Claims were conceived
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`as of February 12, 2001 for the ’651 patent; January 29, 1999 for the ’402 patent; May 3, 2002 for
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`the ’330 patent; January 7, 2003 for the ’691 patent. Defendants dispute whether any Asserted
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`-6-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`Claim is entitled to a conception date or priority date earlier than the filing dates of the applications
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`for the Asserted Patents.
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`C.
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`INVALIDITY UNDER 35 U.S.C. §§ 102 AND 103
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`Defendants contend that each Asserted Claim is invalid at least under 35 U.S.C. § 102,
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`including pre-AIA subsections 102(a), 102(b), 102(e), 102(g), AIA subsections 102(a)(1) and
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`102(a)(2), and/or under 35 U.S.C. § 103. Defendants’ detailed contentions as to where in each
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`identified prior art reference the asserted claim limitations may be found are attached as Exhibits.
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`For each Asserted Patent, the Exhibits contain a separate chart for each anticipating and/or primary
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`obviousness reference detailing where that reference teaches each limitation of the Asserted
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`Claims. For each Asserted Patent, the Exhibits also contain an omnibus combination reference
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`chart detailing which limitations are taught by each combination reference. Defendant reserves
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`the right to combine each anticipating and/or primary obviousness reference with (1) other
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`anticipating and/or obviousness references, (2) any reference described in the omnibus reference
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`chart, or (3) a combination thereof. Defendant also reserves the right to rely on other references
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`disclosed or incorporated by reference in these Invalidity Contentions, in the Asserted Patents, any
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`patents or applications related to the Asserted Patents, in the file history of the Asserted Patents or
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`any related patents or applications, and in the attached Exhibits.
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`Defendants’ claim charts may disclose multiple theories of invalidity in a single chart.
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`Each chart directed to an anticipatory product/system may also describe that the product/system
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`alone, in light of the knowledge and skill in the art, or in light of one or more other prior art
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`references, renders each Asserted Claim obvious.
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`Where Defendants cite to a particular figure in a prior art reference, the citation should be
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`understood to encompass the caption and description of the figure as well as any text relating to
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`the figure in addition to the figure itself. Conversely, where a cited portion of text refers to a
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`-7-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`figure, the citation should be understood to include the figure as well. Furthermore, while
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`Defendants have generally identified at least one citation per limitation present in a reference or
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`combination, each and every disclosure of the same or similar limitation in the same reference or
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`combination is not necessarily identified. To focus the issues, Defendants cite only certain
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`portions of identified references, even where a reference or combination may contain additional
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`support for a particular claim element. Thus, Defendants may rely on uncited portions of the prior
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`art references for additional support for a particular element. Defendants may rely upon other prior
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`art identified in future supplements, corroborating references, documentation, source code,
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`products, and testimony, including materials obtained through further investigation and third-party
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`discovery of the prior art identified herein, that demonstrates the invalidating functionality
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`identified in these Invalidity Contentions or that show the state of the art in the relevant time period
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`(irrespective of whether such references themselves qualify as prior art to the Asserted Patent),
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`and expert testimony to provide context to or aid in understanding the cited portions of the
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`identified prior art. Similarly, where there are multiple references relating to a single prior art
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`product or system, Defendants may cite only to a single reference for a particular limitation, even
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`though other references may also contain similar teachings. Thus, Defendants may rely on uncited
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`references relating to a particular prior art document or system for additional support for a
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`particular element. Any prior art disclosed as anticipating a limitation also renders that limitation
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`obvious.
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`Certain of the Asserted Claims are also invalid due to obviousness-type double patenting
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`based on the grounds discussed in Section d.3 below.
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`Additionally, persons of ordinary skill in the art at the time of the alleged inventions
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`generally read a prior art reference as a whole and in the context of other publications and literature.
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`-8-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`Numerous prior art references, including those identified herein and in the attached exhibits, reflect
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`common knowledge and the state, scope, and content of the prior art before the priority date of the
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`Asserted Claims of the Asserted Patents. Defendants may rely on uncited portions of the prior art
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`references and on other publications and expert testimony to provide context and as aids to
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`understanding and interpreting the portions that are cited.
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`In general, a claimed invention is invalid due to obviousness “if the differences between
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`the claimed invention and the prior art are such that the claimed invention as a whole would have
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`been obvious before the effective filing date of the claimed invention to a person having ordinary
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`skill in the art.” 35 U.S.C. § 103; Graham v. John Deere Co., 383 U.S. 1, 13-14 (1966). The
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`ultimate determination of whether an invention is or is not obvious is a legal conclusion based on
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`underlying factual inquiries including: “(1) the scope and content of the prior art; (2) the
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`differences between the prior art and the claims; (3) the level of ordinary skill in the art at the time
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`of invention; and (4) objective evidence of nonobviousness.” Miles Labs., Inc. v. Shandon, Inc.,
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`997 F.2d 870, 877 (Fed. Cir. 1993); see Graham, 383 U.S. at 17-18. The U.S. Supreme Court
`
`decision in KSR Int’l Co. v. Teleflex Inc., 127 S. Ct. 1727, 1739 (2007) reaffirmed Graham, but
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`further held that a claimed invention can be obvious even if there is no explicit teaching,
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`suggestion, or motivation for combining the prior art to produce that invention.
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`To the extent that any claim limitation is not anticipated pursuant to 35 U.S.C. § 102,
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`Defendant contends that any purported differences are such that the claimed subject matter as a
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`whole would have been obvious to one skilled in the art at the time of the alleged inventions, in
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`view of the state of the art and knowledge of those skilled in the art under 35 U.S.C. § 103. Each
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`Asserted Claim would have been obvious in view of each reference cited in the attached Exhibits
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`either alone or combined with the knowledge that was possessed by one of ordinary skill in the
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`-9-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`art. Additionally, each Asserted Claim would have been obvious to one of ordinary skill in the art
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`in view of the combination of any one of the prior art references identified in the attached Exhibits
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`with one or more of the other references identified or discussed in the same Exhibits.
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`In particular, those of ordinary skill in the art at the time of the alleged inventions of the
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`Asserted Patents would have been motivated to modify or combine the prior art references because,
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`for example: (a) the references in general deal with the same or related subject matter; (b) one of
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`ordinary skill in the art would have been motivated by the problem that the inventor was attempting
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`to solve, or with other problems that would have been faced in reaching a solution, and would have
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`looked to references that concerned similar issues or taught how to overcome the problems faced;
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`(c) the combinations were obvious to try and would have operated in their known and expected
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`way; (d) the combinations were within the technical skill and understanding of a person of ordinary
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`skill in the art; (e) the combinations would have been motivated by the developments in
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`technology; and (f) the combinations reflect various design choices that would have been known
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`to one of ordinary skill in the art and within that person’s technical capability to implement (i.e.,
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`technically feasible).
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`The various motivations described above provide a basis for combining or modifying
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`references, as detailed below, to render each of the Asserted Claims obvious. In addition, the Court
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`can consider the inferences and creative steps a person of ordinary skill in the art would employ in
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`making such combinations. See KSR, 127 S. Ct. at 1741 (“a court can take account of the
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`inferences and creative steps that a person of ordinary skill in the art would employ”).
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`If, and to the extent, Ocean challenges the correspondence of the references in the Exhibits
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`with respect to particular limitations of the Asserted Claims of the Asserted Patents, Defendants
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`-10-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`reserves the right to supplement these Invalidity Contentions to identify additional combinations,
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`motivations to modify, or explanations for particular references with additional particularity.
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`Additionally, Defendants believe that certain non-parties and current or former employees
`
`thereof may have possession of relevant information and/or documents constituting prior art to the
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`Asserted Patents, including prior art products and systems. Defendants have identified several
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`prior art products and systems in these Invalidity Contentions. Defendants are continuing their
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`investigation into these and other companies and their products. Defendants reserve the right to
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`supplement these Invalidity Contentions to identify additional references, combinations,
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`motivations to modify, or explanations for particular references based on any information and/or
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`documents provided by the former employees and/or successors-in-interests of companies or
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`individuals who may possess relevant information and/or documents constituting prior art to the
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`Asserted Patents, including information and documents about prior art systems. The concepts
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`disclosed and claimed in each of the Asserted Patents are not new, and had been disclosed, used,
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`offered for sale, sold, and practiced by others prior to the claimed priority date of the patents. The
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`prior art identified herein and in the Exhibits, individually or in combination, invalidates the
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`asserted claims under 35 U.S.C. §§ 102 (a), (b), (e) and §103. Because discovery has not yet begun
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`in earnest, Defendants expect to gather additional information about the identified prior art, and
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`other prior art, through third party discovery or other discovery, and will thus amend and
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`supplement these invalidity contentions once they obtain that discovery and have meaningful and
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`reasonable time to analyze it.
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`Moreover, Defendants reserve the right to rely on inventor admissions concerning the
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`scope of the prior art relevant to the Asserted Patents found in, inter alia, the prosecution histories
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`of the Asserted Patents or related patents and/or patent applications, any testimony or declarations
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`-11-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`of the named inventors concerning the Asserted Patents or related patents, and any papers or
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`evidence submitted by Plaintiff in connection with this litigation, any other pending or future
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`litigation brought by Plaintiff involving the Asserted Patents or related patents, or inter partes
`
`review proceedings involving the Asserted Patents or related patents. Defendants also may
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`establish what was known to a person having ordinary skill in the art through treatises, published
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`industry standards other publications, products, and/or testimony.
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`a. The ’651 Patent
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`1. Identification of Prior Art
`
`The tables below list prior art that anticipates and/or renders obvious one or more of the
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`asserted claims. The attached claim charts in Exhibits A1-A14 demonstrate where each limitation
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`of the claims is found in certain of the references listed below, either expressly or inherently in the
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`larger context of the passage, as understood by a person having ordinary skill in the art. The
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`following patents, publications, products and/or services are prior art under at least 35 U.S.C. §§
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`102(a), (b), or (e).
`
`a. Prior Art Patents, Patent Publications, And Printed
`Publications To The Asserted Claims of the ’651 Patent.
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`Exhibit
`
`Reference
`
`A1
`
`A1
`
`A2
`
`A2
`
`A4
`
`
`
`
`
`
`International Publication No. WO
`01/22480
`U.S. Patent No. 6,940,582
`
`Japanese Patent Application
`Publication No. JP H11-274031
`U.S. Patent No. 6,327,026
`
`Sluijk et al., Performance results of
`a new generation of 300-mm
`lithography systems, Optical
`
`Filing /
`Priority
`Date
`September
`20, 1999
`May 21,
`2001
`March 20,
`1998
`March 17,
`1999
`N/A
`
`Date of Issue
`or
`Publication
`March 29,
`2001
`September 6,
`2005
`October 8,
`1999
`December 4,
`2001
`February 25,
`2001
`
`Short
`Cite
`
`Tanaka
`
`Tanaka
`’582
`Wakui
`
`Wakui
`’026
`Sluijk
`
`-12-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`Exhibit
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`Reference
`
`Microlithography XIV, Proceedings
`of SPIE Vol. 4346, 544-557 (2001)
`U.S. Patent No. 6,416,635
`
`U.S. Patent No. 6,086,727
`U.S. Patent App. Pub. No.
`2002/0039179
`U.S. Patent No. 6,258,220
`
`European Patent Appl. No.
`EP 0 973 067
`International Publication No. WO
`98/022638
`U.S. Patent No. 6,486,492
`
`U.S. Patent No. 6,150,664
`
`U.S. Patent No. 6,861,614
`
`International Publication No. WO
`99/005703
`U.S. Patent No. 6,707,529
`
`Butler, et al., “Scanning stage for
`exposure tools,” Microlithography
`World (Spring 1999)
`U.S. Patent No. 6,068,784
`
`U.S. Patent No. 6,251,792
`
`U.S. Patent No. 4,836,905
`
`U.S. Patent No. 6,538,720
`
`U.S. Patent No. 4,952,858
`
`International Publication No. WO
`00/058994
`U.S. Patent No. 6,961,113
`
`U.S. Patent No. 6,133,982
`
`A5
`
`A6
`A7
`
`A8
`
`A9
`
`A10
`
`A11
`
`A11
`
`A12
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`A13
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`A14
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`
`
`
`
`
`Filing /
`Priority
`Date
`
`Date of Issue
`or
`Publication
`
`Short
`Cite
`
`July 9, 2002 Hurwitt
`
`July 11, 2000 Pinarbasi
`April 4, 2002 Tanaka
`’179
`July 10, 2001 Dordi
`
`Loopstra
`
`January 19,
`2000
`May 28, 1998 Hawkins
`
`July 24,
`1995
`June 5, 1998
`October 4,
`2001
`April 8,
`1999
`July 15,
`1999
`November 7,
`1997
`November
`June 29,
`26, 2002
`1999
`November
`June 29,
`21, 2000
`1999
`July 7, 2000 March 1,
`2005
`February 4,
`1999
`March 16,
`2004
`Spring 1999
`
`Su
`
`Su ’664
`
`Tanabe
`
`Li
`
`Aoki
`
`Butler
`
`July 23,
`1997
`February 12,
`1999
`N/A
`
`October 3,
`1989
`July 31,
`1990
`July 16,
`1987
`February 28,
`2001
`May 18,
`1988
`March 1999,
`31
`May 28,
`1999
`November
`15, 1996
`
`May 30, 2000 Collins
`’784
`June 26, 2001 Collins
`’792
`June 6, 1989 Davis
`
`March 25,
`2003
`August 28,
`1990
`October 5,
`2000
`November 1,
`2005
`October 17,
`2000
`
`Galburt
`
`Galburt
`’858
`Hao
`
`Hayashi
`
`Inoue
`
`-13-
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`
`
`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
`
`
`
`
`
`Exhibit
`
`Reference
`
`European Patent Appl. No.
`EP 1 030 351
`U.S. Patent No. 5,474,647
`
`International Publication No. WO
`99/034257
`U.S. Patent No. 5,877,843
`
`U.S. Patent No. 5,926,690
`
`Zwart et al., “Performance of a Step
`and Scan System for DUV
`Lithography,” Proc. SPIE, Optical
`Microlithography (Mar. 1997)
`Japanese Patent Application
`Publication No. JP H 10-177942
`Japanese Patent Application
`Publication No. JP H 6-204107
`Japanese Patent Application
`Publication No. JP H 10-125586
`Japanese Patent Application
`Publication No. JP H 6-145974
`U.S. Patent No. 6,614,050
`
`U.S. Patent No. 6,512,571
`
`Japanese Unexamined Patent
`Application Publication No. 2001-
`143984
`U.S. Patent No. 5,701,041
`
`Japanese Patent Application
`Publication No. JP H 07-111238
`European Patent Application No. EP
`1 037 117
`
`
`
`
`
`
`
`
`
`
`
`
`Filing /
`Priority
`Date
`November
`12, 1997
`November
`15, 1993
`December
`29, 1997
`September
`12, 1995
`May 28,
`1997
`N/A
`
`October 16,
`1996
`December
`25, 1992
`October 16,
`1996
`October 29,
`1992
`October 25,
`2000
`April 28,
`1999
`November
`16, 1999
`
`Date of Issue
`or
`Publication
`August 23,
`2000
`December 12,
`1995
`July 8, 1999
`
`Short
`Cite
`
`Magome
`
`Poultney
`
`Sperling
`
`Takagi
`
`March 2,
`1999
`July 20, 1999 Toprac
`
`March 1997
`
`Zwart
`
`June 30, 1998 Kida
`
`July 22, 1994 Nose
`
`May 15, 1998 Hoshino
`’586
`May 27, 1994 Hoshino
`’974
`Yamada
`
`September 2,
`2003
`January 28,
`2003
`May 25, 2001 Sai
`
`Hara
`
`October 3,
`1994
`October 12,
`1993
`February 24,
`2000
`
`December 23,
`1997
`April 25,
`1995
`September
`20, 2000
`
`Akutsu
`
`Akutsu
`’238
`Jasper
`
`-14-
`
`
`
`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
`
`
`
`
`
`b. Prior Art Systems/Services To The Asserted Claims of
`the ’651 Patent
`
`Exhibit
`
`System/Service
`
`Relevant
`Dates
`
`A3
`
`N/A
`
`ASML TWINSCAN™ System At least as
`early as
`November
`8, 2000
`1995
`
`Applied Materials Centura
`System
`
`2. Obviousness Combinations
`
`Persons/Entities
`Involved in
`Prior Use, Sale,
`or Offers for
`Sale
`ASML
`TSMC
`
`Applied
`Materials
`
`Short Cite
`
`TWINSCA
`N
`
`Centura
`
`To the extent that any one of the anticipation references is found not to disclose a limitation
`
`recited in the asserted claims from the ’651 patent, it would have been obvious to one of ordinary
`
`skill in the art at the time of the alleged invention of the ’651 patent either (i) to modify the
`
`reference to include this limitation and any remaining limitations of this claim and any claim(s)
`
`from which this claim depends and/or (ii) to combine said reference with any other of the
`
`references in Exhibits A1 to A14 and/or with a person having ordinary skill in the art’s
`
`(“POSITA’s”) general knowledge. Generally, motivation to combine any of these references with
`
`others exists within the references themselves, as well as within the knowledge of those of ordinary
`
`skill in the art at the relevant time. A person having ordinary skill in the art would have been
`
`motivated to combine any of the references described in attached Exhibits A1 to A14, including
`
`for the reasons described below. A person having ordinary skill in the art at the time of filing of
`
`the asserted ’651 patent would have understood the references listed above, alone or in
`
`combination, to contain explicit and/or implicit teaching, suggestion, and/or rationales to combine
`
`them for at least the following exemplary reasons.
`
`
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`
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`-15-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
`
`
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`
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`Defendants contend that it would have been obvious to modify the above-listed prior art to
`
`include any allegedly missing element, in view of the knowledge of one of ordinary skill in the art,
`
`the admitted prior art of the ’651 patent, and/or in combination with any of the other prior art
`
`references identified for the ’651 patent. By way of example, and without limitation, Defendants
`
`provide the following exemplary combinations for particular claim limitations based on teachings
`
`of the cited prior art references. Defendants reserve the right to rely upon any combination of prior
`
`art references whether listed herein or otherwise.
`
`A person of ordinary skill in the art having knowledge of the above-listed patents, articles,
`
`and systems, among other things, would be motivated, taught, and suggested to combine the prior
`
`art discussed in Exhibits A1 to A14 with one another, in any number of ways, including as detailed
`
`below.
`
`As a threshold matter, the Asserted Claims of the ’651 patent simply arrange old elements
`
`known in the field of semiconductor fabrication technology, with each performing the same
`
`function it had been known to perform, and yield no more than what one would expect from such
`
`an arrangement. Such combinations of the prior art are obvious, as further detailed below.
`
`The ’651 patent uses entirely (and admittedly) conventional processing-tool components
`
`(e.g., a wafer stage, actuators such as pneumatic cylinders, and a process chamber). As the ’651
`
`patent explains, the alleged novelty is simply to make adjustable the wafer stage surface of an
`
`otherwise conventional processing tool. And, even when it adds adjustability to the wafer stage,
`
`the patent relies on admittedly conventional actuators. Indeed, the patent does not purport to have
`
`invented any new actuator or processing tool component.
`
`Of note, the ’651 patent itself admits that a number of the claimed elements were commonly
`
`known, and conventional, prior to the date of the alleged invention. See also, e.g., Exhibits A1–
`
`
`
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`
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`-16-
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`IPR2021-01348
`Ocean Semiconductor Exhibit 2025
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`
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`A14 (evidencing that the components were common and conventional). For example, the ’651
`
`patent discloses that:
`
`
`
`
`
`
`
`
`
`
`
`“In general, semiconductor manufacturing operations involve, among other things,
`the formation of layers of various materials, e.g., polysilicon, insulating materials,
`metals, etc., and the selective removal of portions of those layers by performing
`known photolithographic and etching techniques. These processes, along with
`various ion implant and heating processes, are continued until such time as the
`integrated circuit device is complete.” ’651 patent at 1:51-58.
`
`“In manufacturing semiconductor devices, many deposition processes and etching
`processes may be performed. For example, a variety of process layers, e.g., layers
`of polysilicon, metal or insulating materials, may be formed by performing a variety
`of deposition processes, e.g., chemical vapor deposition (‘CVD’), plasma enhanced
`chemical vapor deposition (‘PECVD’), physical vapor deposition (‘PVD’), etc.
`Additionally, a variety of etching processes, such as a dry plasma etching process,
`may be performed to pattern an underlying process layer.” Id. at 2:25-34.
`
`“As stated previously, in manufacturing integrated circuit devices, many deposition
`and etching processes, e.g., CVD, PECVD and PVD deposition processes, chemical
`etching processes, sputter etching processes, reactive ion etching processes, etc.,
`may be performed. The processing tools for performing such processes, i.e.,
`deposition tools and etch tools, may have various physical configurations that
`depend upon a variety of factors, e.g., the manufacturer, the type of process to be
`performed, etc. U.S. Pat. Nos. 6,068,784 and 6,251,792 B1 depict illustrative
`processing tools that may be used in modern semiconductor manufacturing. Both
`of these patents are hereby incorporated by reference in their entirety. However,
`many, if not all, of such tools have a process chamber, where processing operations
`will be performed, and a wafer stage or chuck in the process chamber that is adapted
`to hold a wafer in position during processing, typically through use of vacuum
`pressure or one or more clamps.” Id. at 5:3-20.
`
`“A mechanism