PERGAMON Microelectronics Reliability 39 (1999) 731-739 Tutorial paper MICROELECTRONICS RELIABILITY www.elsevier.com/locate/microrel New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability? Chris J. McDonald Intel Corporation, FM2-78, Folsom CA, USA Chris.mcdonald@jntel.com Abstract This paper will start with a discussion of why probe yield (the number of good chips per silicon wafer) is so important to f'mancial success in integrated circuit manufacturing. Actual data will be quoted and a numerical example shown. A simple model will be given to demonstrate the main factors influencing yield and the relationship between yield and reliability of the final product. In the last few years a range of new tools have been deployed in manufacturing, and these have accelerated the pace of yield improvement, thus increasing competitive pressures. These tools will be described, along with examples of their use. Topics will include in-line inspection and control, automatic defect classification and data mining techniques. A proposal is made to extend these tools to the improvement of reliability of products already in manufacturing by maintaining absolute chip identity throughout the entire wafer fabrication, packaging and f'mal testing steps. © 1999 Elsevier Science Ltd. All rights reserved. 1. The importance, of probe yields in f'mancial success Probe yield is obviously a very important and direct factor, and a few calculations show just how important. Fig. 1 shows a graph of capital equipment required by a company to manufacture ten million integrated circuits per year, as a function of die size and defect density. (Yield is inversely dependent on defect density.) Since the industry is generally in a growth mode, this is usually a very important question. For a die size of 200 mm 2 on a side, the difference between 50 and 150 defects per wafer comes out to $400M. The company with the highest 3000 ............................ 2500 t .............................. / 2000 ................................................. | 1.ol ............................................ _/ ..... 0 200 250 300 350 400 450 500 550 600 650 700 Dle Slze, mll .... 0 Def/Waf ~ . . 50 Def/Waf 150 Def/VVaf ] Figure 1. Capital needed for 10M units/year yield will be able to plow this extra profit back into R&D and capacity expansion. Data from Leachman [ 1 ] can be used to calculate typical yields for various product types and technology generation. For example, in 1993, two different companies manufacturing 4M DRAM ran defect densities of 1.0 and 0.30 defects per cm 2, corresponding to yields of 49% and 80% respectively, which gave vastly different levels of profitability. Success in DRAM today requires yield in the mid- nineties. Stock market analysts understand these economics very well, and generally have fairly good yield estimates especially when a few product types dominate a company's business. An example [2] from 1995 will illustrate: "We estimate that Intel's 0.6 micron line width fabs are now yielding 65% probe yield out of 154 potential die. As these yields improve over the months ahead, we believe that there is room for upside surprise to the gross margin estimate that.we are projecting for Q3." In the last few years, stock prices have become more volatile, and good or bad news in yields can cause big swings in the market. 2. Yield models A yield model, for example [3,4] is an equation, or increasingly a computer program, used to predict 0026-2714/99/$ - see front matter. © 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(99)00094- 3
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`732 C.J. McDonald/Microelectronics Reliability 39 (1999) 731-739 the die yield in terms of defect density, die area and other parameters. The purposes of a yield model are to: (a) Predict the yield and therefore manufacturing cost during the design phase. (b) Compare actual yield vs. the model, allowing product-specific problems to be identified and corrected. (c) Determine the optimal level of integration, i.e., the number of transistors per chip. (d) Set priorities for process improvement work. (e) Allow extrapolations to future technologies with smaller line widths. Designers usually want to fit the maximum number of electronic functions onto the chip, however, this will increase the die size and cost, so obviously a trade-off has to be made. Generally a new product will have a target market segment, which in turn will have a target price customers are willing to pay for the final product. It is convenient to divide the yield loss mechanisms into three broad categories: (a) Ys is defined as the structural limited yield from dice that fail as a result of internal shorts or opens, due to systematic non-random failure mechanisms, which affect entire wafers or regions on the wafers. (b) YE is defined as the electrical parameter limited yield, from dice that fail for out-of-tolerance electrical parameters such as threshold voltage or sheet resistance. Generally there are two categories. "Hard failures," where the circuit fails to function under any conditions because one or more internal logic levels are incorrect, and "soft failures," where the circuit does function, but fails to meet a specified product parameter, such as standby power or maximum clock frequency. (c) Yo is defined as the defect limited yield, from die which fail due to spot defects, such as those caused by particles. Sometimes these are erroneously referred to as "random" defects, although the types of particles found in semiconductor processing are seldom random, but clustered. These definitions are somewhat arbitrary, since some failure mechanisms could fall under more than one category. For example, plasma etching processes can leave "residue," a dense pattern of very small point defects. In these definitions, this would be considered a structural yield loss mechanism. Structural problems generally come from limitations in the basic process technology from either poor capability, poor control or faults in the way the process steps are integrated together. This is the realm of the technologist or process integration engineer. Electrical limited yield is generally the province of the design engineer, but there are two ways to look at the problem. From the designer's standpoint, the process U.I E o .u lzo ,- L I I I ! 4~ 2~ *'°,./v~" V" -v ¥ V ;'VIrgil v Id V W q~o 4.0 | • __ "° [ "° li -lO.O [ olZ0 SQRT (Die area) mils Fig. 2. Error between the actual available die and the equation parameter distributions are fixed, and it's the designer's job to make sure the circuit functions over the full range. From the process engineer's view, the circuit is fixed but process controls need to be improved to ensure the product always has maximum yield. Defects are generally the realm of the manufacturing department and the manufacturing and process engineers that support them. Mallory et. al. [5] has some good examples of these distinctions. 3. Simple yield model One simple yield model for the number of good dice per wafer is given by, and Y : r = I1 , p - 0"725"f8-Aqex ( Ad E) 4A / / Where N is the number of dice available per wafer. D is the diameter of the wafer. E is the width of an exclusion ring at the edge of the wafer where the yield is zero. A is the area of the die and ds is an effective defect density. This calculation of the number of available die is approximate, but has been found to agree within one or two percent with the actual number counted on a range of products. See Fig. 2. This model is based on the Poisson distribution, which is usually only a good approximation over a small range of die sizes. However, it does serve to demonstrate the strong dependence of the yield on die area and defect density. In this case dE is not an actual defect density as you might estimate by inspection and counting, but rather an effective, "curve-fit" value that would give the predicted yield if the defects were actually random in nature. Other workers have refined the Poisson model using various distribution functions
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`C.J. McDonald / Microelectronics Reliability 39 (1999) 731-739 733 \ Fig. 3. The Effect of Particle Size on Yield at Different Line/Space Widths 0.000 "0 0.700 0.000 o.seo 0.400 0.40 mc t .... [ I b ¢ i 0.50 o.6o o.7o 0.80 0.90 .I,oo Model Yield Fig. 5. Yields: actual vs. model Fig. 4. The Effect of Pattern Defect Size on Yield at Different line/space widths for the defect density, rather than a single value. For example, Stapper [4], Murphy [6] and Seeds [7]. In semiconductor manufacturing, wafers are inspected at various sample points during the process and the number of defects is counted. This actual defect density will be related to dn as follows, d e =~d Where d is the actual defect density and 0 is the probability that a given defect will result in an actual circuit fault. The value of 0 will depend on the defect size, composition (conducting or non-conducting) and permanence (is it cleaned off during processing before it can result in an electrical fault). The probability of failure is illustrated in Figs. 3 and 4. Different types of circuitry tend to have different effective defect densities. For example, in DRAM the transistor elements form a tightly packed array with minimum feature sizes with minimum spacing. In contrast, a logic circuit will contain a greater amount of open space due to inefficiencies in close packing the "random logic." ROM and gate array devices might contain unused circuits and some defects become "non-killer" since they might cause a circuit node to become "stuck" at the logic level for which it has already been programmed. This becomes a problem for complex microprocessors and other devices that contain more than one type of circuit. Stapper [9] proposes one way to deal with this. Alternatively, the termAde can be modified as follows Ad e ---> A(mld t +m2d~ +m3d 3 + ..... ) Where the terms m and d represent the fractions of the chip area used by each circuit type and the corresponding effective defect density curve fit parameters. The values of m are known from the circuit design and the d values can be estimated either by regression analysis of a family of products or by comparing critical areas. (The critical area of a circuit is the area of an equivalent circuit with Oof 1.) Fig. 5 demonstrates that this relationship is a reasonable approximation in practice. 4. The relationship between yield and reliability Small defects which locally reduce the line width or spacing, contact/via size or other feature size, but which do not cause a circuit failure on initial testing, can become "latent" defects. These can cause failures during device operation in the field. A narrow spot in a metal line can result in localized heating and electro- migration or can behave like a fuse. A location where two conductors are almost but not quite bridged, can fail in time due to leakage, dielectric wear out or breakdown. Particles left within the structure can react chemically with the circuit dements, for example, by causing corrosion of a metal line. Fig. 6 from Riordan et. al. [8] illustrates this relationship. In this paper the authors demonstrated the relationship by comparing probe yield and bum-in yield at a lot level, wafer level and location (x/y coordinates) within the wafer. Bum- in yield is known to correlate well with field failures over time. Fig. 7 shows an example for wafer level
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`734 C.J. McDonald/Microelectronics Reliability 39 (1999) 731-739 IlolI.It OKN ..... yiold .... li bili ..... U ~._t..----- Sometimes a latent reliability defect .~ EL jSornetimes yield or latent ~Always a yield deject ~ Mathematical Model [] Dr ~a×Oy !111 "o, Ybi ~ Y a i ~z = = . Log (Sort Yield of Wafer) Fig 6. Model for reliability vs. yield [8] Fig 7. Reliability vs. Yield on a 1 million unit sample at the wafer level [8] data. The bum-in yield is given by Yb, = kY~ dR a 7--- dE Where Ybi is the bum-in yield, k is a constant and dR is an effective density of defects causing bum-in failures. 5. Automated in-line defect inspection The topic of "yield management" has recently started to be studied by academia, for example, by Nag et. al. [10]. They demonstrated that the rate of yield improvement and, therefore, overall profit is strongly tied to the ability of the wafer fab organization to quickly analyze yield loss mechanisms and take corrective or improvement action at the process step level. Obviously the closer the point of detection to the actual process step that is the source of a given defect, the more effective the yield management will be. In recent years, automated in-line defect detection eqmpment has been widely deployed for product wafer inspection. There are two main types. The first basically uses polarized light scattering with very complex schemes to filter the periodicity of the circuit features and process the image data. These instruments are very good at detecting defects with topology, such as particles on the wafer surface. However, they are also able to pick up pattern type defects. The second type captures the image of an area on a die and converts it to pixels with a gray scale value applied to each. The identical area on another separate die is then imaged and compared to the fwst. ff a difference is detected, then a defect is present. This type of instrument is generally more sensitive, but usually slower. These tools are used for process control purposes, to detect an increase in defect density in-line, and also for improvement purposes by allowing the generation of Pareto charts of the baseline defect levels and types. Generally the key inspection points in the process are identified and sample of die on a sample of wafers measured. A sample of the defects found is then verified and classified by type. There are many technical papers published each year at several conferences. Radin [11[ and Strathman and Lotz [12] are early examples. Once these tools became widely available they made a major contribution to yield improvement efforts. The equipment continues to improve in terms of speed and accuracy as better algorithms, electronics and optical techniques are developed. 6. Automated defect classification A similar breakthrough is about to happen with "automated defect classification" (ADC). Inspection of a partially processed product wafer will reveal multiple types of defects, some freshly generated at the process step immediately preceding the inspection, but many from previous steps. Often, subsequent processing will modify the appearance of a defect. Plotting the total defect density on an SPC control chart will be useful, but an important trend for a particular defect mechanism might be missed in the overall noise, and similarly, for correlation between process conditions and total defect density. Also estimates of "kill ratio" or "probability of failure" will be estimates of the overall average of multiple defect mechanisms. The signal-to-noise ratio can be improved by reviewing the defects detected by the automated inspection, classifying them by type and applying data analysis to each type. Unfortunately this work takes great skill, is time consuming and suffers
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`C.J. McDonald/Microelectronics Reliability 39 (1999) 731-739 735 Vkld ~ "r~w # L_':': ........... I I .... ""'°'" I ¢ I I Fig. 8.Typical Wafer Fab Database Fig. 9. Traditional Low Yield Analysis from the imprecision of human judgement In addition, the number of distinct defect type multiplies the amount of information generated. This defect review step is typically the bottleneck operation in defect management. Automated defect classification has been under development for the last few years and has now reached the stage of maturity where useful information is generated. The technology is very complex and uses such techniques as neural net processing, fuzzy logic and machine learning made possible by the availabihty of cheap high performance computing. Accuracy and repeatability are far from perfect, but results are improving and are probably now as good as the average human inspector. Pilot and full manufacturing lines are now using ADC. For example, [13,14,15,16]. ADC tools are continuing to improve as evidenced by improved accuracy and repeatability and faster algorithms. 7. Automated in-line defect inspection using SEM The next impo~nt technique on the horizon is automated defect detection using SEM. As device features continue to shrink, the problems of defect imaging become more acute. For an optical microscope, the resolution, R and depth of focus, d are 2 R = k 1 -- NA given by, [ 17] Where NA is the numerical aperture and k~ and k2 are constants. Combining these equations gives, 2- k2 Rz kl 2 d So for a given depth of focus the inspection wavelength must decrease with the desired resolution, i.e., minimum feature size or size of defect to be detected. This limit has forced the development of automated SEM-based defect detection [18], where the electron wavelength, of the order 0.042nm at 800eV, is much smaller than the defects of interest. In addition to their superior resolution, SEM-based inspection systems are also detecting additional defect types as a result of the charged particle nature of the electron beam. For example: (a) Small defects hidden in dense features such as sub-qnarter micron lines which cannot be resolved optically with thin small defects at the bottom. Co) Unopened contacts and vias with residual material in the bottom for example due to incomplete etching. (c) Defects m or on films with grain or surface roughness. SEM images of such materials appear smooth allowing higher sensitivity settings. (d) Electrical defects exhibiting voltage contrast. Electrically floating structures charge differently, allowing detection of defects such as gate electrode shorted to substrate and metal line not connected through a via. 2 d = k~ NA 2 8. Software techniques for yield improvement 8.1 Introduction This topic is very much an emerging area m the semiconductor industry. The availability of relatively
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`736 C.J. McDonald / Microelectronics Reliability 39 (1999) 731-739 Ills A pattern of varllCJon, suoh ~ a paltleuler bin or tell ¥(K~tor failing In • ~dlcular region of the wllfQrs. 1) Lotslwafers with problem 2) LOtSCwMers ~lthoUt problem Aulomlll0 oomparllonl, using ttMlltlc•l tmltm, mcro~l multiple Qomblnatlons of ml~hlne, operator etc. Invelrtlglte at ~;tmtlon Cecords, ~perlment~tlon Fig. 10. Statistical Low Yield Analysis Could be end of line tilting or In line monitoring t 100 ~ ~ 4O0 R~.er4 N ~l~r Fig. 11. Data mining example: trend chart for high ICC failures [24] inexpensive computing power and mass storage of data has made it possible to start analyzing the mass of fabrication data usually collected for process control and lot tracking purposes. It is possible to write software routines to look for patterns in the data which can lead to knowledge of yield loss mechanisms and, thereby, to yield improvements. Up until now it was mainly the large companies who did this type of work, using in-house resources. In the past few years, however, a number of start-up companies are appearing, offering suitable software packages. Also, suppliers of metrology equr'pment are seeing the value of these techniques and using the gap to expand their business and promote sales of their hardware by offering a total solution to yield management. 8. 2 Data mining concepts Data mining [19,20,21,22] is an emerging field, which has long been applied in such industries as retailing and credit cards. Airlines and hotels have sophisticated systems to manage their revenue and yields by constantly adjusting the number of seats or rooms allocated to different fares or rates [23]. Data mining can be defined as the "non-trivial process of identifying valid, novel, potentially useful and ultimately understandable pallerns in data." The most powerful concept is that the users don't necessarily need to know what they are looking for but can obtain insight that can save money or spawn ideas to grow a business. Some examples of the typos of information, which can be obtained by data mining are: (a) Associations: Occurrences that are linked together in a single event. This is how grocery stores decide which items to place near to the checkout line where "spur of the moment" purchases are made. (b) Sequences: Events that are linked together over time. For example, people who purchase a new home are more likely to buy new appliances or furniture. This is similar to the situation where defects might increase following an equipment preventive maintenance event. (c) Classification, or the recognition of patterns that describe the group to which an item belongs. For example, to discover the characteristics of customers who are likely to "leave" so they can be targeted with promotions. In our case, it is equipment that is more likely to fail, so it can be inspected. (d) Clustering or the discovery of groupings within the data. (e) Forecasting or the estimation of future indicators, i.e., sales or, in our case, yields based on patterns within the data. A typical wafer fab database, Figure 8, will contain large amounts of data such as from in-line measurements and inspection and various process and equipment records as well as the results from wafer probe testing. This is an ideal data "mine." 8.3 Low yield analysis by data mining One new application for data mining is in "low yield analysis", the investigation of samples of low yield wafers to determine priorities for improvement. The lraditional approach, shown in Figure 9, has been to identify a sample of failing dice for detailed electrical and physical failure analysis. This type of failure analysis still has a place in the tool kit. There are times when the precise failure mechanism of a specific die needs to be known, for example, (a) to study a customer return or reliability stress failure; (b) if the sample is characteristic of a larger population of failing die, such as from a systematic, non-random problem, or (c) as a one-time "calibration" to see what failure modes are present. As the complexity of the products and processes continues to evolve, physical failure analysis has become very complex and specialized. For process control or ongoing yield management however, physical failure analysis is no longer practical. The procedure is slow since the etching back of multiple layers is very painstaking and slow. It's labor intensive and difficult to automate, making it very difficult to obtain valid sample sizes. It's not precise. For example, a metal layer today is
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`C.J. McDonald/Microelectronics Reliability 39 (1999) 731-739 737 hi| v, ton - ' , ,L~.JP-" , : 16 | : .,.~ ~. I,. , qb e i . [ I f • °'°°°°° ' • * • ° .'. • • [ °°°-°- " • o°°° k i':; ° ". ..... I' ° ° °. * . °°.." °° ° • • • °... ° ° • • ° • ° °° ° ° ° • .~ ° Fig. 12. Data Mining Example: Correlation between ICC Failures and rcn parameter [24] Fig. 13. Wafer sequence analysis [25] made up of multiple films making it more difficult to determine which one is the source of a defect. Many particles are cleaned, etched or polished off after the circuit fault has been created, for example a particle which blocks an ion implant. "Statistical low yield analysis" as shown in Figure 10, has complemented the traditional approach. A group of lots will be identified as low yielding and a series of searches made comparing all process records for this group against a list of normal yield lots. Statistical tests must be used or too many false alarms will be generated. Likely candidate stations are then investigated further to determine if there is a cause and effect relationship. The next logic step people have taken is to nm these routines automatically, in the absence of any specific yield problem just in order to improve process control. Finally the same routines are run using in- line defect data as the output imraineters, preferably against individual defect types identified by ADC. In this way very tight process control is achieved and yields maximized. 8. 4 Example Weider [24] gives an example of data analysis by data mining. A trend diagram, Figure 11, shows a wide distribution of a particular failure bin, indicating high ICC current. This data was submitted to a software routine that automatically searched for patterns and produced a correlation (Figure 12), to the particular electrical process parameter responsible for the low yield. This example is significant because no knowledge of the relationship existed before the analysis was conducted. 8.5 Analysis of yield by wafer sequence Frequently there is a relationship between process parameters or defect levels and wafer sequence. This can occur in a batch reactor where there is some kind of gradient within the chamber or a localized source of particles. In addition many processes exhibit a "t6ol wear" phenomenon where conditions change over time, for example, due to build up of reaction byproducts. These effects can be detected by randomizing the wafers within a lot prior to each process step, then plotting the parameters of interest versus wafer order for each step. Scher [25, 26], gives several examples. Figure 13 illustrates the concept. It's very easy to pick out the process step responsible for the variation, in this case, even without a formal statistical analysis. 8. 6 Spatial signal analysis ORen the spatial pattern of defects on a wafer will give valuable insight into the root cause. For example, a radial pattern, with defects in the pattern of"spokes" will point to a spin type process, such as resist coating or spin-on dielectric. Scratches also have very characteristic patterns. If these patterns can be separated automatically by soRware, the information can be linked into the data mining tools and give an early warning as soon as one of these patterns is detected. Tobin et. al. [27,28] describe how this is done and an example is shown in Figure 14. 9. The use of these new tools to improve product refiability (a) The techniques described above have been used to bring about an accelerating pace of yield improvement during the manufacturing phase in the most successful companies, which are now on the verge of further breakthroughs. The question is, can There are a number of metrics often used to monitor
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`738 C.J. McDonald / Microelectronics Reliability 39 (1999) 731-739 .......... ...-.... / "\ / • " '7" 7 " 7 '~ Example of wafer map segmentation: (a) Original wafer map. (b) Random, non-clustered particles. (c) Characteristic morphology used to associate the signature with a SOG coat track. (d) Other clustered particles. applied to improving final test and bum-in yields as well. Acknowledgements This tutorial paper is part of a one-day class on Integrated Circuit Yields, from a series "Yield and Reliability in VLSI Development and Manufacturing." For more detail see http://www.cei.se Fig. 14. Spatial Signal Analysis [27] these be applied to improvements in reliability also. product quality and reliability during manufacturing. (b) Final test yield of packaged devices. Some failures at this stage are due to packaging issues, but some falhtres might be as a result of stresses during packaging and testing causing latent defects to fail in distributions at final test. In addition to the raw yield, the failure rates of each bin or test can be used to give further insight into failures due to latent defects. (c) Bum-in yield. Some test flows will include a 100% bum-in on bum-in boards in bake ovens. Studying the fall out from the post-test will give further insight. Application of the new yield improvement tools to final test and bum-in yield requires the ability to trace each unit back to the original fab lot number, wafer number and x-y location on the wafer. The only practical way to do this, is to store the information in the die itself. If the product is a non-volatile memory or contains some non-volatile memory elements for program and/or data storage, for example FLASH or ROM, this is quite easy. A few extra memory cells are added, along with a way to access them, such as an extra address pin for decoding or an extra logic level for an existing pin. For EPROM devices, an ordinary EPROM cell is simply covered with the metal pattern to prevent erasure. For a logic product or volatile type memory, a fuse can be used. For example, see Riordan [8]. The memory element does not need to have a high performance, such as fast programming and read time since it will only be read a few times. 10. Conclusions The pace of yield improvement is accelerating as a result of new tools, such as in-line defect inspection and classification, and a range of software analysis techniques including data mining. By maintaining the ability to trace each finished unit back to its original wafer fab lot number, wafer number and x-y coordinates on the wafer, these techniques can be References [1] R. C. Leachman, Editor, "The Competitive Semiconductor Manufacturing Survey: Second Report on Results of the Main Phase," University of California at Berkeley, Center for Research in Management, 1994. R.C. Leachman and D. Hodges, "Benchmarking Semiconductor Manufacturing," IEEE Trans. Semiconductor Manufacturing, Vol. 9, No. 2, May 1996, pp. 158-169. See also http://euler.berkeley.edu/ersu/csm/csmreports.htm [2] Robertson, Stephens & Co., report on Intel Corporation. April 18 ~ 1995 [3] J.A. Chmningham, "The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," in IEEE Trans. On Semiconductor Manufacturing, VoL 3, No. 2, pp. 60-71. [4] C.H. Stapper, R.M. Armstrong, and K. Saji, "Integrated Circuit Yield Statistics," in Proc. IEEE 71(4), April 1983, pp. 453-470. [5] C. Mallory, D. Perloff, T. Hasan and 1~ Stanley, "Special Yield Analysis in Integrated Circuit Manufacturing," Solid State Technology, November 1983. [6] B.T. Murphy, "Cost Size Optima of Monolithic Integrated Circuits," in Proc. of lEEE, Vo152, No. 12, December 1964, pp. 1537-1545. [7] R_ B. Seeds, "Yield and Cost Analysis of Bipolar LSI," presented at IEEE International Electron Devices Meeting, Washington, October 1%7. [8] W.C. Riordan, 1L Miller, J. /V[ Sherman and J. Hicks, "Microprocessor Reliability Performance as a Function of Die Location for a 0.25~n, Five- Layer Metal CMOS Logic Process," presented at the International Reliability Physics Symposium, 1999 [9] C. H. Stapper and R.J. Rosner, "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation," 1EEE Trans. Semiconductor Manufacturing, Vol. 8, No. 2, May 1995.
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`C.J. McDonald/Microelectronics Reliability 39 (1999) 731-739 739 [10] P.K. Nag, W. Maly and H.J. Jacobs, "Simulation of Yield/Cost Learning Curves with Y4," 1EEE Trans. Semiconductor Manufacturing, Vol. 10, No. 2, May 1997, p. 256. 111] C. Radin, "A Defect Reduction Methodology for Increased Sort Yield Using Automated Inspection," SPIEProc., Vol. 921, 1988. [12] S. Strathman and S. Lotz, "Automated Inspection as Part of a Defect Reduction Program in an ASIC Manufacturing Environment," SPIE Proc., Vol. 1261. 1990. [131 L. Breaux and D. Kolar, "Automatic Defect Classification for Effective Yield Management," Solid State Technology, December 1996. [14] A. Shapiro, "Automatic Classification of Wafer Defects: Status and Industry Needs," IEE/CPMT Int 7. Electronics Manufacturing Technology Symposium, 1996. [15] B. Singh and S. Riley, "Automatic Defect Classification for Yield Management Strategies." Semiconductor International, March 1997. [16] J. Li, M. McIntyre, K. Lee and B. Worster, "Production Use of an Integrated Automatic Defect Classification (ADC) System Operating in a Laser Confocal/White Light Imaging Defect Review Station," IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 1996. [17] J. Bickley and A. Ohwada, "KLA 2710 Review Paper," KLA Instruments Corporation, February 19