I
`
`I
`
`,h”l
`
`8
`
`i t
`
`W
`
`Introduction
`emiconductor manufacturing is a complex aqd highly inte-
`1 Several chemical-based processes are involved in buding
`grated industry involving several intermedi te processes.
`The semiconductor market is currently driven toward low VLSI chips. While their precise descriptions and sequences vary,
`cost VLSI chips with higher circuit density. For e ample, in the depending on the desired device characteristics and the material
`year 2001, dynamic random-access memory (DRA ), which has
`sed in fabrication, the typical VLSI fabrication steps include
`historically employed a cutting-edge technology a ong various
`eta1 preparation, oxidation, photolithography, etch, diffusion,
`nd deposition processes, as shown in Fig. 1. Most devices re-
`semiconductor products, is expected to reach a 1 ensity of 1.7
`Gbits per chip at a cost of only 0.03 cents
`quire multiple steps through the same
`process at different stages. Critical pro-
`per Kbit, whereas the microprocessor is
`cesses directly influencing the critical
`predicted to have a density of 10 million
`dimension (CD) and geometry of VLSI
`logic transistors per squared-centimeter
`at a cost of 1 cent per 1000 transistors. By
`chips are photolithography, etch, chemi-
`cal vapor deposition (CVD), and chemi-
`comparison, the corresponding numbers
`for 1997 were 267 Mbits per chip at the
`cal mechanical polishing (CMP)
`cost of 0.12 cents per Kbit for DRAM,
`process, which are briefly summa-
`rized as follows:
`and 3.7 million logic transistors per
`squared-centimeter at the cost of 3 cents
`Photolithography serves to
`per 1000 transistors for microprocessor.
`transfer the pattern of the de-
`The U.S. semiconductor commu-
`sired circuit (“mask”) onto a
`nity faces increasingly difficult chal-
`wafer for the purpose of selec-
`lenges as it moves into production at
`tive etching; the process in-
`feature sizes approaching 100nm. The
`cludes photoresist coating, the
`grand challenges facing the research
`transfer of mask onto the wafer
`and development community are iden-
`(“direct wafer stepping”), and
`tified as the ability to continue afford-
`the UV light exposure step. The
`wafer is coated with photoresist material that softens
`when exposed to the UV light so that the wafer surface un-
`derneath it can be removed by an etching process. The
`mask is then applied to the photoresist surface to cover se-
`lected area from UV light exposure, which, in turn, deter-
`mines the desired circuit pattern. Photolithography is the
`key technology driver for the semiconductor industry, re-
`sponsible for the recent industry’s sapid growth, and a sig-
`nificant economic factor representing over 35% of the
`chip manufacturing cost [ll.
`
`packaging. To meet these challenges, an
`in the advancement of VLSI
`
`. ,ylching is a process for removing undesired
`
`from
`the wafer. Performed immediately after photolithography,
`etching provides selective wafer surface removal from the
`area not covered by photoresist material. Etching tech-
`niques typically used in VLSI fabrications are plasma and
`Reactive Ion Etching (RIE). The main difference between
`
`gies in advancing VLSI fabrication.
`
`46
`
`1
`1
`The authors are all with the Department of Electric41 Engineering, SdERC, Arizona State University, Tempe, Arizona. Limanond’s and Si’s
`supported in part by SEMY Engineering Inc. under F grant No. SEI-9
`research is supported in part by NSF under grant E S-9553202, by E RI under grant RP8015-03, and by Motorola; Tsakalis’s research is
`P
`0515-002.
`
`0272- 1708/98/$1 .0001998IEE E
`
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`Authorized licensed use limited to: Christopher Gallo. Downloaded on June 24,2021 at 15:37:36 UTC from IEEE Xplore. Restrictions apply.
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`Applied Materials, Inc. Ex. 1019
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`Page 1 of 13
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`

`

`the two techniques is that plasma etching relies on a chemi-
`cal reaction of the feed gas to remove unwanted material,
`while RIE uses both the chemical reaction of the feed gas
`and a physical reaction due to ion bombardment to remove
`material and operate at a lower pressure. Etching is an im-
`portant process for providing reliable device isolation and
`interconnections within the VLSI chip.
`Chemical Vapor Deposition (CVD) is a process used to de-
`posit a thin layer of material on the wafer. The reactant
`gases are introduced into the chamber and undergo chemi-
`cal reactions with the heated wafer surface to form a thin
`film. Different CVD processes are currently used for VLSI
`fabrication, including Atmospheric Pressure CVD
`(APCVD), Low Pressure CVD (LPCVD), and Plasma En-
`hanced CVD (PECVD). The APCVD operates at a moder-
`ate wafer temperature that allows for fast deposition, but
`suffers from poor coverage and particle contamination.
`LPCVD, on the other hand, offers excellent purity and good
`coverage, at the expense of reduced material strength due to
`high operating temperatures. Finally, PECVD operates at
`the lowest wafer temperature by incorporating the RF-
`induced energy in the plasma, which allows for the fastest
`deposition rate. However, similar to APCVD, it suffers
`from contamination problems. CVD is another crucial
`technology for semiconductor industry for providing
`conformal-coating solutions for higher minimum feature
`density of the chip.
`Chemical-Mechanical Polishing (CMP) is a process of re-
`moving ‘high’ material on the wafer surface (or planar-
`ization) through mechanical and chemical reaction. This
`involves the use of a polishing pad and a slurry of abrasive
`material. CMP is typically used for dielectric and metal
`planarization so as to enable satisfactory imaging of poly-
`silicon and metal layers.
`Due to their significance for VLSI manufacturing, these pro-
`cesses have been under extensive investigation from different re-
`search viewpoints, including process monitoring and control.
`
`Monitoring and Control for VLSI Fabrication
`The recent surge of interest in the area of monitoring and con-
`trol of semiconductor manufacturing process arises from the
`need to fabricate VLSI chips with higher feature densities and
`larger chip sizes. Until recently, however, monitoring and control
`of the various processes was fairly rudimentary relative to the
`state-of-the-art. It primarily relied on practical engineering experi-
`ence and basic statistical process control (SPC) methods. Real-
`time feedback control was confined to simple single-loop con-
`trollers (e.g., PID). The lack of development of more sophisti-
`cated, high-performance control systems was due to the
`following:
`A . Poor Process Undei-standing: VLSI fabrication processes
`are primarily based on chemical and physical reactions of small
`particles, which are generally complex and nonlinear. The ana-
`lytical (first-principle) models currently available are often too
`complex and computationally intensive to be used for designing
`control systems. For example, in a CF4/0,/H, plasma system,
`there are 60 possible reactions that can occur [8]. Moreover,
`VLSI fabrication processes consist of several processing steps,
`such as PECVD (plasma generation and deposition step), etch-
`
`ing (plasma generation and etching step), and photolithography
`(photoresist coating, photomask transfer, and develop steps).
`The internal interaction of various process variables leads to
`poor process understanding, hampering the application of sys-
`tematic control design methods.
`B. Lack of Appropriate Sensors and Measurement Tech-
`niques; During Integrated Circuit (IC) fabrication, wafers are
`processed inside a closed chamber on a cassette-to-cassette basis
`(e.g., one cassette may contain 24 product wafers; CVD/Diffu-
`sion furnaces can process four cassettes at a time). Furthermore,
`critical wafer parameters (or process metrics) such as the film
`thickness remaining after etching or line-width of the photo-
`mask, can only be determined using contact (as opposed to non-
`contact) measurements that can destroy the wafer surface and the
`associated electrical characteristics. For this reason, real-time
`control is often limited to variables (such as temperature, RF
`power, pressure, etc.) that affect the critical wafer parameters in-
`directly, but are easily measured.
`These two factors led to a situation where monitoring and
`control of critical wafer parameters was performed outside the
`processing chamber in a non real-time fashion after a cassette of
`wafers had been processed; see Fig. 2 for a block diagram associ-
`ated with this control strategy. More precisely, after the process-
`ing of a cassette, the critical wafer parameters are measured and
`used to update parameters of a (typically static) model, which re-
`lates a set of input variables (or recipes) to the critical wafer pa-
`rameters. The updated model is then used to generate a suitable
`recipe correction, corresponding to the desired wafer parame-
`ters. This control design strategy is commonly referred to as
`Run-to-Run (RtR) Control, which is discussed in more detail
`subsequently.
`These shortcomings have been actively investigated by both
`industry and research communities. Preliminary results are
`
`I INGOT Wafer
`
`I
`
`I
`
`Diffusion
`Deposition ...
`
`Masking
`
`Etching
`
`Fig. 1. Schematic of key semiconductor manufacturing processes
`relevant to system control.
`
`Process
`Dynamics
`
`I
`
`’
`
`
`
`Wafer
`Parameters
`
`’
`
`I
`
`
`
`Fig. 2 . Block diagram ojconventional Run-to-Run control.
`
`December 1998
`
`47
`
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`Applied Materials, Inc. Ex. 1019
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 2 of 13
`
`

`

`available for several VLSI fabrication processes in terms of
`modeling, control, and metrology (Le., instrumentation and
`measurement techniques). It should be mentioned that direct
`in-situ measurement of CD variables is still not practical. Never-
`theless, optical-based sensors (e.g., optical emission spectros-
`copy (OES) and laser interferometry (LIF), see [15], [26], [27]
`and references therein) have been invented to measure various
`chamber-status process variables (or in-situ variables) such as
`temperature and pressure. This, together with the development
`of appropriate models that relate in-situ variables to the process
`metrics, leads to the integrated RtR and real-time control strat-
`egy [6], [8], [26], which can be designed in two steps. First, the
`RtR control uses these models to determine in-situ process vari-
`ables corresponding to the desired critical wafer parameters.
`Second, a real-time control design is implemented to drive the
`chamber states to the set-point obtained from the RtR control.
`Notice that the latter step also requires a model relating manipu-
`lated process variables to the iiz-situ process variables. The asso-
`ciated block diagram is illustrated in Fig. 3. Table 1, on the other
`hand, lists the critical process variables, chamber state variables,
`and typical input variables for various VLSI manufacturing pro-
`cesses.
`
`Organization
`In this article, we report some representative results of emerg-
`ing modeling and control techniques for VLSI fabrication. The
`underlying processes considered include photolithography,
`etching, CVD, and CMP. We would like to use these examples to
`demonstrate what could be done by the control systems commu-
`nity to advance the current practice of semiconductor manufac-
`turing industry. In the mean time, the relevant issues of
`monitoring and control in semiconductor manufacturing are re-
`vealed to some extent through the examples.
`In the next section, we discuss various modeling techniques
`that have been studied and, possibly, implemented for different
`VLSI processes. Following that, we consider monitoring and
`
`I
`
`!
`
`I
`
`'
`
`
`
`In-Situ
`Measurments
`
`I
`
`1
`
`S
`
`~
`
`Fig 3 Block diagram of the Integrated Run-to-Run and Real-Time
`I
`control
`control issues for semiconductor manufacturing processes with
`emphasis (on process monitoring, the Run-to-Run and real-time
`control.
`In the fourth and fifth sections, we present two case studies
`based on kesearch activities currently taking place at the Center
`for Systeps Science and Engineering, Arizona State University.
`The first /concerns a novel wafer-to-wafer end-point detection
`scheme for reactive ion etching. The second is an integrated de-
`sign (from data to control) of a real-time multivariable tempera-
`ture contjoller for CVD and Diffusion furnaces, a design that has
`been use! successfully in about two hundred controller installa-
`tions woilld-wide. Inner-outer loop control structures combining
`RtR and teal-time controllers have special importance in semi-
`conduct+ manufacturing due to the difficulty in measuring criti-
`cal wafer parameters. In this way real-time control strives to
`maintainla repeatable process while run-to-run aims at adjusting
`the variable set-points so that product specifications are met. In
`particulak, a practically desirable connection of these seemingly
`disparate( controllers is that their designs are based on the follow-
`ing common objectives and requirements: 1) the ability to obtain
`models flrom data, tailored to a specific piece of equipment and
`
`Etching (Plasma and RIE)
`
`PECVD
`
`Table 1. Typical process metrics, input settings, and intermediate &cess variables for VLSI fabrication t)rocesses.
`I Process Metrics
`etch rate
`etch anisotropy
`etch uniformity
`etch selectivity
`deposition late
`film stress
`film uniformity
`film purity
`
`dc bias
`gas speciks concentration
`pressure 1
`temperatare
`I
`dc bias
`gas specigs concentration
`pressuie I
`temperature
`
`I
`
`rf power
`throttle position
`gas flow
`
`rf power
`throttle position
`gas flow
`
`Photolithography
`Spin coat and
`Bake step
`
`Exposure step
`Develop step
`CMP
`
`48
`
`photoresist thickness
`photoactive concentration (PAC)
`
`exposed PAC
`pattern line width
`removal rate
`uniformity
`
`I
`
`spinning speed
`baking
`temperature
`exposure dose
`
`spinning speed
`pressure
`force
`
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`Applied Materials, Inc. Ex. 1019
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`
`

`

`conforming to industrial needs of quick turn-around time; and 2)
`production-grade design and implementation.
`In the final section, we summarize the current state of re-
`search in the area of monitoring and control of semiconductor
`manufacturing process and discuss some of the future research
`activities in the area.
`
`Modeling of Semiconductor
`Manufacturing Processes
`In this section we present a summary of various monitoring
`and control related models that have appeared in the literature,
`including regression, linear dynamical, physical, and neural net-
`work-based models. All have found successful applications to
`CMP, CVD, and etching processes. The role of these models in
`VLSI fabrication is two-fold. First, they serve to provide esti-
`mates of various in-situ process variables, for which the associ-
`ated sensor and instrumentation technology is neither available
`nor suitable for implementation, for the purpose of process mon-
`itoring and diagnosis. Second, they serve as nominal models for
`traditional control system designs. Briefly summarized, process
`modeling from data consists of the following steps: selection of
`the model input, and possibly output; data collection; model
`structure selection; and, if necessary, model reduction. Widely
`used models that have appeared in VLSI fabrication literature are
`listed in Table 2.
`
`Static Regression Models
`Static models have found numerous applications in monitor-
`ing and control of semiconductor processes [21-[51, [36], [40],
`[41]. Although, in principle, the regression model can be polyno-
`mial of any degree, a linear model often performs satisfactorily
`and is widely accepted as a standard model for statistics-based
`monitoring and control. For monitoring, a static model is typi-
`cally implemented in combination with a conventional SPC
`chart (e.g., Shewhart and CUSUM chart) or a multivariate chart
`to generate alarms when the statistical properties of the moni-
`tored process variables deviate significantly from the set-point
`value [2], [3], [36]. Further, in the RtR control framework, the
`model can be used to determine an appropriate recipe adjustment.
`Typically, a design-of-experiments is implemented to determine
`the appropriate process variables, those that have the greatest influ-
`ence on the system outputs. For a modeling task involving large
`sets of data, principal component analysis or partial least-squares
`analysis can be employed to reduce the data correlation [3], [5],
`[7]. A linear regression model has the form:
`
`y = A x + d
`
`(1)
`
`where x and y are the input and output vectors, and A is a matrix
`containing the model parameters. Here, d is a constant term. This
`simple podel is rather attractive for several reasons. First, the
`constant term d can be used to represent the slow process drift,
`common in semiconductor manufacturing processes. The slow
`drift is primarily due to chemical residue buildup inside the pro-
`cessing chamber and/or the loading effect of various electrical
`equipment. Exponentially weighted moving average (EWMA)
`adaptation is typically employed to adjust the term d [40]-[43].
`Further, occasional shifts due to material variations and sched-
`uled maintenance operations can be captured by the variation of
`the model parameters in A (see [2] for further details). Finally,
`the simplicity of the model allows for fast control computations.
`In fact, it has been successfully used in RtR control to generate
`suitable recipe adjustments for etching 121, 131, [5], photo-
`lithography [36], and CMP [40]-[42].
`
`Linear Dynamical Models
`Linear dynamical models are most commonly used in a ge-
`neric control system design, mainly due to the fact that various
`systematic control design algorithms are readily available. In
`semiconductor manufacturing process, these models have been
`employed primarily for real-time control design @]-[I 11, [26],
`1291 but they have also found a limited application in process
`monitoring. The selection of the model inputs and outputs is
`roughly similar to the one for static regression models.
`A linear dynamical model is typically obtained by using step
`response and/or parameterization methods. In the former, the
`step response (or frequency response) plots are obtained so as to
`determine the associated gain and time constant for each single-
`input single-output channel of the process. This modeling
`method has been successfully used to determine a control-
`related model for RIE [6], [8], [9] and PECVD [26]. Another
`modeling technique relies on the parameterization of the system
`under consideration, and the minimization of a suitable error cri-
`terion for input-output data obtained during an identification ex-
`periment [44], In particular, a simple parametrization arises from
`the so-called equation error; although this parameterization and
`estimation does not always lead to good prediction models, it is
`attractive for its computational simplicity as well as the control-
`oriented properties of the associated error system. It has pro-
`vided a quick and successful mechanism for the temperature
`control problem of diffusion/CVD furnaces [29], presented in
`the second case study below.
`
`Physical Models
`Physical, or first-principle, models of VLSI manufacturing
`processes are complex and difficult to build. They are therefore
`
`December 1998
`
`49
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`Applied Materials, Inc. Ex. 1019
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`Page 4 of 13
`
`

`

`Table 3. Representative monitoring and control publications for various VLSI fabrication processes.
`Etch
`Photolithography
`
`,CVD
`
`CMP
`
`RtR Control
`Conventional Control Design
`Monitoring
`
`PI, 141, [6
`[8], [9], [Ill, [12], 1141, [24]
`PI, [SI, 1131,1151, [171, [201,
`P11, P31, [4sl, [461,1471, [481
`
`[361
`[26], [29], [32], [33], [35] [37], [38], [53]
`[331, [341
`[541
`
`[401, [411, [421
`
`[421
`
`typically used for providing simulation studies under various op-
`erating conditions and settings or for the monitoring of process
`variables, see [15], 1301, [39], [55] for examples. Nonetheless,
`with suitable assumptions and a model reduction step, simplified
`first-principle models can serve as nominal models for control
`design as well, as shown in [12] and [14]; [31]-[331: and 1371,
`[38], and [53], for, respectively, etching, CVD, and photo-
`lithography.
`
`Neural NetwoYk-Based Models
`Neural networks have recently found many applications in
`VLSI fabrication, especially for providing estimates of critical
`wafer parameters for real-time monitoring purposes. Briefly
`summarized, a neural network is an interconnected system of
`“neuron” units interacting with each other through their
`“weight” connections. These neurons are activated by the
`weighted sum of incoming signals (from other neurons) and fire
`outputs according to the associated “activation” function, which
`can be of sigmoid or Gaussian type. A special class of neural net-
`works, known as multilayer perceptron (MLP), is commonly
`used as an approximating “ode1 for nonlinear dynamical sys-
`tems, due to its good approximating property, which was rigor-
`ously established in [56]. An additional attractive feature lies in
`the fact that building an MLP model requires less training data
`than building a statistical model [ 161, [ 171.
`MLP modeling requires similar building steps as statistical
`and linear dynamical modeling. The MLP structure is chosen
`based on the number of model inputs and outputs, typically with
`one or two internal layers. In order to determine a set of connect-
`ing weights that provide the least fitting error, a gradient descent
`training algorithm, such as backpropagation, can be imple-
`mented. However, better convergence properties can be achieved
`by using the Levenberg-Marquardt algorithm or other improved
`backpropagation training methods [ 181, [ 191. For highly corre-
`lated sets of data, principal component analysis can be applied to
`reduce the correlation. In VLSI fabrications, MLP’s have been
`used for process modeling for CMP [40], CVD [34], [3S], and
`etching [161-[181, [201-[221, [241, [251.
`
`monitoripg schemes as well as control design schemes such as
`RtR and real-time control (see also Table 3).
`
`Monitoring
`Process monitoring serves to provide information concerning
`critical process variables in the form of real-time sensor readings
`or the akociated statistics. Traditionally, process monitoring
`was done in an off-line and non real-time fashion, based on mea-
`surements available after several batches of wafers had been pro-
`cessed. Though sufficient for a simple systems, this type of
`process monitoring, is rather inadequate for complex processes
`such as etching and CVD. This leads to the development of dif-
`ferent ogtical-based measurement techniques, such as OES and
`LIF for certain critical process variables (see [15], [26], [27],
`[46], [49] and references therein). In the absence of suitable sen-
`sors, twO alternatives are available. First, state estimation algo-
`rithms such as Kalman filter [54], extended Kalman filter [13],
`[37], and, recently, a jump linear filter [48], have been imple-
`mented Lo estimate intemal variables of the process from the
`availablt measurements. Second, sophisticated models can be
`built off-Lline and implemented on-line so as to provide real-time
`approxihation or prediction of the critical variables. For this pur-
`pose, neural networks are instrumental and widely used in
`model-qased monitoring of etch processes [ 5 ] , [ 151, [18], [20],
`[21].
`In acldition to real-time control, another important application
`of procdss monitoring is in the detection of process end-point. In
`that cas&, the ability to correctly specify process end-points is of
`signific?nt importance, since, for example, it can reduce produc-
`tion scrap from over or inadequate etching and increase through-
`put repfpducibility. Briefly summarized, an end-point detection
`schemeimonitors the so-called “end-point detection signals” ob-
`tained fiom optical-based sensors (i.e., OES and LIF) until they
`match d decision criteria for end-point [46], [49]. Another tech-
`nique involves the use of MLP to compute the etch time based on
`various;process measurements [45], [50], [52]. An example of
`the endrpoint detection schemes that involves the use of MLP
`andoptimization algorithm [23] is discussed in the next section.
`
`Monitoring and Control of Semiconductor
`Manufacturing Processes
`Semiconductor manufacturing processes suffer from a high
`level of system nonlinearity, internal state interaction and a lack of
`real-time measurement tools that hamper the effective application
`of the existing comprehensive diagnostic and control design pro-
`cedures. Furthermore, these processes are often corrupted by slow
`drift and other process shifts due to, for example, maintenance op-
`erations. In this respect, several control schemes have recently
`been devised to address these issues. In this section we discuss
`
`Run-To-Run Control
`Runko-Run (RtR) control is an integrated monitoring and
`control! algorithm for semiconductor manufacturing processes
`which lncorporates various modeling and (statistics-based) con-
`techniques in a systematic fashion. Traditional RtR
`trol de!ign
`controljis based on static modeling and SPC charting techniques
`(RtR control is sometimes referred to as “integrated SPC”) to
`provide monitoring and control functionality [2], [36], [41]. Re-
`cently, /neural network-based modeling and control techniques
`have ako been incorporated into the RtR control framework to
`
`50
`
`,
`
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`Applied Materials, Inc. Ex. 1019
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`Page 5 of 13
`
`

`

`provide better performance and capabilities [40], [57]. The RtR
`control has been studied in the context of etching [2], [6], 1571,
`CVD [33], photolithography [361, and CMP [40]-[42].
`RtR control typically consists of several basic modules, in-
`cluding gradual control, rapid control, and alarm module, and
`other additional features related to building and updating the
`model (see [2] for details). Here, we focus on the gradual and
`rapid control modules.
`The gradual control mode serves to provide control for pro-
`cesses that exhibit slow drift. Models that are typically used with
`the gradual control mode are linear regression models (1) [2], [3]
`and neural network models with added constant term [41], 1421.
`The control strategy is to update the constant term of the model,
`based on measurements available after each run, to track the as-
`sociated process drift and determine a suitable correction ac-
`cording to the following control laws:
`
`( Y , -4
`linear regression model: x = -__
`U
`
`neural network model: min.$ ( y, - d - f ( yp. x)),
`
`(2)
`
`where y,. denotes the set-point of controlled variables, x denotes
`the recipe variables, and d is the term signifying the process drift.
`Further, y , is used to denote the previous measurements of y .
`Rapid control mode, on the other hand, aims to compensate
`for an occasional process shift. The shift can be deterministic,
`e.g., due to scheduled equipment maintenance, or occur at ran-
`dom, e.g., due to unscheduled maintenance. The occasional shift
`is best modeled by the change in the model parameter, that is, the
`parameter a of a linear regression model or the “weight” of the
`neural network model. This, in turn, requires a parameter update
`law to be incorporated into the rapid control mode to enable the
`tracking of the occasional shift. Once the model is updated, a rec-
`ipe is determined according to (2), depending on the underlying
`model. It should be noted that in the case of random process
`shifts, a procedure to confirm that the shift did actually occur
`must he provided to avoid unnecessary model and control up-
`dates.
`Several RtR control and optimization packages are now avail-
`able, such as the MIT Run-by-Run Controller [58], the Knowl-
`edge-based Interactive R2R Control (KIRC) from the University
`of Michigan [59], ULTRAMAXTM [60], and the PCC Controller
`from Texas Instrument 1611. The available features and algo-
`rithms employed in these packages vary widely. Their perfor-
`mance is also dependent on the control problem at hand. For
`example, the MIT Run-by-Run Controller exhibits a satisfactory
`performance for systems that can be represented by an a priori
`optimized first-order regression model whereas the KIRC con-
`tains optimization algorithms and does not require the model to
`be optimized a priori.
`
`Real-Time Control
`Real-time control systems have also found applications in
`VLSI fabrication, typically integrated with an RtR control to pro-
`vide an inner-outer loop control architecture [6], [26]. It should
`be mentioned that the need for this inner-outer control loop stems
`from the lack of sensors and measurement techniques for reading
`critical wafer parameters. In this sense, the role of the real-time
`
`controller is to drive and maintain the intermediate process vari-
`ables to the set-points, updated by the RtR control after a cassette
`of wafers has been processed. These intermediate process vari-
`ables are, for example, chamber states in etching or CVD pro-
`cesses, for which appropriate sensor technology is available. A
`number of control design techniques have successfully been im-
`plemented for various VLSI fabrication processes, including
`PID [SI, [IO], [53], LQG [261, LQGLTR [$I, H _ [291, model
`predictive control 1241, model inverse control [12], [35], [38]
`and nonlinear optimal control E321, 1331, 1371.
`Case Study I:
`Neural Optimal Etch Time Controller
`for an RIE Process
`In this section we consider an end-point control problem for
`an RIE process to demonstrate how system modeling and control
`could be applied to improve some aspects of the current manu-
`facturing practice. Fig. 4 gives a schematic diagram of a poly
`etch process used in this study. The control objective is to reduce
`the effect of false determination of the end-point, or failure to sig-
`nal the end-point. These two factors are practical problems faced
`by production engineers from time to time. They directly affect
`the “health status” of the wafer, or even result in scrapped wafers.
`We discuss and provide empirical studies for our method of
`determining the process end-point for RIE processes [23]. This
`provides an alternative to the existing end-point detection
`schemes that can be categorized into two classes. In the first
`class, the so-called end-point detection signal is monitored until
`it matches suitable criteria for process end-point [46], [47]. In the
`second class, the etch time is taken as an indicative parameter for
`the process end-point and an MLP model is used to provide an es-
`timate of the optimal etch time [501-[521. Our end-point detec-
`tion scheme is also based on the use of an MLP model. However,
`instead of directly estimating the optimal etch time, the MLP
`model is used for building a functional relationship between var-
`ious process parameters, including the etch time and the end-
`point detection signal, and the film thickness remaining. For a
`desired film thickness, an optimization algorithm can subse-
`quently be employed so as to determine an optimal etch time
`based on the MLP model.
`
`Film Thickness Remaining Prediction Network
`The objective of this film thickness prediction model (Fig. 5 )
`is to build a functional relationship between the etch time, as well
`as other critical real-time in-situ measurements of the current
`
`Breakthrough Step (F Chem)
`
`Oxide of Poly
`
`Photo Resist
`
`Photo Resist
`
`I
`
`I
`Main Etch
`
`1
`
`si
`
`Over Etch
`
`Over Etch
`
`(Cl Chem)
`Fig. 4. Schematic of a poly etch process
`
`December 1998
`
`51
`
`Authorized licensed use limited to: Christopher Gallo. Downloaded on June 24,2021 at 15:37:36 UTC from IEEE Xplore. Restrictions apply.
`
`Applied Materials, Inc. Ex. 1019
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 6 of 13
`
`

`

`Fig. 5. Block diagram of the film thi