Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
`
`
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`FUTURE LINK SYSTEMS, LLC,
`Patent Owner.
`
`
`
`
`DECLARATION OF DR. DONALD ALPERT IN SUPPORT OF PETITION
`FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,622,108
`
`
`
`
`Petitioner AMD Ex-1002, 0001
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`
`TABLE OF CONTENTS
`
`
`I.
`INTRODUCTION .......................................................................................... 1
`BACKGROUND AND QUALIFICATIONS ................................................ 1
`II.
`INFORMATION CONSIDERED .................................................................. 4
`III.
`IV. RELEVANT LEGAL STANDARDS ............................................................ 5
`A.
`Claim Interpretation ............................................................................. 5
`B.
`Perspective of One of Ordinary Skill in the Art ................................... 5
`C.
`Obviousness .......................................................................................... 6
`LEVEL OF ORDINARY SKILL IN THE ART ............................................ 8
`V.
`VI. SUMMARY OF MY OPINIONS .................................................................. 9
`VII. BACKGROUND OF THE PATENT AND THE ART ............................... 10
`VIII. SPECIFIC EXPLANATION OF THE GROUNDS .................................... 17
`A. Ground 1: Claims 1–3, 8, and 11–13 are rendered obvious by
`Cuppens and Bhavsar ......................................................................... 17
`1.
`Overview of Cuppens .............................................................. 17
`2.
`Overview of Bhavsar ............................................................... 18
`3. Motivations to Combine .......................................................... 20
`4.
`Claim 1 ..................................................................................... 24
`5.
`Claim 2: “wherein the test unit comprises a Read Only
`Memory (ROM)” ..................................................................... 39
`Claim 3: “wherein the test unit comprises a read/write
`register” .................................................................................... 42
`Claim 8: “wherein the electronic circuit is provided with
`a test control node and wherein the electronic circuit is
`arranged to switch into the test mode on the basis of a
`signal value on the test control node” ...................................... 46
`Claim 11 ................................................................................... 47
`
`6.
`
`7.
`
`8.
`
`
`
`
`
`i
`
`
`
`Petitioner AMD Ex-1002, 0002
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`9.
`
`4.
`
`5.
`
`Claim 12: “wherein the test data comprises an address,
`the method further comprising the step of generating
`response data on the interconnects by the first electronic
`circuit, the response data being previously stored in the
`first electronic circuit at the address” ...................................... 50
`10. Claim 13: “wherein the test data comprises write data and
`the putting step comprises storing the write data in the
`first electronic circuit, the method further comprising the
`step of reading back the stored write data by the second
`electronic circuit” ..................................................................... 53
`Ground 2: Claims 1, 3, 6–8, 10, and 11 are anticipated by Hong ...... 55
`1.
`Overview of Hong .................................................................... 55
`2.
`Claim 1 ..................................................................................... 57
`3.
`Claim 3: “wherein the test unit comprises a read/write
`register” .................................................................................... 70
`Claim 6: “wherein the test unit comprises a combinatorial
`circuit implementing an XOR function and connected to
`the I/O nodes” .......................................................................... 72
`Claim 7: “wherein the main unit is arranged to bring the
`electronic circuit into the test mode on receipt via a
`subset of the I/O nodes of a predefined pattern or
`sequence of patterns” ............................................................... 72
`Claim 8: “wherein the electronic circuit is provided with
`a test control node and wherein the electronic circuit is
`arranged to switch into the test mode on the basis of a
`signal value on the test control node” ...................................... 74
`Claim 10: “wherein the test unit includes at least one
`combinatorial circuit implementing at least one of an
`XNOR function and an XOR function with at least two
`function inputs and a function output, the function inputs
`being connected to particular I/O nodes arranged to
`operate as input nodes of the test circuit and the function
`
`6.
`
`7.
`
`ii
`
`
`
`B.
`
`
`
`
`
`
`
`Petitioner AMD Ex-1002, 0003
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`C.
`
`output being connected to a particular I/O node arranged
`to operate as output node of the test circuit” ........................... 76
`Claim 11 ................................................................................... 78
`8.
`Ground 3: Claim 4 is rendered obvious by the combination of
`Hong and Wakerly .............................................................................. 82
`1.
`Overview of Wakerly ............................................................... 82
`2.
`Claim 4: “wherein the test unit comprises a combinatorial
`circuit implementing an XNOR function and being
`connected to the I/O nodes” ..................................................... 83
`IX. CONCLUSION ............................................................................................. 87
`
`
`
`
`
`
`
`iii
`
`
`
`Petitioner AMD Ex-1002, 0004
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`I, Dr. Donald Alpert, declare as follows:
`
`1.
`
`I.
`
`INTRODUCTION
`2.
`I have been retained by Advanced Micro Devices, Inc. (“AMD” or
`
`“Petitioner”) as an independent expert consultant in this inter partes review
`
`(“IPR”) proceeding before the United States Patent and Trademark Office
`
`(“PTO”).
`
`3.
`
`I have been asked by AMD’s counsel (“Counsel”) to consider whether
`
`certain references disclose, teach, and/or suggest the features recited in Claims 1–
`
`4, 6–8, and 10–13 of U.S. Patent No. 6,622,108 (“the ’108 Patent”) (Ex-1001) .
`
`My opinions and the bases for my opinions are set forth below.
`
`4.
`
`I am being compensated at my ordinary and customary consulting rate
`
`for my work, which is $600 per hour. My compensation is in no way contingent
`
`on the nature of my findings, the presentation of my findings in testimony, or the
`
`outcome of this or any other proceeding. I have no other financial interest in this
`
`proceeding.
`
`II. BACKGROUND AND QUALIFICATIONS
`5.
`All of my opinions stated in this Declaration are based on my own
`
`personal knowledge and professional judgment. In forming my opinions, I have
`
`relied on my knowledge and experience in designing, developing, researching, and
`
`teaching the technology referenced in this Declaration.
`
`1
`
`Petitioner AMD Ex-1002, 0005
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`I am an independent consultant with Camelback Computer
`
`6.
`
`Architecture, LLC. My residence and place of business is at 2020 21st Street,
`
`Sacramento, CA 95818. I am over 18 years of age and, if I am called upon to do
`
`so, I would be competent to testify as to the matters set forth herein. I understand
`
`that a copy of my current curriculum vitae, which details my education and
`
`professional and academic experience, is being submitted as Ex-1003. The
`
`following provides a brief overview of some of my experience that is relevant to
`
`the matters set forth in this Declaration.
`
`7.
`
`I have 45 years of academic and industrial experience in applying,
`
`designing, studying, teaching, and writing about microprocessors and computer
`
`systems. I received an Electrical Engineering Ph.D. degree in 1984 from Stanford
`
`University. I earlier received an Electrical Engineering B.S. degree from MIT in
`
`1973 and an Electrical Engineering M.S. degree from Stanford University in 1978.
`
`I have taught classes in computer architecture at Stanford, Tel Aviv, and Arizona
`
`State Universities.
`
`8.
`
`From 1976 to 1977, I worked at Burroughs Corporation, where I
`
`designed peripheral interface controllers, including those for serial data
`
`communications based on Intel 8080 microprocessor components. From 1980 to
`
`1989, I was the lead architect for the design of three high-performance
`
`microprocessors at Zilog and National Semiconductor. Later, at Intel, I was the
`
`2
`
`Petitioner AMD Ex-1002, 0006
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`lead architect of the Pentium® Processor from 1989 to 1992 and of the 815 chipset
`
`from 1999 to 2000, both of which became the most widely used PC components of
`
`their time. The 815 chipset comprised two components: (1) a memory controller
`
`hub (MCH) that included a graphics controller and memory controller with
`
`interfaces to the CPU, 133 MHz SDRAM system memory modules, an optional,
`
`external graphics controller and (2) an I/O controller hub (ICH) that included
`
`various I/O controllers (e.g., network, hard drive, USB) for system peripheral
`
`devices. Additionally, I served as co-manager for the Itanium processor design
`
`from 1993-1997.
`
`9.
`
`I am a Senior Member of the Institute of Electrical and Electronics
`
`Engineers (IEEE), and served as the chair of the IEEE Technical Committee on
`
`Microprocessors and Microcomputers from 1999 to 2000. I was the keynote
`
`speaker at the first Cool Chips conference, dedicated to the study of low-power
`
`microprocessors and systems. I have given invited lectures at several universities,
`
`and published ten papers in various professional journals and conference
`
`proceedings. My paper entitled “Architecture of the Pentium Processor,” was
`
`selected as best paper in IEEE Micro for 1993. I am a named inventor on over 30
`
`U.S. patents that pertain to microprocessors, computer systems, and related
`
`technology.
`
`10.
`
`I have reviewed the ’108 Patent, and I am familiar with the patent’s
`
`3
`
`Petitioner AMD Ex-1002, 0007
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`subject matter, which is within the scope of my education and professional
`
`experience. Based at least on my background in academia, industry, and
`
`consulting, I am familiar with the issues and technology relating to processors,
`
`chipsets, memory, peripheral devices, and testing computer systems. I have
`
`personally analyzed, developed, and tested such computer components and
`
`systems. More specifically, the Pentium® Processor for which I was the lead
`
`architect at Intel implemented various testing features, including JTAG boundary
`
`scan with an external command mode for debugging (see, e.g., U. S. Patent No.
`
`5,479,652) that allowed access to system memory through the JTAG port.
`
`Additionally, the 815 chipset MCH used an XOR tree for testing connectivity
`
`between its pins and circuit board.
`
`III.
`
`INFORMATION CONSIDERED
`11.
`In preparation for this Declaration, I have considered the materials
`
`discussed in this Declaration, including, for example, the ’108 Patent, the
`
`references cited by the ’108 Patent, the prosecution history of the ’108 Patent,
`
`various background articles and materials referenced in this Declaration, and the
`
`prior art references identified in this Declaration. In addition, my opinions are
`
`further based on my education, training, experience, and knowledge in the relevant
`
`field.
`
`4
`
`Petitioner AMD Ex-1002, 0008
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`IV. RELEVANT LEGAL STANDARDS
`12.
`I am not an attorney and offer no legal opinions. For the purposes of
`
`this Declaration, I have been informed about certain aspects of the law that are
`
`relevant to my analysis, as summarized below.
`
`A. Claim Interpretation
`13.
`I have been informed and understand that in an IPR proceeding,
`
`claims are to be interpreted according to the Phillips claim construction standard. I
`
`have been informed and understand that claim construction is a matter of law and
`
`that the final claim constructions for this proceeding will be determined by the
`
`Patent Trial and Appeal Board (“PTAB”).
`
`14. To resolve the particular grounds presented in this Petition I do not
`
`believe any term requires explicit construction.
`
`B.
`15.
`
`Perspective of One of Ordinary Skill in the Art
`I have been informed and understand that a patent is to be understood
`
`from the perspective of a hypothetical “person of ordinary skill in the art”
`
`(“POSITA”). Such an individual is considered to possess normal skills and
`
`knowledge in a particular technical field (as opposed to being a genius). I
`
`understand that in considering what the claims of a patent require, what was known
`
`prior to that patent, what a prior art reference discloses, and whether an invention
`
`is obvious or not, one must use the perspective of such a POSITA.
`
`5
`
`Petitioner AMD Ex-1002, 0009
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`
`C. Obviousness
`16.
`I have been informed and understand that a patent claim is obvious
`
`under 35 U.S.C. §103, and therefore invalid, if the claimed subject matter, as a
`
`whole, would have been obvious to a POSITA as of the priority date of the patent
`
`based on one or more prior art references and/or the knowledge of a POSITA.
`
`17.
`
`I understand that an obviousness analysis must consider (1) the scope
`
`and content of the prior art, (2) the differences between the claims and the prior art,
`
`(3) the level of ordinary skill in the pertinent art, and (4) secondary considerations,
`
`if any, of non-obviousness (such as unexpected results, commercial success, long-
`
`felt but unmet need, failure of others, copying by others, and skepticism of
`
`experts).
`
`18.
`
`I understand that a prior art reference may be combined with other
`
`references to disclose each element of the invention under 35 U.S.C. §103. I
`
`understand that a reference may also be combined with the knowledge of a
`
`POSITA, and that this knowledge may be used to combine multiple references. I
`
`further understand that a POSITA is presumed to know the relevant prior art. I
`
`understand that the obviousness analysis may take into account the inferences and
`
`creative steps that a POSITA would employ.
`
`19.
`
`In determining whether a prior art reference would have been
`
`combined with other prior art or other information known to a POSITA, I
`
`6
`
`Petitioner AMD Ex-1002, 0010
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`understand that the following principles may be considered:
`
`a. whether the references to be combined involve non-analogous art;
`
`b. whether the references to be combined are in different fields of
`
`endeavor than the alleged invention in the Patent;
`
`c. whether the references to be combined are reasonably pertinent to the
`
`problems to which the inventions of the Patent are directed;
`
`d. whether the combination is of familiar elements according to known
`
`methods that yields predictable results;
`
`e. whether a combination involves the substitution of one known
`
`element for another that yields predictable results;
`
`f. whether the combination involves the use of a known technique to
`
`improve similar items or methods in the same way that yields
`
`predictable results;
`
`g. whether the combination involves the application of a known
`
`technique to a prior art reference that is ready for improvement, to
`
`yield predictable results;
`
`h. whether the combination is “obvious to try”;
`
`i. whether the combination involves the known work in one field of
`
`endeavor prompting variations of it for use in either the same field or
`
`a different one based on design incentives or other market forces,
`
`7
`
`Petitioner AMD Ex-1002, 0011
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`where the variations are predictable to a POSITA;
`
`j. whether there is some teaching, suggestion, or motivation in the prior
`
`art that would have led one of ordinary skill in the art to modify the
`
`prior art reference or to combine prior art reference teachings to
`
`arrive at the claimed invention;
`
`k. whether the combination requires modifications that render the prior
`
`art unsatisfactory for its intended use;
`
`l. whether the combination requires modifications that change the
`
`principle of operation of the reference;
`
`m. whether the combination is reasonably expected to be a success; and
`
`n. whether the combination possesses the requisite degree of
`
`predictability at the time the invention was made.
`
`20.
`
`I understand that in determining whether a combination of prior art
`
`references renders a claim obvious, it is helpful to consider whether there is some
`
`teaching, suggestion, or motivation to combine the references and a reasonable
`
`expectation of success in doing so. I understand, however, that a teaching,
`
`suggestion, or motivation to combine is not required.
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`21. At the time the ’108 Patent was filed, a person of ordinary skill in the
`
`art would have had a bachelor’s degree in electrical or computer engineering or a
`
`8
`
`Petitioner AMD Ex-1002, 0012
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`related field, and at least two years of experience in design, development, and/or
`
`testing of memory circuits, related hardware design, or the equivalent, with
`
`additional education substituting for experience and vice versa.
`
`22.
`
`In determining the level of ordinary skill in the art, I considered, for
`
`example, the type of problems encountered in the art, prior art solutions to those
`
`problems, the rapidity with which innovations are made, the sophistication of the
`
`technology, and the educational level of active workers in the field.
`
`23.
`
`I met the definition of a POSITA from 1977 to present. I also had
`
`greater knowledge and experience than a POSITA. I worked with POSITAs from
`
`1975 to 2000, and beyond, and I am able to render opinions from the perspective of
`
`a POSITA based on my knowledge and experience. My opinions concerning the
`
`’108 Patent claims and the prior art are from the perspective of a POSITA, as set
`
`forth above.
`
`VI. SUMMARY OF MY OPINIONS
`24.
`I have been asked to consider whether the claims of the ’108 Patent
`
`are obvious over certain prior art references. As explained below in detail in this
`
`Declaration, it is my opinion that:
`
`a. Ground 1: Claims 1–3, 8, and 11–13 are rendered obvious by U.S.
`
`Patent No. 4,862,418 (“Cuppens”) and Dilip K. Bhavsar, Testing
`
`Interconnections to Static RAMs, IEEE (1991) (“Bhavsar”);
`
`9
`
`Petitioner AMD Ex-1002, 0013
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`b. Ground 2: Claims 1, 3, 6–8, and 10–11 are anticipated by U.S.
`
`Patent No. 4,241,307 (“Hong”);
`
`c. Ground 3: Claim 4 is rendered obvious by Hong and John Wakerly,
`
`Digital Design Principles and Practices, Prentice Hall (2d. 1994)
`
`(“Wakerly”).
`
`VII. BACKGROUND OF THE PATENT AND THE ART
`25. During the development, manufacturing, and field-service of
`
`microprocessors and computer systems it is necessary to test the processor or
`
`system. Testing a device generally involves controlling the input to the device,
`
`observing its output, and comparing that output with expected results. Testing is
`
`generally performed during development to identify design flaws, during
`
`manufacturing to detect structural defects, and during field service to diagnose
`
`device failures to replaceable units. The ’108 Patent refers to the book “Boundary-
`
`Scan Test, A Practical Approach” for technical background about testing. Ex-
`
`1001, 1:28-32.
`
`26. Through the 1970s, systems were constructed from components that
`
`were discrete or fabricated at small or medium levels of integration (SSI and MSI,
`
`about 100 transistors or fewer). Such components and the system boards
`
`constructed with them were generally tested with probes to access the input and
`
`output interface signals between components. Larger boards required many points
`
`10
`
`Petitioner AMD Ex-1002, 0014
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`to probe narrow lines on circuit boards, so the test fixture was called a “bed of
`
`nails.”
`
`27. As technology improved through the 1980s, Large- and Very-Large-
`
`Scale Integration (LSI and VLSI, about 1000 transistors or more) made it
`
`increasingly difficult to fully test such internally-complex components by
`
`accessing only the interface signals on pins. Additionally, the highly-integrated
`
`components required a large number of interface signals, so package assembly
`
`technology evolved from in-line pins to surface-mounted solder balls. Similarly,
`
`circuit boards had to carry many more interface signals, so signals were routed on
`
`multiple levels of the board. Together, these trends made many of the signals
`
`inaccessible to bed-of-nails probes. Furthermore, signal speeds were increasing to
`
`the point where probes contacting the metal lines of the circuit board interfered
`
`with the signals’ integrity.
`
`28. Consequently, the industry required an alternative to bed-of-nails
`
`probing, and the Joint Test Access Group (JTAG) developed IEEE standard 1149
`
`(IEEE Standard Test Access Port and Boundary-Scan Architecture). The standard
`
`covers a scan chain through each component’s interface signals (“boundary scan”)
`
`and routed between components on board, thereby providing moderate-speed,
`
`serial access to all the signals on the board. The scan chain also provides access to
`
`testing features within a component that can be used to observe and control its
`
`11
`
`Petitioner AMD Ex-1002, 0015
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`internal circuitry. For example, the figures reproduced below ( “Boundary-Scan
`
`Test, A Practical Approach” at p. 11) show how the insertion of multiplexers
`
`enables access to internal logic through boundary scan.
`
`
`
`29. The ’108 Patent relates to a “method of testing interconnects” between
`
`integrated circuits (ICs) “on a carrier, such as a printed circuit board….” Ex-1001,
`
`1:17–24, 5:8–15. The patent explains that a “known circuit has a main unit or core
`
`logic that is responsible for providing some arbitrary specified function in a normal
`
`mode of the circuit,” and a “test unit” used to “perform[] an interconnect test, i.e., a
`
`test whether the circuit is properly connected to a further circuit via its I/O nodes or
`
`IC pins.” Id., 1:28–45. “Efficient interconnect test of miniaturised [sic] and/or
`
`12
`
`Petitioner AMD Ex-1002, 0016
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`complex circuit assemblies is a necessary part of the production process of such
`
`assemblies.” Id., 1:38–40.
`
`30. The ’108 Patent admits that, long before its filing, built-in test circuits
`
`had been standardized by IEEE in the “boundary-scan test standard IEEE Std.
`
`1149.1.” Ex-1001, 1:28–2:58, 5:8–15; Ex-1008. The boundary-scan standard
`
`“defines test logic that can be included in an integrated circuit to provide
`
`standardized approaches to … testing the interconnections between integrated
`
`circuits once they have been assembled onto a printed circuit board or other
`
`substrate….” Ex-1008, 1-1. The standard “involves the inclusion of a shift-
`
`register stage (contained in a boundary-scan cell) adjacent to each component pin
`
`so that signals at component boundaries can be controlled and observed using scan
`
`testing principles.” Id., 1-3. A “pin” is the “point at which connection is made
`
`between the integrated circuit and the substrate on which it is mounted (e.g., the
`
`printed circuit board).” Id., 2-4. Figure 1-2 shows four exemplary ICs, along with
`
`boundary scan cells on each pin:
`
`13
`
`Petitioner AMD Ex-1002, 0017
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`
`
`
`31.
`
`Id., 1-4. “The boundary-scan cells for the pins of a component are
`
`interconnected so as to form a shift-register chain around the border of the design,
`
`and this path is provided with serial input and output connections and appropriate
`
`clock and control signals.” Id., 1-5. These cells “allow the interconnections
`
`between the various components to be tested” by shifting test data “into all the
`
`boundary-scan register cells associated with component output pins and loaded in
`
`parallel through the component interconnections into those cells associated with
`
`input pins….” Id.
`
`32. The ’108 Patent discloses two alleged improvements to this standard
`
`technology. First, it explains that the boundary-scan standard has an alleged
`
`14
`
`Petitioner AMD Ex-1002, 0018
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`“problem” in that it is “too expensive to reserve area for … boundary scan
`
`circuitry.” Ex-1001, 2:21–28. To address this problem, the patent proposes that
`
`for ICs where boundary scan is too expensive to implement, the boundary scan
`
`circuitry of an adjacent IC can be used to test the interconnects. Id., 4:61-68
`
`(“Low complexity memory types like Static Random Access Memories (SRAMs)
`
`and (Programmable) ROMs can readily be tested for their connectivity using
`
`neighbouring circuits equipped with boundary-scan or neighbouring
`
`microprocessors and/or ASICs.”).1
`
`33. Figure 4 illustrates testing the interconnects of a circuit 402 using the
`
`boundary scan chain 240 of a neighboring processor 210:
`
`
`1 All text emphasis and color annotations are added unless otherwise specified.
`
`15
`
`Petitioner AMD Ex-1002, 0019
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`
`Ex-1001, Figure 4
`
`
`
`34. Second, the ’108 Patent purports to disclose a way to improve testing
`
`throughput. In some cases, an IC whose interconnects need to be tested (e.g.,
`
`element 404 in Figure 4) might be a “high complexity memory” such as an
`
`SDRAM. Id., 3:61–4:11, 9:30–35. Such memories “are not suited as test units for
`
`interconnect testing” because they require “initialization” and/or “the process of
`
`exchanging data is too complex and therefore takes too much time. Id., 3:61–4:11.
`
`The patent proposes that, rather than perform test reads/writes to the high
`
`complexity memory, test reads/writes can be performed on a “test unit 406”
`
`composed of a “low complexity memory” such as an SRAM. Id., 4:22–28, 4:48–
`
`67, 9:30–36. Alternatively, the patent states that “for the test unit being operable
`
`as a low complexity memory,” “the test unit could be implemented as a
`
`16
`
`Petitioner AMD Ex-1002, 0020
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`combinatorial circuit,” such as an XOR or XNOR circuit. Id., 3:36–43, 4:61–67,
`
`10:7–12:19, Figs. 4–6.
`
`VIII. SPECIFIC EXPLANATION OF THE GROUNDS
`A. Ground 1: Claims 1–3, 8, and 11–13 are rendered obvious by
`Cuppens and Bhavsar
`1. Overview of Cuppens
`35. Cuppens is entitled “Non-Volatile, Programmable Semiconductor
`
`Memory Having Reduced Testing Time.” Id. Cuppens discloses using a test unit
`
`(a low complexity SRAM) to test a main unit (EEPROM memory). Figure 1
`
`shows the SRAM (elements 2 and 3, annotated in red) and the EEPROM (element
`
`1, annotated in blue).
`
`
`
`17
`
`Petitioner AMD Ex-1002, 0021
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`36. Cuppens explains the test unit shown in Figure 1: “According to the
`
`invention, volatile memory cells are taken for the test memory cells, for example of
`
`the dynamic random access type, or DRAM type … Static test memory cells can
`
`also be used….” Ex-1005, 2:49–59 (emphasis added). Thus, a POSITA would
`
`have understood that Cuppens disclosed the use of “static” random access memory,
`
`commonly abbreviated as “SRAM,” for the test memory cells. Figure 1 also
`
`includes “sense or read amplifiers and input/output gates 8, as well as logic circuits
`
`9, all of which are also part of the on-chip peripheral circuits. The logic circuits 9
`
`provide for signals, for example, for the activation of the semiconductor memory,
`
`the activation of the output gates, and for programming or write signals.” Ex-
`
`1005, 3:17–27.
`
`2. Overview of Bhavsar
`37. Bhavsar “describes a method for testing the interconnections of
`
`ordinary static RAM ICs with a microprocessor or a peripheral IC that has a
`
`boundary-scan register and an IEEE 1149.1 test-access port.” Ex-1006, 63.
`
`Bhavsar notes that while standardization of boundary scan “has paved the way for
`
`its widespread acceptance,” going forward “test engineers will have to deal with
`
`modules that have a mixture of compliant and noncompliant components—
`
`‘compliant components’ meaning those that implement” the boundary scan
`
`standard.” Id. To test interconnects with noncompliant components (e.g., SRAM)
`
`18
`
`Petitioner AMD Ex-1002, 0022
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`that lack boundary-scan circuity, Bhavsar proposes using an adjacent component
`
`that implements the boundary-scan standard. Id. Figure 1 shows use of a
`
`processor with boundary-scan circuits to test the interconnects of an SRAM:
`
`Ex-1006, Fig. 1
`
`
`
`38. Figure 6 is a magnified view showing “a segment of boundary-scan
`
`register at the processor chip’s RAM interface.” Id., 68.
`
`Ex-1006, Fig. 6
`
`
`
`39. The ’108 Patent’s disclosure of using a boundary-scan compliant
`
`component to test an adjacent, non-compliant SRAM is identical to Bhavsar’s
`
`disclosure. For example, Figure 2 of the ’108 Patent, and the accompanying
`
`19
`
`Petitioner AMD Ex-1002, 0023
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`explanation, is essentially identical to Figure 1 of Bhavsar:
`
`
`
` Ex-1001 (’108 Patent), Fig. 2
`
`Ex-1006 (Bhavsar), Fig. 1
`
`40. Compare Ex-1001, 1:66–2:28, 3:63–66, 8:42–65, Fig. 2 with Ex-1006,
`
`Fig. 1, 63–64. Similar to Bhavsar, the ’108 Patent explains that “boundary-scan is
`
`hardly available in memory devices due to pin count and/or pin compatibility
`
`considerations” and due to “price pressure.” Ex-1001, 2:25–28, 4:25–28. And, the
`
`’108 Patent duplicates Bhavsar’s solution—using an adjacent circuit (element 210
`
`in Figure 2) with boundary scan registers (element 240) to test a separate memory
`
`component (element 205), such as SRAM, for “open circuits and short circuits”
`
`between the two components. Ex-1001, 2:15–20, 8:42–65.
`
`3. Motivations to Combine
`It would have been obvious to combine Bhavsar and Cuppens.
`
`41.
`
`Bhavsar and Cuppens are in the same field—functionality testing of ICs. Cuppens
`
`focuses on testing “selection circuits” for the SRAM. Ex-1005, 1:28–56, 1:59–64,
`
`2:3–12. Bhavsar focuses on testing interconnects that write to and read from
`
`20
`
`Petitioner AMD Ex-1002, 0024
`
`

`

`Declaration of Dr. Donald Alpert
`Petition for Inter Partes Review of U.S. Patent No. 6,622,108
`SRAMs. Ex-1006, 63. A POSITA would have recognized the importance of
`
`conducting both types of testing on an SRAM, as both the selection circuits and the
`
`interconnects must function for the memory to work properly.
`
`42. Specifically, it would have been obvious to substitute Cuppens’
`
`electronic circuit (as defined in element 1[pre] below) into Bhavsar’s Figure 1 to
`
`replace Bhavsar’s “ordinary static RAM.” Bhavsar explains that that even though
`
`IEEE Standar