Silicon-gate
`
`technology
`
`Low-cost, large-scale integrated electronics based
`on metal-oxide-semiconductor design benefits from the
`application of silicon-gate technology
`
`L. L. Vadasz, A. S. Grove, T. A. Rowe, G. £. Moore
`
`Intel Corporation
`
`technology provides an advantageous ap(cid:173)
`Silicon-gate
`proach for implementing
`large-scale integrated arrays
`of field-effect
`transistors.
`Its advantages-principally
`resulting
`from the low threshold voltage and the self(cid:173)
`aligned gate structure buried under an insulator-ease
`these circuits to bipolar in(cid:173)
`the problem of interfacing
`tegrated circuits and increase both their performance
`and functional density, making MOS integrated circuits
`to use. This article re(cid:173)
`easier and more economical
`views recent progress with this technology and shows
`its application
`to the construction of complex digital
`functions as illustrated by a memory circuit.
`
`Much of the early enthusim,m for metal-oxide-semicon(cid:173)
`ductor (MOS) integrated circuits stemmed from their
`promise as low-cost digital functions. Optimism was
`based upon the apparent simplicity of integrated circuits
`made completely with self-isolated enhancement-mode
`transistors
`that could be constructed with a single
`diffusion step. By comparison, conventional bipolar
`integrated circuits typically involve four such steps.
`However, the growth of MOS circuitry has been slow(cid:173)
`compared with early expectations-for many reasons.
`I. Early device:. often had
`reliability problems,
`principally relating lo ion drift in the oxide film!> or to
`dielectric breakdown in the thin gate insulator resulting
`from static electricity.
`2. There wc:re device-availability 1>rohlems, and sys(cid:173)
`tems designed for MOS structures were delayed. (Thi~
`suggests that the production yields were not as high as
`expected.)
`3. For economy and to overcome the high-impedance
`drawback of MOS, it''> important to build large functions.
`This aim contributed to the yield dilliculties.
`4. The expected cost advantages have also been slow
`in materializing. Yield problems have kept device cosh
`high; but extra cost was incurred interfacing MOS to
`bipolar electronic,, an important requirement
`in many
`systems. Generally,
`this factor related
`to the incom(cid:173)
`patibility of power supply and of signal levels between
`the two types of circuits, and tended to force designer:,
`to all-MOS or all-bipolar systems rather than use each to
`its advantage.
`5. Performance of MOS circuits has restricted their
`applicability. The speed of MOS circuits is limited-for
`quite fundamental reasons-below
`bipolar structure~.
`
`28
`
`A
`
`B
`.----
`
`s,o,
`I
`
`"typr:::,
`
`FIGURE 1. A-First oxide cut after initial oxidation for sub(cid:173)
`sequent source, drain, and gate region. B-Second
`oxidation to define gate oxide thickness. C-Scanning
`electron microscope (SEM) photograph of a transistor
`fabrication at stage B.
`
`the other hand, MOS circuits clearly have
`On
`certain advantages.
`I. Their use permits logic circuits to be designed in
`a straightforward manner.
`2. The ability to usl: such combination~ a~ scrit:s gates
`greatly simplifie~ the circuitry, and the large fan-out
`and
`fan-in potential of a voltage-controlled device
`allows large margins for reliable operation.
`3. New circuit form~. particularly multiphascd-clockcd
`circuits, are practical.
`4. High-functional packing density can be achieved(cid:173)
`probably
`two to ten times as much function per unit
`silicon area as with conventional bipolar circuits using
`the same geometrical tolerances. The cost of processing
`
`IFEE Sj)Cctrum OCl 011m I 969
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
`
`

`

`A
`
`B
`
`I I I I I I
`
`A
`
`Sib, n tyr,c S1 P.
`
`I •
`
`S,U
`
`p
`
`FIGURE 2. A-Device of Fig.1(8) after deposition of nitride
`and amorphous silicon sandwich. 8-Definition
`of gate
`insulator and gate electrode dimensions and subsequent
`boron diffusion. C-Perspective
`view of structure of
`2(8). D-SEM photograph of the structure at end of this
`fabrication stage.
`
`i~ more nearly related to area than complexity. pointing
`to low cost pa function in complex circuits.
`isolation
`5. Mask
`la)OUl is simplified. No special
`structures
`need be considered. The high
`impedance
`levels and
`resulting
`lower current
`densities greatly
`simplify the interconnection
`problems by allowing use
`of high-resistance
`signal paths. Fewer mask la) crs arc
`generally required. The result is many fewer oversighb.
`Much effort has gone into improving MOS technology
`to remove the limitations while preserving as many of the
`advantages as possible.
`In general. there are several ways that each limitation
`can be allackcd. However. the use of polycrystalline sili(cid:173)
`con for the gate electrode affords a unique and powerful
`combination of properties
`that remove~ man) of the ob(cid:173)
`jections that have been raised regarding mctal-insulator(cid:173)
`(MIS) device~. 1.e
`scmiconductor
`
`Vadas,. Moon.:. Gron:. Ro,\.:
`
`Silii:on-gat~
`
`t~l'.hnology
`
`FIGURE 3. A-Device of Fig. 2(8) after deposition of silicon
`dioxide and definition of contact
`regions. 8-Final
`structure after deposition and definition of metal inter(cid:173)
`C-SEM
`connections.
`photograph
`of
`the
`completed
`transistor
`structure.
`
`A look at the technology
`the starting
`technology.
`As
`in conventional MOS
`material
`for silicon-gate
`technology
`is n-typc silicon.
`The wafer is first placed into an oxidizing atmosphere
`al high temperature and a relatively thick (about
`l µ111)
`la)cr of silicon dioxide is formed on its surface. Next.
`regions for the source and drain of the final device and
`the eventual channel
`regions arc defined by photo(cid:173)
`masking. The oxide is then etched from this area, as
`shown in Fig. I (A). The slice is placed into an oxidizing
`ambient again, and a la)cr of :,ilicon dioxide about 0.1
`µIll thick is formed in the window [Figs. l(B) and l(C)].
`Subsequently, a thin layer of silicon nitride (Si.N ,),
`another
`insulator,
`is deposited onto
`the entire surface
`of the wafer. Thi:, layer affects both the electrical charac(cid:173)
`teristics and the reliability
`in a desirable manner.
`Next, a thin layer of amorphous silicon is dcpo!>itcd
`on the wafer. The device structure at this point
`is as
`illustrated in Fig. 2(A).
`for
`to photomasking
`The structure now is returned
`rcmontl of the silicon and silicon nitride
`layers except
`where the gate area is to be or where the silicon tllm
`
`29
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
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`

`

`is intended for use as a circmt mterconnection layer.
`The thin oxide is also removed by exposing it to an oxide
`etch, as shown in Fig. 2(8).
`Finally, the wafer is placed into a diffusion furnace
`and boron-a p-type impurity that diffuses with relative
`rapidity in silicon, but very slowly in silicon nitride or in
`silicon oxide-is diffused into the surface of the struc(cid:173)
`ture. Consequently, after exposure, boron
`impurities
`will convert both then-type silicon wafer, where exposed,
`and
`the deposited silicon layer into p-type silicon;
`but the n-type regions under the oxide-covered areas are
`unaffected [Figs. 2(8), 2(C), and 2(D)].
`The device structure, except for the necessary inter(cid:173)
`connections, is now complete. A layer of silicon dioxide
`is deposited onto the entire surface-the exposed regions
`of the silicon wafer, the thick oxide layer covering most
`of the surface, and the deposited gate silicon. Openings
`are photoetched in this deposited silicon dioxide layer
`wherever a contact between the subsequent metalization
`and the underlying silicon wafer or deposited silicon is
`desired, as shown in Fig. 3(A). Aluminum is evaporated
`onto the surface so that it enters into these contact open(cid:173)
`ings, and the desired interconnection patterns are defined
`by another photomasking operation. The device now
`appears as shown in Figs. 3(8) and 3(C).
`It is desirable to protect the device both from me(cid:173)
`chanical damage to its intricate interconnection pattern
`and from contamination. For this reason, another layer
`of glass is deposited onto the wafer surface, and pat(cid:173)
`terned by subsequent photomasking and etching to ex(cid:173)
`pose the pads where bonding wires are to make contact
`with the aluminum interconnection pattern.
`It is interesting to note that, in fabricating this device,
`there is only one diffusion step, but there are five steps
`in which a thin film-an
`insulator or a conductor-is
`deposited. In the silicon-gate technology, yields, per(cid:173)
`formance, and reliability-thus,
`success or failure--all
`depend on the manufacturer's ability to control the thin(cid:173)
`film deposition steps.
`
`Overcoming MOS's past, poor performance
`Two key aims of MOS technological developments
`have been easier interfacing with bipolar circuitry, and
`higher component densities to decrease further the cost
`
`FIGURE 4. A de stable (static) inverter circuit. Figure of
`merit depends on operating voltages.
`
`~Voo
`
`7t 2
`
`1---------,----------Vaut
`
`r
`
`functions. The silicon-gate technology
`of electronic
`achieves significant improvements in both directions.
`Low threshold voltage. The minimum operating
`voltages that must be used in an MOS circuit are de(cid:173)
`termined by the gate voltage required to create a con(cid:173)
`ducting channel between source and drain-called
`the
`It
`is important
`that Vr be
`threshold voltage (Vr).
`relatively low, not only to interface to bipolar circuits,
`but to improve circuit performance.
`To demonstrate the improved performance attainable
`with the low threshold voltage compared with standard
`high-voltage technology, consider the use of a simple
`de stable (static) inverter. The significant points of
`speed. A
`comparison
`are power dissipation and
`figure of merit is the speed-power product. An appro(cid:173)
`priate tradeoff can be made for any given application.
`The inverter stage of Fig. 4 has an MOS transistor
`(Q,) and an MOS resistor (Q2) in series. It can be shown
`that the limit of circuit performance will be determined
`by the output transition from "zero" to "one."
`We can define an equivalent RC time constant for
`this transition. Since the MOS resistor, Q2, is a nonlinear
`resistor, a true time constant will not exist, but one can
`be approximated for the initial part of the transition.
`In terms of this time consta0.t, the advantage of a low(cid:173)
`voltage circuit is simply that, for the same power level,
`the resistor value can be significantly lower. In the power(cid:173)
`dissipating state the dissipation of an inverter is given by
`
`The characteristic time constant is given by
`
`(1)
`
`(2)
`
`where C is the load capacitance.
`The combination of these two equations will result in
`the expression for the power-speed product
`
`(3)
`
`Equation (3) illustrates that, for a given capacitive load,
`lower-voltage operation gives a more meritorious figure.
`In the silicon-gate technology, lowering the threshold
`voltage is achieved because a dielectric sandwich of
`silicon dioxide and silicon nitride is used under the
`gate and the gate electrode is made of heavily doped
`p-type silicon rather than of aluminum, as in conven(cid:173)
`tional MOS technology. The threshold voltage de(cid:173)
`pends on the electric field in the silicon reaching a
`certain critical value before a conducting channel ap(cid:173)
`pears. The higher the dielectric constant of the insu(cid:173)
`lator, the lower the gate voltage has to be.
`Silicon nitride has roughly twice the dielectric con(cid:173)
`stant of silicon dioxide, so its use might be expected to
`lower threshold voltages. When silicon nitride is de(cid:173)
`posited directly onto a silicon wafer, however, spurious,
`undesirable charges appear near the interface between
`the nitride and the silicon and actually increase the
`threshold voltage. But if the layer of silicon dioxide under
`the layer of nitride is thick enough, these charges can be
`eliminated and one can still benefit from the higher
`average dielectric constant of the resulting sandwich.
`The material from which the gate electrode is made
`also has a significant effect on the magnitude of the
`threshold voltage. The gate electrode and the silicon
`
`30
`
`IEEE spectrum OCTOBER 1969
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
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`
`

`

`wafer act, in a way, like the two electrodes of a battery;
`an electromotive force is developed between them that
`can add to or subtract from the threshold voltage. Ac(cid:173)
`cordingly, the use of p-typc silicon for the gate produces
`a threshold voltage for p-channel devices whose mag(cid:173)
`nitude is about one volt lower than it would be in a
`comparable aluminum-gate MOS. Thus, the combined
`use of a silicon nitride-silicon dioxide sandwich and of a
`p-typc silicon gate electrode results in threshold voltage
`values that arc typically two volts.
`Reducing parasitics. Reductions
`in parasitics attrib(cid:173)
`utable
`to silicon-gate
`technology arc equally
`imprcs-
`
`Aluminum
`interconnection
`
`Dittused
`interconnection
`
`S1l1con
`interconnection
`
`FIGURE 5. Photomicrograph of a small region of Intel's
`i-1101 256-bit RAM, showing the three possible modes of
`interconnection: diffused regions within the wafer, de•
`posited silicon, and metal interconnecting lines.
`
`FIGURE 6. Photomicrograph of static memory bits of
`three MOS memory products: (A) Intel's i-1101, (B) Tl's
`4003, (C) Fairchild's 3530.
`
`sive. This advantage accrues from a basic feature of
`this technology
`the gate electrode and the p-typc dif(cid:173)
`fused regions arc "self-aligned" as shown in Fig. 2(8).
`The gate electrode, or rather the dielectric under the gate
`electrode, is the diffusion mask that defines the edge of
`the source and drain
`regions. Thus,
`they arc auto(cid:173)
`matically aligned.
`In conventional MOS technology,
`this alignment
`is done by the superposition of two
`sequential masking operations. The inherent inaccuracy
`of manually aligning two patterns causes a certain tol(cid:173)
`erance for misalignment
`that has to be included in the
`design. This tolerance wastes space, resulting in larger
`device structures, and, in particular, introduces relatively
`large
`intcrclcctrode
`capacitances
`that degrade per(cid:173)
`formance. Major advantages of the self-aligned gate
`structure result from these reduced parasitic capacitances.
`I. Reduced gme capacitance. The thin gate oxide area
`is smaller. For a given channel
`length, the thin oxide
`region will extend over the source and drain regions only
`to the depth of the source-drain
`diffusion,
`typically
`< 1 µm with the silicon-gate technology. Since standard
`technologies have as much as an 8-10-µm gate overlap
`above
`the source and drain regions, gate capacitance
`reduction can be as much as 50 percent.
`item 1, it is
`2. Reduced Miller capacitance. From
`capacitances
`obvious
`that
`the gate-to-drain
`overlap
`have been reduced significantly by the use of a self(cid:173)
`aligned gate. This reduction can be as much as an order
`of magnitude for equivalent device size.
`is
`reduction
`3. Reduced ju11cti1111 capacitance. The
`mainly the result of reduced junction area. In a con(cid:173)
`ventional metal-gate device, the size of the drain junction
`is larger primarily because a minimum separation has
`to be kept between gate metal and the line connecting
`to the drain. With the silicon-gate technology, the metal
`connected
`to the drain can overlap
`the gate regions
`since there is an insulating
`layer separating
`the gate
`from the metal. The only constraint
`is
`the proximity
`of the drain contact to the gate region; junction area re(cid:173)
`duction is about 30--40 percent.
`High functional density. Smaller devices obviously
`contribute
`to higher packing density, but even more
`important
`is
`the circuit
`interconnection
`flexibility
`inherent
`in the silicon-gate technology. Figure 3 shows
`
`B
`
`One bit
`
`C
`
`One bit
`
`A
`
`One bit
`
`Vadasz, Moore, Grove, Rowe-Silicon-gate
`
`technology
`
`31
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
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`
`

`

`p+
`
`FIGURE 7. Capacitances associated with various types of
`interconnecting
`lines. Both metal and deposited silicon
`have a smaller capacitance per unit length than diffused
`region interconnections. For 10-µm-wide le lines, C, = 2.21
`pf /mm; C,, = 0.35 pf /mm; and CA1 = 0.28 pf /mm.
`
`FIGURE 8. Photomicrograph of Intel's i-1101 256-bit RAM.
`Block diagram is superimposed.
`
`interconnections are separated from
`that the aluminum
`the silicon-gate electrode by an insulator. Basically.
`this establishes all features necessary for metal patterns
`to cross the silicon film conductors,
`resulting
`in two
`layers of conductors
`above
`the substrate. The ad(cid:173)
`ditional use of diffused conductors
`in the substrate, as
`in other MOS technologies, gives flexibility approaching
`that of three layers for interconnecting complex function~
`efliciently. These
`interconnections
`are
`illustrated
`in
`Fig. 5. By contrast,
`in the standard MOS technology,
`the only crossover possible is metal-crossing diffused
`regions.
`An illustration of the higher packing den~ity of this
`
`32
`
`IHI spectrum OCTOIU.R 1969
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 005
`
`

`

`newer technology is given in Fig. 6, which compares a
`static memory bit from the silicon-gate memory array
`(described
`later) with a comparable bit from a circuit
`made using standard
`technology. The area saved ap(cid:173)
`proaches 50 percent. Similar area savings can be re(cid:173)
`alized in other circuits, using static or dynamic schemes.
`The use of deposited silicon for interconnection also
`reduces interconnection capacitances, further contribut(cid:173)
`the
`improved performance. Figure 7 shows
`ing
`to
`capacitance per unit length of three types of intercon(cid:173)
`nection lines. Clearly, metal or silicon layers are asso(cid:173)
`ciated with smaller parasitic
`capacitances
`than are
`diffused interconnections.
`Lowering the failure rate. In addition
`to the device
`characteristic
`advantages and component density
`in(cid:173)
`crease that silicon-gate
`technology provides, reliability
`benefits also result. The gate electrode and gate region
`in this device are buried under two layers of dielectrics.
`This shields the most sensitive region of the device from
`external contamination.
`In addition,
`the Si,:N, layer is a
`very effective barrier to ion migration. The use of lower
`voltages stresses the insulator less-also
`an advantage.
`Manufacturability.
`It has been well established
`that
`yield is a strong function of integrated circuit area. Thus
`the higher packing density can be expected to produce
`higher yields for a given circuit complexity. The early
`protection of the sensitive, thin insulator region by the
`silicon-gate electrode minimizes the chance of damage
`during subsequent processing. It appears
`that the high
`yields and resulting low costs and product availability
`originally projected
`for MOS circuits will be realized
`with the silicon-gate structure.
`
`proves
`Theory is one matter-practice
`All of the advantages of the silicon-gate technology
`can be illustrated by Intel's 1101, a 256-bit, random-access
`memory clement, fully decoded on the chip (i.e., including
`the circuitry necessary
`to select a particular bit from
`
`an eight-bit, binary-coded address) and with controls for
`read/write and inhibit modes provided. The functional
`block diagram superimposed on a photomicrograph of
`this element is shown in Fig. 8. The chip size is 3.10 X
`2.8 mm. It is packaged in a 16-leacl dual inline package
`(DIP). Operation and performance of this clement are:
`An 8-bit address code will select any one of 256 bits
`for either read or write operation. All address input logic
`levels are compatibk with standard bipolar TTL or DTL
`logic levels. The mode of operation ("read" or "write")
`is determined by the R/W input control. In the "read"
`mode, the information from the memory will be available
`on the outputs, typically, less than I µs later than appli(cid:173)
`cation of an address code. Note that there is no need to
`rewrite the data into the memory after a read operation
`since the read is nondestructive.
`is accomplished by the
`The "chip-select"
`function
`input. This renders both Rf W and data input
`"inhibit"
`leads ineffective and stops information
`transfer through
`the output buffer. The address decoder, however, is not
`inhibited-creating
`an effective increase in memory speed.
`The output
`leads are open while the memory array
`is
`inhibited, allowing OR-tying of many memory arrays.
`Typical access times-defined
`as the lapse between ap(cid:173)
`plication of an address code and the output of the TTL
`on the circuit are shown in Fig. 9.
`load-measured
`The difference between positive-going output delay
`and negative-going output delay is clue to the difference
`in driving capability of the push-pull output stage from
`the memory: A positive output transition from the TTL
`gate (negative
`transition
`from
`the MOS output) will
`always be 200-300 ns slower.
`The access time degradation as a function of capacitive
`loading is also shown in Fig. 9. Note that the degradation
`is about I ns/pF.
`Direct driving of bipolar circuits is accomplished by
`the use of a push-pull output stage on the i-1101. This
`output stage will typically "sink" 8 mA at a +0.45-volt
`output voltage (worst-case TTL
`logic zero level). Al(cid:173)
`though
`this drive capability
`is reduced at higher tem-
`
`FIGURE 9. Typical access time of i-1101 as a function of
`temperature. Outputs are those of TTL load and thus in(cid:173)
`verted from the actual memory output. Access time of
`i-1101 at a function of capacitive
`loading is also shown.
`Measurements are at room temperature.
`
`FIGURE 10. Typical current sinking capability of i-1101 at
`V,.,,, = +0.45 volt (worst-case TTL, DTL logic zero level) as
`a function of temperature. Note that two worst-case TTL
`loads need only 2.8 mA, whereas the i-1101 can sink more
`than double this figure over the whole temperature range
`of operation.
`
`C
`
`"'
`-0
`C
`0 800
`u
`Q)
`"' 0
`"' C
`.; 600
`E
`;:;
`"' 400
`"' Q)
`u
`u
`<C
`
`200
`
`Address~Outputs
`
`~~
`
`-55
`
`0
`
`25
`Temperature. 'C
`
`50
`
`100
`Capacitance. pF
`
`85
`
`J'iO
`
`10
`
`8
`
`6
`
`"' CJ
`CJ
`C.
`E
`~
`E
`i
`~
`4
`c3
`
`2
`
`Two worst-case TTL loads
`
`One worst-case TTL load
`
`-40
`
`-20
`
`0
`
`60
`40
`20
`Temperature, °C
`
`80
`
`100
`
`120
`
`Vadasz, Moore.:, Grove, Rowe.:
`
`·Silknn-gatc
`
`technology
`
`33
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
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`
`

`

`CJ ]3-
`:i
`>
`:i
`g-21 -----------------------,
`
`Worst case bipolar ·· 1 •· level
`
`Undetermined
`levels for i-1101
`
`l 1-.:...---------------------'
`
`Worst-case bipolar "O" level
`
`__j__
`
`-40
`
`...L-~--~-
`-20
`
`0
`
`.. L
`40
`20
`Temperature.
`
`60
`C
`
`80
`
`100
`
`FIGURE 11. Invalid input voltage levels for i-1101 compared
`with worst-case logic zero and one levels of TTL gates.
`
`in the cells and in the
`FIGURE 12. Power dissipation
`(1/0, decoder) for i-1101. Measure(cid:173)
`peripheral circuitry
`ments are at room temperature.
`
`FIGURE 13. A 4096-word by one-bit RAM organization using
`i-1101 RAM elements.
`
`300
`
`250
`~ ro
`-~
`200
`E
`ci ;::
`0 a..
`
`150
`
`100
`
`50
`
`0
`
`Cell and periphery voltages
`
`St I
`ro Je output.=[}
`
`Input
`R/W
`
`I
`
`I
`
`I
`....LL
`
`-
`1-1101
`-
`
`-
`-
`-
`
`-
`
`I
`...l.......L
`
`-
`
`f--
`
`I
`~
`
`~
`
`1-1101
`-
`
`-,
`
`-
`-
`-
`
`I
`....LL
`
`'
`
`:II
`
`-
`1-1101
`'--
`
`I
`
`-
`-
`
`-
`
`-
`
`-
`-
`-
`
`-
`
`I-
`
`il
`
`i-ll01
`
`-,
`
`....___
`
`l
`...l.......L
`-
`1-1101
`-
`
`7
`.....L..L
`
`1--
`
`'--
`
`-
`-
`-
`
`'--
`
`I
`....LL
`
`....___
`
`c..J
`
`I-
`
`ii
`-
`f--i-1101
`f--
`f--T
`;:Ll_
`- i-1101
`f--
`-
`T
`:il
`
`.....__
`
`I--
`
`I--
`
`,___
`~-
`
`i-1101
`
`T
`
`I-
`
`1--
`
`I-
`
`-
`-
`
`I--
`1-1101
`
`I-
`
`I
`
`.....__
`I
`:::==
`~
`
`-
`-
`-
`
`-
`1-1101
`-
`
`-,
`
`I
`.....L..L
`
`I--
`
`I--
`I--
`
`,___
`i
`
`-,
`- i-1101
`-
`-
`T
`1--~~J-
`- i-1101
`f--
`-
`'
`
`I
`I
`I
`
`-
`-
`-
`
`1-1101
`I-
`
`I
`,..LL
`
`....._
`
`I--
`
`I-
`
`- 1-1101
`-
`-
`
`'-----r
`
`I
`!
`
`I
`.....L..L
`
`i-1101
`
`I--
`
`I-
`
`'--,
`
`I--
`I--
`I--
`I--
`
`Address decoder
`to
`"inhibit"
`
`inputs
`
`Address decoder
`
`3-l
`
`!EH spectrum OCTOBLlt 1969
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 007
`
`

`

`is main(cid:173)
`loads)
`peratures, good fanout capability (>2
`tained even at 125°C. This is shown in Fig. 10.
`Input voltage levels also are compatible with bipolar
`circuitry. Figure 11 shows the range of invalid
`input
`voltages at various operating temperatures. For compari(cid:173)
`logic 1 and O level specifications
`for
`son, worst-case
`bipolar circuits are also included. Ample margins exist
`for direct bipolar/MOS
`at all temperatures
`interfacing.
`is typically less than 2 mW per bit
`Power dissipation
`for normal operation. This, however, can be lowered to
`below 50 µW. In standby mode-when
`the chip will
`only store information, but does not need to be accessed(cid:173)
`the peripheral power supply can be completely
`shut
`down. This "idle" cuts the total power drain by a factor
`of 2. Furthermore,
`the cell power can be reduced con(cid:173)
`siderably by reducing the cell voltage to - 2 volts. This
`generates only - 7 volts across the memory bits and is
`adequate
`for holding
`information
`in the memory cells.
`Figure 12 shows typical power dissipation in both the cells
`(decode, 1/0) circuitry. In this mode of
`and peripheral
`operation,
`the total power dissipation
`is less than 12
`mW, and corresponds
`to less than 50 µW/bit.
`Larger memory arrays can easily be built with this
`memory element. Sixteen packages can make a 4096-
`word X I-bit memory by simply OR-tying
`the outputs,
`paralleling all address lines, and decoding to each inhibit
`lead. This is shown in Fig. 13.
`An interesting feature of an array of i-1101 memory
`clements is that the inhibit lead becomes part of the ad(cid:173)
`dress inputs. This will allow improved performance
`for
`certain modes of operation. Since
`the
`inhibit/enable
`operation
`is much faster (~200
`ns) than
`the address
`decoding,
`it is possible to address all 16 clements of the
`array of Fig. 13, at the same time inhibiting 15 of the 16
`packages. Once the first element
`is accessed (say in I
`µs), 15 more bits of data at 200-ns intervals are obtainable
`only if the inhibit leads arc switched. This gives a total
`of 4 µs for accessing 16 bits of data, or 250 ns average
`access time per bit.
`
`The combination counts
`To be sure, other MIS processes possess some of the
`advantages
`of
`the silicon-gate
`technology. Lowered
`threshold voltages
`can be obtained
`using different
`crystal orientation,
`or by utilizing multiple dielectric
`layers under the gate electrode. '3 Use of a molybdenum
`gate electrodc 4 can also achieve a self-aligned structure
`and the use of ion implantation" can give the same result
`with conventional
`aluminum electrodes. However,
`the
`combination
`of desirable
`features available with
`the
`silicon-gate structures appears
`to be truly unique.
`
`REFERENCES
`I. Samec, J. C., Kerwin, R. E., Klein, D. L., and Edwards, R.,
`"Metal-nitride-oxide
`silicon
`fidd-ctkct
`transistors
`with
`sdf(cid:173)
`aligned gates,'' Solid State Elec., vol. 11, pp. 653-660, July 1968.
`2. Faggin, F., Klein, T., and Yadasz, L., "Insulated
`gate fidd
`dl\!ct transistor
`circuits with silicon gates," prcscnt~d
`integrated
`at the IEEE
`lnternat'l Electron Device Meeting, Oct. 1968.
`3. Nigh, H. E., Stach, J., and Ja,·obs, R. M., ·•Afield-gate
`IGFET,"
`presented at the Solid-State Devic.: Research Conf., 1967.
`4. Brown, D. M., Engcler, W. E., Garfinkel, M., and Gray, P. V.,
`Solid State Elect.,
`"Refractory metal silicon device technology,"
`vol. 11, pp. I 105-1112, Dec. 1968.
`5. Bower, R. W., Dill, H. G .. Aubuchon, K. G., and Thompson,
`S. A., "MOS
`field-effect transistors
`formed by gate masked
`ion
`IEEE Trans. Electron Del'ices, vol. ED-15, pp.
`implantation,"
`757-761, Oct. 1968.
`
`Yadasz, Moore, Grove, Rowe-Silicon-gate
`
`technology
`
`Leslie L. Vadasz (M) received
`the bachelor of engineering
`degree from McGill University,
`Montreal, Quebec. He has ac(cid:173)
`cumulated
`extensive
`experi(cid:173)
`ence in the field of semicon(cid:173)
`ductor
`technology during
`the
`past eight
`years-first
`with
`Transitron,
`then with Fairchild
`Semiconductor,
`and more re(cid:173)
`cently with Intel. At Transitron,
`he studied gold doping of sili(cid:173)
`resistance of silicon materials and
`con and the radiation
`devices. As manager of the MOS Circuit and Technology
`Section at Fairchild, he worked on bipolar integrated circuit
`development
`and MOS circuit
`technology.
`
`Gordon E. Moore (F) has par(cid:173)
`ticipated
`in the creation of two
`companies within
`the
`last 13
`years. In 1957 he was cofounder
`of Fairchild
`Semiconductor.
`After serving Fairchild as man(cid:173)
`ager ot engineering and director
`of research and development,
`he left last year to help found(cid:173)
`and become vice president of(cid:173)
`Intel Corporation. Earlier in his
`career Dr. Moore received
`the
`the University of California, Berkeley,
`from
`B.S. degree
`and the Ph.D., in chemistry and physics,
`from California
`Institute of Technology. He then worked
`for three years
`at the Applied Physics Laboratory, Johns Hopkins Uni(cid:173)
`versity, and another year at the Shockley Semiconductor
`Laboratory, Beckman
`Instrument Corporation. He has
`authored more than a score of technical papers and con(cid:173)
`tributed
`to a McGraw-Hill text.
`
`Andrew S. Grove
`(M) was
`awarded
`the B.S. degree from
`the City University of New York
`(1960) and
`the Ph.D. degree
`from
`the University
`of Cali(cid:173)
`fornia, Berkeley
`(1963). There(cid:173)
`upon, he joined
`the Physics
`Department
`at
`the Research
`and Development
`Laboratory,
`Fairchild Semiconductor.
`In 1966
`he became head of Fairchild's
`Surface and Device Physics
`Section, and in 1967, assistant director of research and
`development.
`Last July, he participated
`in
`founding
`Intel Corporation and
`is now its director of operations.
`Dr. Grove lectures at the University of California, Berkeley,
`and serves on the Administrative Committee of the IEEE
`Electron Devices Group. He is author of more than 30
`technical papers and a book, "Physics and Technology
`of Semiconductor Devices"
`(Wiley). He also holds
`the
`IEEE Region Six 1969 Achievement Award for contributions
`to MOS technology.
`
`Thomas A. Rowe earned
`the
`bachelor
`of science
`degree
`(metallurgy) and the master of
`science degree (materials)
`from
`the Massachusetts
`Institute of
`Technology
`and
`then
`joined
`Fairchild Semiconductor where
`he worked until
`joining
`Intel
`last year. At Fairchild he had
`responsibility
`in the areas of
`metalization, dielectric deposi-
`tion, masking, epitaxial, and
`starting wafer evaluation and product
`responsibility
`for
`TTL logic devices. He has also done research on dual-layer
`metal processing and metalization
`reliability and on the
`development
`of a high-reliability
`process
`for bipolar
`military products. Mr. Rowe previously coauthored an
`article for the Physical Review.
`
`35
`
`MICROCHIP TECH. INC. - EXHIBIT 1023
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 008
`
`