i486”II MICROPROCESSOR
`
`l Binary Compatible with Large
`Software Base
`— MS-DOS", OS/2**, Windows
`—UNIX*** System V/386
`—iRMX®, iFtMKTM Kernels
`-
`-
`-
`HI h Inte ration Enables On-Chl
`' _% Kbytg Code and Data Cache”
`—Floating Point Unit
`—Paged, Virtual Memory Management
`l Easy To Use
`— Built-In Self Test
`—-Hardware Debugging Support
`—-lntel Software Support
`—Extensive Third Party Software
`Support
`
`I High Performance Design
`—Frequent Instructions Execute in One
`Clock
`—25 MHz and 33 MHz Clock
`Frequencies
`.
`— 106 Mbyte/Sec Burst Bus
`—CHMOS IV Process Technology
`I Complete 32-Bit Architecture
`, —Address and Data Busses
`_ Registers
`I Multiprocessor Support
`— Multiprocessor Instructions
`—Cache Consistency Protocols
`— Support for Second Level Cache
`
`The i486TM CPU offers the highest performance for DOS, 08/2, Windows and UNIX System W386 applica-
`tions.
`It is 100% binary compatible with the 386TM CPU. One million transistors integrate cache memory,
`floating point hardware and memory management on-chip while retaining binary compatibility with previous
`members of the 86 architectural family. Frequently used instructions execute in one cycle resulting in RISC
`performance levels. An 8 Kbyte unified code and data cache combined with a 106 Mbyte/Sec burst bus at
`33.3 MHz ensure high system throughput even with inexpensive DRAMs.
`
`New features enhance multiprocessing systems. New instructions speed manipulation of memory based sem-
`aphores. On-chip hardware ensures cache consistency and provides hooks for multilevel caches.
`
`The built in self test extensively tests on-chip logic, cache memory and the on-chip paging translation cache.
`Debug features include breakpoint traps on code execution and data accesses.
`
`i486TM Microprocessor Pipelined 32-Bit Microarchitecture
`$4 Blt Intorunlt Transfer Bu:
`
`
`SZ-blt Data Bus
`
`
` SZ-bll Data Bus
`
`
`Bu: Interlaco
`Segmentation
`
`Unlt
`
`Dlserlptor
`
`
`-— Room-r:
`Physical
`Address
`Do-Dsi
`lelt and
` Translation
`
`
`Mtrlbutl
`Lookasldi
`
`
`
`FLA
`Buffer
`ADS w Ry D cl;
`
`v LOCK PLOCKII
`u it?» coyvé
`
`Bus Control
`BOF if A20
`EREQ
` Roqulst Soquonc-r
`HOLD HLDA 2557
`mm NMI
`raw IGNNEI}
`
`aan; BLAST];
`sz Byto Cod-
`
`____________
`Control and —_
`— ou-u-
`
`
`
`Protcctlon 'Ilst
`
`
`2 x ‘5 BY“!
`BSIG'} ESE”
`_ Instruction
`Decod-
`
`Unit
`
`
`
`
`
`AHO D. EAD II
`Instruction
`
`
`-------------
`KENI[ FLUSH
`chodod
`Fa|h
`Control
`
`
`
`ROM
`
`
`Parity Genlmtlon
`DPo-Ps
`and Control
`
`240440—1
`
`Az-ui.
`Bum-am
`
`.
`
`Floating
`Pulnt
`”Unit
`F.P. Register
`Flle
`
`
`
`
`
`iFIMX, iRMK, 386, 387, 486, i486 are trademarks of Intel Corporation.
`‘MS-DOS® is a registered trademark of Microsoft Corporation.
`"OS/2W is a trademark of Microsoft Corporation.
`”*UNIXTM is a trademark of AT&T.
`
`Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
`licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
`April 1989
`© Intel Corporation, 1989
`Order Number: 240440-001
`
`Petitioner Samsung EX-1009, 0001
`
`Petitioner Samsung Ex-1009, 0001
`
`