(12) United States Patent
`Block et al.
`
`USOO6397375B1
`(10) Patent No.:
`US 6,397,375 B1
`(45) Date of Patent:
`May 28, 2002
`
`(54) METHOD FOR MANAGING METAL
`RESOURCES FOR OVER-THE-BLOCK
`ROUTING IN INTEGRATED CIRCUITS
`
`(*) Notice:
`
`(75) Inventors: Adam Stuart Block, Fort Collins;
`Jeffrey P Witte; Don D. Josephson,
`both of Ft Collins, all of CO (US)
`(73) Assignee: Hewlett-Packard Company, Palo Alto,
`CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`(21) Appl. No.: 09/507,240
`(22) Filed:
`Feb. 18, 2000
`(51) Int. Cl." ......................... G06F 17/50; H01L 25/03;
`HO3K 19/00
`(52) U.S. Cl. .......................................... 716/14; 326/101
`(58) Field of Search .......................... 716/1-21; 326/41,
`326/47, 101-103
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,841,664 A 11/1998 Cai et al. ...................... 716/14
`5,859.999 A
`1/1999 Morris et al. ............... 712/224
`5,860,017 A
`1/1999 Sharangpani et al. ......... 712/23
`5.984.510 A * 11/1999 Guruswamy et al. ......... 716/12
`6,014,507 A * 1/2000 Fujii ........................... 716/12
`6,230,304 B1 * 5/2001 Groeneveld et al. ........... 716/7
`OTHER PUBLICATIONS
`Guan et al. (“An area minimizing layout generator for
`random logic blocks”, Proceedings of the IEEE 1995 Cus
`tom Integrated Circuits Conference, May 1, 1995, pp.
`457-460).*
`Taliercio et al. (“A procedural datapath compiler for VLSI
`full custom applications”, Proceedings of the IEEE Custom
`Integrated Circuits Conference, May 12, 1991, pp. 22.5/
`1-22.5/4).*
`Ammar et al. (“A high density datapath compiler mixing
`random logic with optimized blocks, Proceedings of 4th
`European Conference on Design Automation, 1993, with the
`European Even in ASIC Design, Feb. 22, 1993, pp.
`194-198).*
`
`Panyam et al. (“An optimal algorithm for maximum two
`planar subset problem”, Proceedings of Fourth Great Lakes
`Symposium on VLSI, Design Automation of High Perfor
`mance VLSI Systems, Mar. 4, 1994, pp. 80–85).*
`Danda et al. (“Optimal algorithms for planar over-the-cell
`routing problems”, IEEE Transactions on Computer-Aided
`Design of Integrated Circuits and Systems, Nov. 1996, vol.
`15, No. 11, pp. 1365–1378).*
`Cong et al. (“General models and algorithms for over-th
`e-cell routing in Standard cell design”, Proceedings of 27th
`ACM/IEEE Design Automation Conference, Jun. 24, 1990,
`pp. 709–715).*
`Tsuchiya et al. (“A three-layer over-the-cell multi-channel
`routing method for a new cell model”, Proceedings of the
`ASP-DAC 95/CHDL 95/VLSI 95 Design Automation
`Conference, Aug. 29, 1995, pp. 195-202).*
`Danda et al. (“Optimal algorithms for planar over-the-cell
`routing in the presence of obstacles', Proceedings of the 8th
`International Conference on VLSI Design, Jan. 4, 1995, pp.
`3–7).*
`Wolfe, Alexander, “Patents Shed Light on Merced.” Elec
`tronic Engineering Times, Feb. 15, 1999, pp. 43–44.
`Interactive Repeater Insertion Simulator (IRIS) System And
`Method, Application No. 09/329556, Filed Jun. 10, 1999,
`Inventor: John D. Wanek.
`* cited by examiner
`Primary Examiner Matthew Smith
`ASSistant Examiner-Phallaka Kik
`(57)
`ABSTRACT
`A method and System for managing metal resources in the
`physical design of integrated circuits is presented. Percent
`metal usage is allocated for intra-block routing use by each
`functional block. Power and clock grids are established.
`Block designers coordinate the locations of Signal ports of
`the blockS So as to avoid blocking any inter-block signals,
`areas of metal are then reserved for ports and intra-block
`Signals. The inter-block Signals are then pre-routed, avoiding
`the power grid, clock grid, and reserved intra-block routing
`metal. If any problem nets emerge from the pre-routing,
`better port locations and Sub-block placement within the
`respective blocks are determined and the process is repeated.
`8 Claims, 7 Drawing Sheets
`
`iod
`
`(start y
`
`ALLOCATEPERCENE USAGE
`OFRETAFORSEBY
`BLOCKS
`
`ESTABLISHPOWERGRD
`
`1.96
`
`g
`ESTABLISHCLOCKSRID
`
`& CoRDATELOcarios
`(FSIGNALPORTS
`BETWEEBLOCK
`OESGNERSSOASO
`AppBCSNSA
`INTERBLOCKSIGNALS
`— & RESERVE METAL FOR
`
`PORTS &MINTRA-BLOCK
`SIGNALS
`t
`PREROUTEINERBEOCK
`SIGNALSAWOIDINSPOWER
`GRID, CLOCKGRID, AND
`RESERWECBLOCKMETA
`
`fi2
`
`PROBLEM8ETS?
`s
`
`DONE -X
`
`N-DETERMINEBETTErport
`LOCATIONSARCINTERNAL
`BLOCKAGE PLACEMENT
`BASECONPRROUTINC
`
`Page 1 of 11
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 1 of 7
`
`US 6,397,375 B1
`
`1O
`\-N
`
`-----
`
`E
`
`D
`
`20C
`
`20d-/
`
`C
`
`l
`
`20a
`20e-/
`22- - s—
`
`2Ob 1 Nu
`
`B
`
`A
`
`1O
`
`24d
`
`24d
`
`N is
`
`24e
`
`E
`
`24eM
`
`20e -
`22-/
`
`d
`
`t
`
`24C
`
`20d-/
`
`C
`
`20C
`-
`
`20a
`
`2Ob 1 N
`
`---
`
`B
`
`24b
`
`— -
`A
`
`24
`
`-
`
`24a
`
`--
`
`. . .
`
`Page 2 of 11
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 2 of 7
`
`US 6,397,375 B1
`
`
`
`QOZ
`
`BOZ
`
`GW
`
`8 W
`
`ZW
`
`Page 3 of 11
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 3 of 7
`
`US 6,397,375 B1
`
`1 O2
`
`
`
`
`
`104
`
`ALLOCATE PERCENT USAGE
`OF METAL FOR USE BY
`BLOCKS
`
`
`
`ESTABLISHPOWER GRID
`
`106
`
`
`
`ESTABLISHCLOCKGRID
`
`108
`
`110
`
`112
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`COORDINATE LOCATIONS
`OF SIGNAL PORTS
`BETWEEN BLOCK
`DESIGNERS SOAS TO
`AVOID BLOCKING ANY
`INTER-BLOCKSIGNALS
`
`
`
`RESERVE METAL FOR
`PORTS AND INTRA-BLOCK
`SIGNALS
`
`PREROUTEINTER-BLOCK
`SIGNALS, AVOIDING POWER
`GRID, CLOCK GRID, AND
`RESERVED BLOCK METAL
`
`PROBLEM NETS?
`
`
`
`
`
`DETERMINE BETTERPORT
`LOCATIONS AND INTERNAL
`BLOCKAGE PLACEMENT
`BASED ON PREROUTING
`
`FIG. 3
`
`Page 4 of 11
`
`

`

`U.S. Patent
`US. Patent
`
`May 28, 2002
`May 28, 2002
`
`Sheet 4 of 7
`Sheet 4 0f 7
`
`US 6,397,375 B1
`US 6,397,375 B1
`
`
`
`mow
`
`
`
`Page 5 ofll
`
`Page 5 of 11
`
`

`

`U.S. Patent
`US. Patent
`
`May 28, 2002
`May 28, 2002
`
`Sheet 5 of 7
`Sheet 5 0f 7
`
`US 6,397,375 B1
`US 6,397,375 B1
`
`
`
`ezy
`va
`
`
`
`b.GE
`
`Page 6 ofll
`
`Page 6 of 11
`
`

`

`U.S. Patent
`US. Patent
`
`May 28, 2002
`May 28, 2002
`
`Sheet 6 of 7
`Sheet 6 0f 7
`
`US 6,397,375 B1
`US 6,397,375 B1
`
`
`
`
`
`5.GE
`
`Page 7 ofll
`
`Page 7 of 11
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 7 of 7
`
`US 6,397,375 B1
`
`
`
`q0ff
`
`
`
`q9Þ–/_T TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT
`
`
`
`
`
`7.
`
`Page 8 of 11
`
`

`

`US 6,397.375 B1
`
`1
`METHOD FOR MANAGING METAL
`RESOURCES FOR OVER-THE-BLOCK
`ROUTING IN INTEGRATED CIRCUITS
`
`FIELD OF THE INVENTION
`The present invention pertains generally to interconnect
`routing in integrated circuit design, and more particularly to
`a method for managing the metal resources used in over
`the-block routing in integrated circuits.
`
`2
`more metal layerS and interconnects per layer are required
`than ever before. The result is that the routing task has
`become even more complex.
`Generally, the lowest level metal layers are used by local
`block interconnects, i.e., intra-block Signals, and higher
`level metal layers are used by inter-block interconnects.
`Each layer includes a power grid and clock distribution
`Signals. In high density integrated circuits, all of the intra
`block routing often cannot be achieved within the lowest
`level metal layers. Accordingly, metal in the higher layers
`must often be reserved for intra-block routing.
`It is clear from this description that Several distinct route
`types compete for the available metal resources in the
`different metal layers. In this respect, the power grid, the
`clock distribution System, the intra-block routing, and the
`global inter-block routing all compete for metal on Some, if
`not all, of the metal layers. Therefore, unless metal tracks in
`each of the higher-level metal layers are Specifically Set
`aside on each of those layerS for each of the respective
`routing types, the auto-router may not be able to find a
`complete or Satisfactory routing Solution.
`In the prior art, a number of metal tracks in each layer are
`pre-allocated for use by each of the different route types.
`Once a track is pre-allocated for use by a particular route
`type, its use must remain for that purpose. Block designers
`must design the blockS to interface with the pre-assigned
`track assignment, which therefore often limits the different
`combinations of placement of Signal ports and Sub-blockS
`within the block. Accordingly, optimal placement of Sub
`blocks often cannot be achieved. In addition, Since the track
`assignments are immutable, blocks that require more upper
`layer intra-block interconnects often must occupy more chip
`Space just to be able to connect to pre-allocated intra-block
`tracks on those layers. Similarly, blocks that require leSS
`upper-layer intra-block interconnects often do not fully
`utilized pre-allocated intra-block tracks that pass over them.
`Accordingly, it is clear that the density of the chip is directly
`affected by the efficiency of use of the upper-level metal
`layers.
`It is therefore an object of the invention to provide a metal
`management methodology that makes more efficient use of
`the available metal in each layer.
`SUMMARY OF THE INVENTION
`The present invention is a novel method and System for
`managing metal resources during over-the-block routing of
`an integrated circuit.
`The metal management methodology enables advantages
`in efficiency over the prior art. The communication between
`block designers as to the block routing requirements facili
`tates better placement of Sub-blockS and Signal ports. This
`results in more efficient use of over-the-block routing metal,
`as well as facilitates the ability to create higher density
`blocks. In addition, the allowance of multi-use tracks in
`over-the-block routing results in less unused metal and
`therefore also allows higher density blockS.
`BRIEF DESCRIPTION OF THE DRAWING
`The invention will be better understood from a reading of
`the following detailed description taken in conjunction with
`the drawing in which like reference designators are used to
`designate like elements, and in which:
`FIG. 1 is a top view layout diagram of an integrated
`circuit;
`FIG. 2 is a side view of a portion of the integrated circuit
`of FIG. 1;
`
`BACKGROUND OF THE INVENTION
`Integrated circuits comprise a plurality of electronic com
`ponents that function together to implement a higher-level
`function. ICS are formed by implanting a pattern of transis
`tors into a Silicon wafer which are then connected to each
`other by layering multiple layers of metal materials, inter
`leaved between dielectric material, over the transistors. The
`fabrication process entails the development of a Schematic
`diagram that defines the circuits to be implemented. A chip
`layout is generated from the Schematic. The chip layout, also
`referred to as the artwork, comprises a set of planar geo
`metric shapes over Several layers that implement the cir
`cuitry defined by the Schematic. A mask is then generated for
`each layer based on the chip layout. Each metal is then
`Successively manufactured over the Silicon wafer according
`to the layer's associated mask using a photolithographical
`technique.
`The process of converting the Specifications of an elec
`trical circuit Schematic into the layout is called the physical
`design proceSS. CAD tools are extensively used during all
`Stages of the physical design process. The physical design
`process is accomplished in Several Stages including
`partitioning, floorplanning, and routing.
`During the partitioning Stage, the overall integrated circuit
`is partitioned into a set of functional Subcircuits called
`blocks. The block partitioning process considers many fac
`tors including the number and size of the blocks, and number
`of interconnections between the blocks. The output of par
`titioning is a set of blockS along with a Set of interconnec
`tions required between blocks, referred to herein as a netlist.
`During the floorplanning Stage, a floorplan is developed
`defining the placement and rectangular shape of each block.
`The goal of the floorplanning Stage is to Select the optimal
`layout for each block, as well as for the entire chip.
`Once an acceptable floorplan is developed, the intercon
`nections between the blocks (as defined by the netlist) are
`routed. The Space not occupied by the blockS is partitioned
`into rectangular regions referred to as channels. Intercon
`nects are preferably routed within the designated channels,
`but may also be routed through defined feedthroughs
`through the blocks, or in defined over-the-block routing
`Space.
`The goal of a router is to complete all circuit connections
`resulting in minimal interconnect Signal delay. Where
`possible, the router will generally attempt to route individual
`interconnects on a Single layer; however, if this is not
`achievable given the topology of the netlist, an interconnect
`may be routed over two or even more layers. Often, inter
`connect routes resulting from the autorouting will be too
`long to meet Signal delay Specifications. The delay results
`from the inherent RC characteristics of the interconnect line.
`Over the past decades, integrated circuits (ICs) of increas
`ingly higher density have been developed to meet industry
`demands of higher performance and Smaller packaging. The
`very high densities of today's integrated circuits means that
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Page 9 of 11
`
`

`

`3
`FIG. 3 is a flowchart of the general method of the
`invention for managing metal resources,
`FIG. 4 is a top view of the layout of the IC of FIG. 1
`illustrating the functional blocks overlaid by the reserved
`over-the-block metal M4 areas after the blocks have been
`designed in accordance with the guidelines,
`FIG. 5 is a breakout perspective view of a portion of the
`IC of FIG. 1 illustrating an example implementation of the
`power grid;
`FIG. 6 is a breakout perspective view of a portion of the
`IC of FIG. 1 illustrating an example implementation of the
`clock grid;
`FIG. 7 is a breakout perspective view of a portion of the
`IC of FIG. 1 illustrating an example implementation of the
`intra-block routing metal usage of a functional block, and
`FIG. 8 is a breakout perspective view of a portion of the
`IC of FIG. 1 illustrating the example implementation of
`FIGS. 5, 6 and 7 and the remaining available metal available
`for use by global inter-block routing.
`
`15
`
`DETAILED DESCRIPTION
`A novel method and System for managing metal resources
`during over-the-block routing of an integrated circuit is
`described in detail hereinafter.
`FIG. 1 is a top view layout diagram of an integrated circuit
`(IC) 10. IC 10 includes functional blocks A, B, C, D, and E,
`referenced at 20a-20e. Channels 22 occupy the area
`between blocks 20a-20e. Inter-block communication is
`preferably achieved via channel-based routing where poS
`Sible. In high-density circuits, however, over-the-block rout
`ing is usually necessary for efficiency purposes, and the
`higher the density of the circuit, the more metal layers are
`typically required.
`FIG. 2 is a side view of a portion of integrated circuit (IC)
`10. FIG. 2 illustrates functional blocks 20a and 20b (not to
`Scale) implemented in Silicon layer 12. Metal layers
`M1-M6, sandwiched with intervening dielectric layers (not
`shown), are layered one on top of the other as illustrated. The
`metal on each layer M1-M6 is preferably formed in parallel
`tracks, where the direction of the tracks in adjacent layerS is
`orthogonal.
`AS described previously, the lowest level metal layers are
`used by local block interconnects, i.e., intra-block signals,
`and higher-level metal layers are used by inter-block inter
`connects. Each layer includes a power grid and clock
`distribution Signals. In the illustrated example, metal layers
`M1-M3 are used exclusively for intra-block routing, while
`layers M4-M6 are used mainly for inter-block routing and
`any intra-block routing that could not be achieved at the
`lower layers.
`FIG. 3 is a flowchart of the general method 100 of the
`invention for managing metal resources. At the beginning of
`the physical design process, a general guideline as to the
`percentage of M4 metal that will be allocated for use by each
`block is established 102. Preferably, the percent allocation is
`determined on an individual basis according to the amount
`of metal each block is expected to utilize (as estimated by
`the block designers), and therefore the amount may be
`different for each block. The flexibility in the allocation of
`amount of M4 metal allows blocks with large requirements
`for M4 to receive it, yet does not unnecessarily reserve it for
`blocks that will not end up utilizing the metal. In the
`preferred embodiment, the default amount of M4 is 30%, yet
`Some blocks may use up to 100% of the M4 metal over the
`block.
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 6,397.375 B1
`
`4
`The layout of the power grid is established 104 in the M5
`and M6 layers to provide the basic power Supply infrastruc
`ture from the flip-chip solder bumps (not shown) which
`connect to the M6 power grid to the block owners M4 grid.
`FIG. 5 is a perspective view of a portion of IC 10 showing
`the break-out of layers M4, M5, and M6. Each of metal
`layers M6, M5, and M4 comprise a plurality of parallel
`metal tracks. The tracks in each layer are orthogonal to the
`tracks in each of its adjacent layers. Accordingly, M5 tracks
`are perpendicular to the M4 and M6 tracks. In the illustrative
`example, the top layer of the power grid is established on
`tracks 40a, 40b, and 40c of M6. Each of these tracks 40a,
`40b, 40c connect to power grid tracks 50a, 50b, 50c and 50d
`of layer M5, which in turn connect to power grid tracks 60a,
`60b, 60c of layer M4. In actuality, each power grid track
`40a–40c, 50a–50d, and 60a-60c comprises at least two
`individual trackS-one for power and one for ground. They
`may also comprise additional tracks for different power
`levels, for example, a 3.3 Volt and a 5 Volt line. For
`Simplicity, the power grid tracks are illustrated as a Single
`track; however, it is to be understood that each power grid
`track may actually comprise any number of individual tracks
`for each distinct power/ground level in the power grid.
`After establishing the layout of the power grid, the layout
`of the clock grid is then established 106 (FIG. 3). The
`establishment of the clock grid prior to assigning metal to
`use by blocks or for inter-block routing enables more
`efficient use of metal to lower clock skew and increase
`performance. FIG. 6 is a perspective view of the same
`portion of IC 10 of FIG. 5. In the illustrative example, the
`clock grid is established on tracks 42a and 42b of M6. Clock
`grid trackS 42a, 42b connect to clock grid trackS 52a, 52b,
`of layer M5, which in turn connect to clock grid tracks 62a,
`62b of layer M4. In actuality, each clock grid track 42a-42b,
`52a-52b, and 62a-62b may comprise a plurality of indi
`vidual tracks, for example, a global clock signal CK, it's
`complement CK', and a plurality of local clock Signals. For
`Simplicity, the clock grid tracks are illustrated as a Single
`track; however, it is to be understood that each clock grid
`track may actually comprise any number of individual tracks
`for each distinct clock in the clock grid.
`Once the power and clock grids are set up, the block
`designers then plan 108 the locations of Signal ports in
`coordination with other block designers So as to avoid
`blocking any inter-block signals. The communication with
`other block designers allows planning of the respective
`blocks taking into consideration possible routing conflicts
`with other blocks. This early planning allows better place
`ment of Signal ports in order to avoid inter-block signal
`routing conflicts due to insufficient routing resources.
`The block designers determine actual block port locations
`and areas of any M4, M5, and M6 metal required for
`intra-block routing. The port locations and associated intra
`block metal areas are reserved 110 for the blocks. FIG. 4 is
`a top view of the layout of IC 10 illustrating functional
`blocks 20a-20f overlaid by the reserved over-the-block
`metal M4 areas after the blocks have been designed in
`accordance with the guidelines established in Step 102. AS
`illustrated, functional block A 20a requires approximately
`30% of the over-the-block M4 metal, shown at 24a. Func
`tional block B 20b requires approximately 20% of the
`over-the-block M4 metal; functional block C 20c requires
`100% of the over-the-block M4 metal, functional block D
`20d requires approximately 40% of the over-the-block M4
`metal; and functional block E 20e requires approximately
`20% of the over-the-block M4 metal. The flexibility offered
`by allowing different percentage usage of metal for each
`
`Page 10 of 11
`
`

`

`US 6,397.375 B1
`
`S
`block thereby allows the unused over-the-block metal in
`each block to be used for global inter-block routing.
`FIG. 7 is a perspective view of the same portion of IC 10
`of FIGS. 5 and 6 illustrating the reserved tracks areas for
`over-the-block intra-block routing for the underlying func
`tional block. In the illustrative example (FIG. 7), the intra
`block routing in the upper layerS is reserved on trackS 42a
`and 42b of M6. Intra-block signals are routed along tracks
`42a, 42b, and connect respectively to M5 tracks 52a, 52b,
`which connect to M4 track 64a. Track 64b of layer M4 is
`also reserved for use by functional block 20a.
`Once the block port locations and areas reserved for any
`M4, M5, and M6 metal required for intra-block routing is
`established, the global inter-block Signals are then pre
`routed 112 (FIG. 3) using metal in M4, M5 and M6 that is
`not reserved for the power grid, clock grid, or functional
`blocks. In the illustrative embodiment, pre-routing is per
`formed manually using a floorplanning tool Such as IC
`Master manufactured by Cadence Corp.
`FIG. 8 is a perspective view of the same portion of IC 10
`of FIGS. 5, and 7 illustrating the reserved metal for the
`power grid, clock grid, and over-the-block intra-block rout
`ing for the underlying functional block. The remaining
`unused track areas are available for use for global routing.
`In the illustrative example, all of tracks 46a-46d along with
`portions of tracks 42a-42b, 44a in M6, all of tracks 56a-56g
`along with portions of 52a-52b, 54a–54b in M5, and all of
`tracks 66a-66e along with portions of tracks 62a-62b, 64a
`in M4 are available for inter-block routing.
`During the pre-route process, if any nets are encountered
`114 that are problematic in terms of timing or inability to
`route (due to signal congestion in certain areas), the signal
`port locations and placement of Sub-blocks within the blockS
`are altered 116, taking into account the existing pre-routes,
`to achieve better Signal performance and/or a simpler rout
`ing Solution. The pre-route Step and port and/or Sub-block
`relocation Step often results in the identification of changes
`that can be made that an automated router tool might not be
`able to identify.
`With the changed signal port locations and Sub-block
`placement within the blocks, the process is repeated until no
`unroutable inter-block interconnects are encountered and all
`nets result in Satisfactory performance.
`It will be appreciated by the above detailed description
`that the present invention enables advantages in efficiency
`over the prior art. The communication between block
`designers as to the block routing requirements facilitates
`better placement of Sub-blocks and Signal ports. This results
`in more efficient use of over-the-block routing metal, as well
`as facilitates the ability to create higher density blocks. In
`addition, the allowance of multi-use tracks in over-the-block
`routing results in less unused metal and therefore also allows
`higher density blockS.
`Although the invention has been described in terms of the
`illustrative embodiments, it will be appreciated by those
`skilled in the art that various changes and modifications may
`be made to the illustrative embodiments without departing
`from the spirit or scope of the invention. It is intended that
`the Scope of the invention not be limited in any way to the
`illustrative embodiment shown and described but that the
`invention be limited only by the claims appended hereto.
`What is claimed is:
`1. A method for managing metal resources during over
`the-block routing of an integrated circuit, Said integrated
`circuit comprising a Silicon layer partitioned into and imple
`menting a plurality of functional blocks, and a plurality of
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`metal layers layered over Said Silicon layer, Said method
`comprising the Steps of:
`allocating a percent usage of over-the-block metal over
`each of Said functional blocks in each of Said metal
`layerS for intra-block routing, Said percent usage allo
`cated for intra-block routing being different between at
`least two of said plurality of functional blocks;
`reserving areas of Said over-the-block metal on each of
`Said metal layers for routing a power grid;
`reserving areas of Said over-the-block metal on each of
`Said metal layers for routing a clock grid;
`coordinating, among Said plurality of functional blocks,
`locations of Signal ports of Said functional blockS So as
`to avoid blocking any inter-block signals,
`reserving areas of Said over-the-block metal on each of
`Said metal layers for Said Signal ports and for routing
`intra-block signals,
`prerouting Said inter-block Signals, allowing inter-block
`routing in Said over-the-block metal on each of Said
`metal layers but avoiding Said reserved areas for Said
`power grid, Said clock grid, Said Signal ports and Said
`intra-block signals.
`2. The method of claim 1, further comprising:
`determining better port locations and internal Sub-block
`placement based on results of Said pre-routing Step if
`Said pre-routing Step results in an unroutable net or a
`net with unsatisfactory timing.
`3. An integrated circuit, comprising:
`a Silicon layer implementing a plurality of functional
`blocks;
`a plurality of metal layers layered over Said Silicon layer,
`each layer comprising a plurality of metal tracks,
`wherein:
`portions of a first Set of Said plurality of tracks are
`allocated to and comprise over-the-block intra-block
`routes,
`portions of Said first Set of Said plurality of tracks are
`allocated to and comprise over-the-block inter-block
`routes,
`Said portions of Said first Set of Said plurality of tracks
`allocated to Said over-the-block intra-block routes
`being different between at least two of said plurality
`of functional blocks.
`4. An integrated circuit in accordance with claim 3,
`further comprising:
`a Second set of Said plurality of tracks comprising a power
`grid.
`5. An integrated circuit in accordance with claim 3,
`further comprising:
`a third set of Said plurality of tracks comprising a clock
`grid.
`6. An integrated circuit in accordance with claim 5,
`wherein:
`portions of Said third Set of Said plurality of tracks
`comprise over-the-block intra-block routes.
`7. An integrated circuit in accordance with claim 6,
`wherein:
`portions of Said third Set of Said plurality of tracks
`comprise over-the-block inter-block routes.
`8. An integrated circuit in accordance with claim 5,
`wherein:
`portions of Said third Set of Said plurality of tracks
`comprise over-the-block inter-block routes.
`
`k
`
`k
`
`k
`
`k
`
`k
`
`Page 11 of 11
`
`