Petitioner
`Siemens Industry Software, Inc.
`IPR2022-01213 – U.S. Patent No. 8,234,614
`(Claims 1-4, 12-13, 16-19)
`Andrew M. Mason; Cameron D. Clawson
`October 18, 2022
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`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
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`Siemens Industry Software, Inc.
`IPR2022-01213 – U.S. Patent No. 8,234,614
`(Claims 1-4, 12-13, 16-19)
`Andrew M. Mason; Cameron D. Clawson
`October 18, 2022
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`Grounds
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`2
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`Petition (Paper 1), 2
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`Primary Issues in Dispute
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`Primary Issues – Ground 1 (Block + Mehrotra)
`Claims 1, 12, 16 –
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`1. Whether Mehrotra discloses routing a subset’s global nets
`“in isolation of” / “without reference to” other global nets in the subset
`
`2. Whether Mehrotra teaches identifying subsets of global nets
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`3. Whether a POSITA would have combined Block and Mehrotra
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`Claims 4, 19 –
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`4. Whether Mehrotra teaches issuing each global net to a thread
`because the thread is available
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`4
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`Primary Issues – Ground 2 (Andreev + Sherwani)
`Claims 1, 12, 16 –
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`1. Whether the combination routes a subset’s global nets
`“in isolation of” / “without reference to” other global nets in the subset
`
`2. Whether Andreev teaches identifying subsets of global nets
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`3. Whether a POSITA would have combined Sherwani and Andreev
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`Claims 4, 19 –
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`4. Whether Andreev teaches issuing each global net to a thread
`because the thread is available
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`5
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`Prosecution History
`Prosecution History
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`Klarquist
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`Prosecution History
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`7
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`Office Action, November 14, 2011 (EX1002, 44)
`(cited in Petition (Paper 1) at 9)
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`Prosecution History
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`(Currently Amended) A method of routing a semiconductor chip's global
`1.
`nets, comprising:
`ranking said semiconductor chip's global nets, wherein said ranking includes at
`least one of the following:
`ranking power/ground nets over clock signal nets;
`ranking power/ground nets over timing/slew critical nets;
`ranking clock signal nets over timing/slew critical nets;
`ranking shorter length and lower fan-out nets over longer length and
`higher fan-out nets;
`identifying a subset of said global nets;
`routing said subset of global nets using multiple threads, each of said global nets
`within said subset routed by one of said threads in isolation of said subset’s
`other global nets;
`identifying a second subset of said global nets;
`routing said second subset of global nets using said multiple threads, each of
`said global nets within said second subset routed by one of said threads in
`isolation of said second subset's other global nets but in respect of the
`routes of said first subset of global nets.
`Claim Amendment, March 12, 2012 (EX1002, 25-26)
`(cited in Petition (Paper 1) at 9)
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`8
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`Claim Construction
`Claim Construction
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`Klarquist
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`Agreed Construction – “global nets”
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`Petition (Paper 1), 14
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`10
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`Tentative Construction – “routed … in isolation”
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`Term/Phrase
`“each of said global nets within said
`second subset routed by one of said
`threads in isolation of said second
`subset’s other global nets but in
`respect of the routes of said subset of
`global nets” (all asserted claims)
`
`Synopsys Litigation Construction
`each global net of the second subset is
`independently routed by a respective
`thread, without reference to the routing
`of any other net within the second
`subset and where the routing is in
`respect of the routes of said [first]
`subset of global nets
`
`EX1009, 11-12; EX1010, 10; EX1012,
`1.
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`Court’s Tentative Construction
`Each global net of the second subset is
`independently routed by a respective
`thread, where the threads routing nets
`of the second subset do not
`communicate routing information with
`one another, and the resulting routing
`does not conflict with routings of the
`first subset of global nets
`EX1011, 2.
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`Petition (Paper 1), 15
`(filed July 14, 2021) (footnote omitted)
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`11
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`D. Ct. Construction – “routed … in isolation”
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`Term
`“Each of said global nets within said
`second subset routed by one of said
`threads in isolation of said second
`subset’s other global nets but in
`respect of the routes of said subset of
`global nets”
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`Court’s Ruling
`Each global net of the second subset is
`independently routed by a respective
`thread, without reference to the routing
`of any other net within the second
`subset, and the resulting routing does
`not conflict with routings of the first
`subset of global nets
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`District Court Markman Order, Sept. 27, 2021 (EX2001, 13)
`(cited in Reply (Paper 24) at 3)
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`12
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`Ground 1 – Mehrotra and Block
`Mehrotra discloses routing global nets
`“without reference to” other global nets
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`
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`“in isolation of … “ / “without reference to ...”
`is a negative claim limitation
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`Term
`“Each of said global nets within said
`second subset routed by one of said
`threads in isolation of said second
`subset’s other global nets but in
`respect of the routes of said subset of
`global nets”
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`Court’s Ruling
`Each global net of the second subset is
`independently routed by a respective
`thread, without reference to the routing
`of any other net within the second
`subset, and the resulting routing does
`not conflict with routings of the first
`subset of global nets
`EX2001, 13 (highlighting added)
`(cited in Reply (Paper 24) at 3)
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`Negative limitation: “[D]ynamically accepting … co-processor[s]
`… without any communication with the controller.”
`Juniper Nets., Inc. v. Swarm Tech. LLC, IPR2022-00141,
`Paper 14 at 37 (PTAB May 16, 2022) (highlighting added)
`(citing AC Techs., S.A. v. Amazon.com, Inc., 912 F.3d 1358, 1367 (Fed. Cir. 2019))
`(cited in Reply (Paper 24) at 5)
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`14
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`“in isolation of … “ / “without reference to ...”
`is a negative claim limitation
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`A negative claim limitation “defines the claimed subject matter by
`what it is not rather than by what it is.”
`Teradata Corp. v. SAP SE, IPR2020-00943, Paper 12 at 48 (PTAB Nov. 25, 2020)
`(cited in Reply (Paper 24) at 4)
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`“[A] negative limitation requiring the absence of an element…”
`Palo Alto Nets., Inc. v. Juniper Nets., Inc., IPR2013-00466, Paper 17 at 18
`(PTAB Jan. 28, 2014) (cited in Reply (Paper 24) at 4-5)
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`15
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`The Petition relies on the Mehrotra embodiment of Figs. 9 & 10
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`Mehrotra (EX1004), [0092-93] (highlighting added);
`see also id., at [0094-102]
`(cited in Petition (Paper 1) at 33-42)
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`16
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`Mehrotra (EX1004), Fig. 9 (annotated)
`(cited in Petition (Paper 1) at 29-30, 34-42)
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`Mehrotra (EX1004), Fig. 10
`(cited in Petition (Paper 1) at 34, 37-38, 41)
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`Mehrotra’s discloses “various strategies” related to net routing
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`17
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`Mehrotra (EX1004), Abstract (highlighting added)
`(cited in Petition (Paper 1), 27)
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`Patent Owner focuses on Mehrotra’s “cost matrix,”
`which relates only to the embodiment of Fig. 1B
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`Mehrotra (EX1004), [0042-43]
`(highlighting added)
`(cited in Patent Owner Response (Paper 22), 22-23)
`18
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`Mehrotra (EX1004), Fig. 1B
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`Mehrotra does not require using routing information of other
`nets within a routed subset of nets
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`“Mehrotra nowhere discusses the cited ‘cost matrix’ with regard to its parallel processing routing
`scheme. . . . Accordingly, a POSITA reading Mehrotra would not consider it as disclosing that its ‘cost
`matrix’ is utilized during Mehrotra’s parallel routing, or that nets routed during a parallel processing
`period take into account any cost matrix associated with other nets belonging to the same subset.”
`Robins Reply Decl. (EX1019), ¶9 (highlighting added)
`(cited in Reply (Paper 24) at 6-7)
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`“Mehrotra provides no disclosure that the routing of nets within an area designated to be processed
`(e.g. in Area 92 in Fig. 9) during a given parallel processing period references any routing information
`associated with the other nets within that area routed during the same processing period.”
`Robins Reply Decl. (EX1019), ¶10
`(cited in Reply (Paper 24) at 7)
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`19
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`Ground 1 – Mehrotra and Block
`Mehrotra identifies subsets of global nets
`when routing its areas of nets
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`Mehrotra identifies a first subset of global nets
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`First Subset of Global Nets:
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`21
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`Mehrotra (EX1004), Fig. 9 (annotated)
`(cited in Robins Decl. (Ex.1003), ¶¶ 117-122;
`Petition, 33, 35-37)
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`Mehrotra identifies a second subset of global nets
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`Second Subset of Global Nets:
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`22
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`Mehrotra (EX1004), Fig. 9 (annotated)
`(cited in Robins Decl. (Ex.1003), ¶¶ 129-135;
`Petition, 37-42)
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`Mehrotra identifies subsets of global nets
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`“Mehrotra discloses identifying a first subset of global nets in the form of traces and
`subtraces contained within areas 92 and 96 as depicted in Fig. 9 to be processed
`during a first parallel processing period. Mehrotra further discloses identifying a
`second subset of global nets in the form of traces and subraces contained within areas
`94 and 98. “Step 1002 designates areas 94 and 98 to be processed during a second
`parallel processing period. . . .” Then, “[s]tep 1005 performs route searches for traces
`and subtraces in areas 94 and 98 simultaneously.” Id., [0102]. Therefore, Mehrotra
`identifies a second subset of the global nets to be routed. Without first identifying
`those nets, Mehrotra would be unable out [sic] to route those nets as disclosed in step
`1005 of Fig. 10.”
`
`Robins Decl. (EX1003), ¶¶ 130-131 (highlighting added)
`(citing Mehrotra (EX1004), [0102])
`(cited in Petition (Paper 1) at 37-38)
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`23
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`Global nets within areas to be routed are subsets of global nets
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`“Simply stated, without first identifying nets to be routed within an area, routing
`those nets would be impossible, and Synopsys provides no explanation of how a
`net could be routed without first identifying that net. By way of example, in order
`to read a book, one must first identify which book they wish to read. In other
`words, without first identifying a book, one would not be able to read that book.
`Likewise, in Mehrotra’s routing system, routing nets by a processor would be
`impossible without first identifying the nets to be routed.”
`
`Robins Reply Decl. (EX1019), ¶12 (highlighting added)
`(cited in Reply (Paper 24) at 8)
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`24
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`Ground 1 – Mehrotra and Block
`Nets routed by Mehrotra
`are global nets
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`Mehrotra discloses routing undivided global nets
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`Mehrotra (EX1004), [0100] (highlighting added)
`(cited in Reply (Paper 24) at 10)
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`26
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`Mehrotra (EX1004), Fig. 9 (annotated)
`(cited in Reply (Paper 24) at 9)
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`Mehrotra (EX1004), Fig. 10 (highlighting added)
`(cited in Petition (Paper 1) at 34, 37-38, 41)
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`Mehrotra discloses routing undivided global nets
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`“Moreover, as shown in annotated Fig. 9, above, designated areas for
`parallel processing also contain undivided global nets, as shown by the
`example of the trace labelled 97, in addition to other subtraces, which are
`themselves global nets. Ex. 1004, Fig. 9, ¶ [0100]. Therefore, a POSITA
`would understand that routing the given areas of a chip using Mehrotra’s
`parallel processing methods would also involve identifying and routing
`undivided global nets in addition to global nets that are subtraces resulting
`from the dividing process.”
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`Robins Reply Decl. (EX1019), ¶15 (highlighting added)
`(see Reply (Paper 24) at 10)
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`27
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`Mehrotra’s subtraces are global nets
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`Petition (Paper 1), 14
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`28
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`Mehrotra (EX1004), Fig. 9 (annotated)
`(cited in Petition (Paper 1) at 33-37)
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`Mehrotra’s subtraces are global nets
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`“As shown in Fig. 9 of Mehrotra, reproduced below and highlighting the traces
`contained in Areas 92 and 96, the highlighted subtraces cross multiple tiles of the
`chip as indicated by gridlines 6 and 8. Ex. 1004, Fig. 9. Therefore, Mehrotra’s
`subtraces are indeed global nets.”
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`Robins Reply Decl. (EX1019), ¶14
`(cited in Reply (Paper 24) at 8-9)
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`29
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`Subtraces are treated as nets
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`Andreev (EX1006), 19:8-10 (emphasis added)
`(cited in Reply (Paper 24) at 24)
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`30
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`Ground 1 – Mehrotra and Block
`Independent claims do not require
`parallel routing of power or clock nets
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`Claims do not require parallel routing of power or clock nets
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`“Claim 1 first recites ranking global nets (“ranking said semiconductor chip’s
`global nets . . .”)—without mentioning multiple threads—and then recites
`identifying and routing subsets of global nets using multiple threads. . . . A
`POSITA would not read the claims of the ’614 Patent to require identified
`subsets to include any specific portion of the chip’s global nets, let alone that
`the subsets to be routed in parallel must contain power nets or clock nets.”
`Robins Reply Decl. (EX1019), ¶16 (highlighting added)
`(see Reply (Paper 24) at 10-11)
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`32
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`Claims do not require parallel routing of power or clock nets
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`ranking global nets
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`identifying and
`routing subsets
`of global nets
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`33
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`’614 patent (EX1001, 8:51-9:5), claim 1 (annotated)
`(cited in Robins Reply Decl. (EX1019), ¶ 16;
`Reply (Paper 24) at 10-11)
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`Claims do not require parallel routing of power or clock nets
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`34
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`Robins Deposition, Sept. 1, 2022 (EX2023), 19:16-20:7
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`Ground 1 – Mehrotra and Block
`Block teaches ranking
`power and ground nets over
`other signal nets
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`Establishing power and clock grids constitutes routing
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`Block FIG. 3 at step 102 shows how the power nets are routed first, as part
`of establishing the power grid. At this step, the layout of the power grid,
`including power and ground lines, is established using tracks located on
`specific metal layers of the circuit. EX1005, 4:1-23. “After establishing the
`layout of the power grid, the layout of the clock grid is then established 106
`(FIG. 3).” Id. 4:24-25. A POSITA would have understood that this involved
`establishing routes for the clock signal nets in the design, as it was well-
`known that the clock grid corresponded to the clock net and provided clock
`signals throughout the design. In other words, a POSITA would know that
`“clock grid” refers to the clock net, which could be implemented as a tree, a
`mesh, or some other topology, and that clock grid / net should be
`established (i.e. routed) before less critical nets.
`Robins Decl. (EX1003), ¶112 (highlighting added)
`(cited in Petition (Paper 1) at 32-33)
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`Block ranks power and clock grids over other signal nets
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`EX1005, Fig. 3 (annotated)
`(cited in Robins Reply Decl.
`(EX1019), ¶17;
`cited in Reply (Paper 24) at 13)
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`37
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`Block ranks power and clock grids over other signal nets
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`Robins Deposition, Sept. 1, 2022 (EX2023), 27:10-20
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`38
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`Ground 1 – Mehrotra and Block
`Mehrotra teaches issuing
`nets to threads because
`they are available
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`
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`Mehrotra teaches making additional threads available for
`routing and issuing nets to such threads as a result
`“[A]ny number of areas may be routed in parallel in a given processing period.”
`Mehrotra (EX1004), [0098]
`(cited in Petition (Paper 1) at 45)
`
`“The POSITA would therefore understand that the number of areas that Mehrotra can process in
`parallel is limited by the total number of processors (i.e., with one processor being assigned to each
`area.).”
`
`Patent Owner Response (Paper 22) at 32
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`“A POSITA would find it obvious to utilize additional processors, as they become available, in order
`to route a corresponding additional number of areas of a circuit in parallel, as this would decrease
`the overall processing time to route the nets within those areas.”
`
`Robins Decl. (EX1003), ¶154
`(cited in Petition (Paper 1) at 46)
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`40
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`Ground 2 – Andreev and Sherwani
`Routing Andreev’s nets in isolation
`would have been obvious to a POSITA
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`
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`Routing Andreev’s subsets of nets in isolation
`would have been obvious to a POSITA
`In addition, a POSITA would find it to be a simple design choice
`to have nets belonging to a subset and processed in parallel to
`be routed without reference to the routing of other nets within the
`same subset. For example, each such net would be routed
`based on occupancies stored prior to processing the subset. A
`POSITA would make such a design choice, for example, in order
`to increase processing speeds and thereby reduce the design
`time through the use of parallelism, while still avoiding potential
`concurrent access conflicts that naturally arise in any parallel
`processing system (i.e. when multiple parallel processes try to
`simultaneously modify the same data).
`Robins Decl., July 13, 2021 (EX1003), ¶192
`(cited in Petition (Paper 1) at 61-62)
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`42
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`Patent Owner’s District Court expert testimony supports
`that it was obvious to route nets in isolation
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`Carley Deposition, Apr. 28, 2021 (EX1020), 22:21-23:6
`(cited in Reply (Paper 24) at 21)
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`43
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`Ground 2 – Andreev and Sherwani
`Andreev teaches identifying
`subsets of global nets
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`
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`Andreev identifies a first subset of global nets
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`First Subset of Global Nets:
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`45
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`Andreev (EX1006), Fig. 23A (annotated)
`(cited by Robins Decl. (EX1003), ¶¶ 184-190;
`Petition (Paper 1) at 57-61)
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`Andreev identifies a second subset of global nets
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`Second Subset of Global Nets:
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`46
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`Andreev (EX1006), Fig. 23A (annotated)
`(cited by Robins Decl. (EX1003), ¶¶ 195-202;
`Petition (Paper 1) at 62-66)
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`Andreev identifies subsets of global nets
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`“Under the described method of Andreev the four highlighted quadrants shown
`below would be processed in parallel (assuming that four processors are
`available for routing and at least one relevant net is contained within each
`quadrant) to route any net with a characteristic larger than 1/8 and that is
`completely contained within one of the four quadrants. These nets correspond
`to a second subset of global nets and a POSITA would recognize that clearly
`such nets must necessarily be identified before they can be routed.”
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`Robins Decl. (EX1003), ¶¶ 197-98 (highlighting)
`(cited in Petition (Paper 1) at 62-63)
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`47
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`Ground 2 – Andreev and Sherwani
`Nets routed by Andreev
`are global nets
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`Andreev discloses routing undivided global nets
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`“As Andreev admits, this partitioning applies only to a “small number of nets” ([Ex. 1006],
`8:5-7) and therefore the remaining majority of global nets are maintained and routed as
`undivided nets. Nothing in Andreev’s description of its parallel routing process indicates to
`a POSITA that it applies only to partitioned subnets. Ex. 1006, 24:64-26:36. Instead, in
`describing its parallel routing process, Andreev discusses nets in general. See e.g., id.,
`26:8-11 (“For each net we calculate the two quotients . . . .”) A POSITA would understand
`that the parallel routing process of Andreev applies to undivided nets as well as partitioned
`subnets in order to achieve the efficiency improvements provided by parallel processing to
`all such routed nets.”
`
`Robins Reply Decl. (EX1019), ¶31 (emphasis added)
`(cited in Reply (Paper 24) at 23-24)
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`49
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`Subnets routed by Andreev are global nets
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`Andreev (EX1006), 8:11-14 (highlighting added)
`(cited in Reply (Paper 24) at 23)
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`Andreev (EX1006), 19:8-10 (highlighting added)
`(cited in Reply (Paper 24) at 24)
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`50
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`Ground 2 – Andreev and Sherwani
`Independent claims do not require
`parallel routing of power or clock nets
`
`
`
`Claims do not require parallel routing of power or clock nets
`
`“Claim 1 first recites ranking global nets (“ranking said semiconductor chip’s
`global nets . . .”)—without mentioning multiple threads—and then recites
`identifying and routing subsets of global nets using multiple threads. . . . A
`POSITA would not read the claims of the ’614 Patent to require identified
`subsets to include any specific portion of the chip’s global nets, let alone that
`the subsets to be routed in parallel must contain power nets or clock nets.”
`Robins Reply Decl. (EX1019), ¶16, see also ¶32
`(see Reply (Paper 24) at 10-11, 24-25)
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`52
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`Claims do not require parallel routing of power or clock nets
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`ranking global nets
`
`identifying and
`routing subsets
`of global nets
`
`53
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`’614 patent (EX1001, 8:51-9:5), claim 1 (annotated)
`(cited in Robins Reply Decl. (EX1019), ¶¶ 16, 32;
`Reply (Paper 24) at 24-25)
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`Claims do not require parallel routing of power or clock nets
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`54
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`Robins Deposition, Sept. 1, 2022 (EX2023), 19:16-20:7
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`Ground 2 – Andreev and Sherwani
`A POSITA would have been motivated
`to combine the cited teachings of
`Sherwani with Andreev
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`A POSITA had motivation to implement
`the relied-on teachings of Sherwani
`“[N]umerous references recognize Sherwani as a fundamental treatise in
`the field of VLSI design, and a POSITA would therefore look to the
`teachings of Sherwani in the potential designs of VLSI devices. . . . Thus, a
`POSITA would have readily been led to Sherwani’s textbook and would
`have considered the teachings of Sherwani when implementing the
`semiconductor chip design methods of Andreev.”
`
`Robins Decl. (EX1003), ¶ 174
`(cited in Petition (Paper 1) at 49)
`
`“Sherwani teaches the benefits of routing power and ground before clock
`and other signal nets, so that power and ground nets, with their high
`currents, best utilize low resistivity metal layers. Sherwani, 1995 393-394,
`414, 417. A POSITA would therefore have been motivated to implement the
`teaching of Sherwani together with the parallel processing method
`disclosed by Andreev, to also attain the increased processing speeds
`facilitated by Andreev.”
`
`Robins Decl. (EX1003), ¶ 172
`(cited in Petition (Paper 1) at 51-52)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`56
`
`
`
`Ground 2 – Andreev and Sherwani
`Andreev teaches issuing
`nets to threads because
`they are available
`
`
`
`Andreev teaches issuing nets to threads because they are
`available
`
`“[T]he chip also includes definitions of thousands, tens of thousands, or hundreds of
`thousands of nets.”
`
`Andreev (EX1006), 1:25-31
`(cited in Petition (Paper 1), 72)
`
`“As each of the four quadrants is processed be a separate processor, each such processor,
`though working in parallel with the processors assigned to the other quadrants, will
`nonetheless be responsible for processing the many nets contained within that processor’s
`assigned quadrant. Accordingly, a POSITA would understand that each processor is
`capable of routing a single assigned net one at a time, and would route each net within the
`processor’s assigned quadrant in turn, as that processor becomes available.”
`Robins Decl. (EX1003), ¶ 214
`(cited in Petition (Paper 1), 72)
`
`58
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`IPR2021-01213
`Patent 8,234,614
`
`CERTIFICATE OF SERVICE
`IN COMPLIANCE WITH 37 C.F.R. § 42.6(e)(4)
`The undersigned certifies that on October 14, 2022, a complete copy of
`
`EXHIBIT 1021 – PETITIONER’S DEMONSTRATIVES was served on Patent
`
`Owner via electronic mail as follows:
`
`David B. Cochran
`Joseph M. Sauer
`Robert M. Breetz
`Jones Day
`901 Lakeside Avenue
`Cleveland, OH 44114
`Email:
`dcochran@jonesday.com
`jmsauer@jonesday.com
`rbreetz@jonesday.com
`
`Evan M. McLean
`Jones Day
`1755 Embarcadero Road
`Palo Alto, CA 94303
`Email: emclean@jonesday.com
`
`
`
`Joshua R. Nightingale
`Matthew W. Johnson
`Marlee H. Hartenstein
`Jones Day
`500 Grant Street, Suite 4500
`Pittsburgh, PA 15219
`Email: jrnightingale@jonesday.com
`mwjohnson@jonesday.com
`mhartenstein@jonesday.com
`
`
`
`
`
`
`
`By: /Andrew M. Mason/
`Andrew M. Mason, Reg. No. 64,034
`andrew.mason@klarquist.com
`Cameron Clawson, Reg. No. 73,509
`cameron.clawson@klarquist.com
`Todd M. Siegel, Reg. No. 73,232
`todd.siegel@klarquist.com
`Samuel Thacker, Reg No. 78,633
`samuel.thacker@klarquist.com
`KLARQUIST SPARKMAN, LLP
`One World Trade Center, Suite 1600
`121 S.W. Salmon Street
`Portland, Oregon 97204
`
`CERTIFICATE OF SERVICE
`
`
`
`Page 1
`
`
`
`IPR2021-01213
`Patent 8,234,614
`
`Tel: 503-595-5300
`Fax: 503-595-5301
`
`Counsel for Petitioner
`
`
`
`CERTIFICATE OF SERVICE
`
`
`
`Page 2
`
`
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