Petitioner
`Siemens Industry Software Inc.
`IPR2022-01212
`U.S. Patent No. 7,546,567
`(Claims 1-8, 11-20, 23-25)
`
`October 19, 2022
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`Siemens Industry Software Inc.
`IPR2022-01212
`U.S. Patent No. 7,546,567
`(Claims 1-8, 11-20, 23-25)
`
`October 19, 2022
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Grounds
`
`2
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`DI (Paper 11), 9
`
`
`
`’567 Claim 1
`1. A method for generating a clock-tree on an integrated circuit (IC) chip, comprising:
`receiving a placement for a chip layout, where the placement includes a set of
`registers at fixed locations in the chip layout;
`generating, using a computer, a timing criticality profile for the set of registers,
`wherein the timing criticality profile specifies timing criticalities between pairs of registers
`in the set of registers; and
`clustering the set of registers based on the timing criticality profile to create a
`clock-tree for the set of registers, wherein clustering the set of registers involves
`clustering a first pair of registers which has a higher timing criticality between each other
`prior to clustering a second pair of registers which has a lower timing criticality between
`each other;
`wherein clustering registers based on the timing criticality profile facilitates using
`commonly-shared clock paths in the clock-tree to provide clock signals to timing critical
`register pairs.
`
`3
`
`’567 patent (EX1001), claim 1
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Primary Issues – Sano Grounds
`
`1. Whether Sano Emb. 1 generates a clock tree without moving registers
`(claims 1-7, 11-19, and 23-25)
`
`2. Whether Sano Emb. 1 renders obvious computing slack and clock skew
`(claims 2-3 and 14-15)
`
`3. Whether Sano Emb. 1’s clustered registers share clock nets (claims 7 and 19)
`
`4. Whether dependent claims 8 and 20 are obvious over aspects of Sano Emb. 4,
`combined with aspects of Sano Emb. 1
`
`4
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Primary Issues – Cheng-based Grounds
`
`1. Whether Cheng discloses or renders obvious using a timing criticality profile to
`prioritize and address timing violations (claims 1-7, 11-19, and 23-25)
`
`2. Whether clock buffers are clustered in Cheng (claims 5, 17)
`
`3. Whether Cheng’s clustered registers share clock nets (claims 7, 19)
`
`4. Whether Cheng and Sherwani satisfy dependent claims 8 and 20
`
`5
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Generates a Clock Tree
`(claims 1, 14, 25)
`
`
`
`Sano Clock Tree Generation
`
`1. A method for generating a clock-tree on an integrated circuit (IC) chip, comprising:
`receiving a placement for a chip layout, where the placement includes a set of
`registers at fixed locations in the chip layout;
`generating, using a computer, a timing criticality profile for the set of registers,
`wherein the timing criticality profile specifies timing criticalities between pairs of registers
`in the set of registers; and
`clustering the set of registers based on the timing criticality profile to create a
`clock-tree for the set of registers, wherein clustering the set of registers involves
`clustering a first pair of registers which has a higher timing criticality between each other
`prior to clustering a second pair of registers which has a lower timing criticality between
`each other;
`wherein clustering registers based on the timing criticality profile facilitates using
`commonly-shared clock paths in the clock-tree to provide clock signals to timing critical
`register pairs.
`
`7
`
`’567 patent (EX1001), claim 1
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Clock Tree Generation
`
`8
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition (Paper 1), 14
`(citing EX1008, 2; EX1016, 2)
`
`
`
`Sano Clock Tree Generation
`
`Sano (EX1004), 25:64-67 (cited by Petition (Paper 1), 23, 26);
`see also Sano (EX1004), 22:28-30 (cited by Petition (Paper 1), 26)
`
`9
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Sano (EX1004), 19:57-60
`(cited by Petition (Paper 1), 23)
`
`
`
`Sano Clock Tree Generation
`
`Sano (EX1004), 21:11-16
`(cited by Petition (Paper 1), 38; Reply (Paper 22), 2)
`
`10
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Clock Tree Generation
`
`The ‘567 patent:
`
`567 patent (EX1001), 5:5-9 (cited by Petition (Paper 1), 10);
`see also Petition (Paper 1), 12 (“The clock-tree synthesis process …”)
`
`11
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Clock Tree Generation
`
`Patent Owner’s
`declarant agreed that the
`Sano First Embodiment
`produces a clock tree
`
`12
`
`EX1018, 116:16-24 (cited by Reply (Paper 22), 2-3)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`“registers at fixed locations” is a
`negative limitation and Sano discloses
`its first embodiment as a complete
`clock tree generation process that
`does not involve register movement
`(claims 1, 14, 25)
`
`
`
`Sano Clock Tree Generation
`
`1. A method for generating a clock-tree on an integrated circuit (IC) chip, comprising:
`receiving a placement for a chip layout, where the placement includes a set of
`registers at fixed locations in the chip layout;
`generating, using a computer, a timing criticality profile for the set of registers,
`wherein the timing criticality profile specifies timing criticalities between pairs of registers
`in the set of registers; and
`clustering the set of registers based on the timing criticality profile to create a
`clock-tree for the set of registers, wherein clustering the set of registers involves
`clustering a first pair of registers which has a higher timing criticality between each other
`prior to clustering a second pair of registers which has a lower timing criticality between
`each other;
`wherein clustering registers based on the timing criticality profile facilitates using
`commonly-shared clock paths in the clock-tree to provide clock signals to timing critical
`register pairs.
`
`14
`
`’567 patent (EX1001), claim 1
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`“Registers [At/In] Fixed Locations”
`
`District Court’s Construction:
`
`15
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX2001, 9
`(cited by Reply (Paper 22), 3); see also POR (Paper 19), 34
`
`
`
`A negative limitation
`Patent Owner asserts this claim term “is essentially a negative limitation”
`
`16
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`POR (Paper 19), 35
`
`
`
`Sano’s silence satisfies the claim element
`“[A] reference need not state a feature’s absence in order to disclose a negative limitation.”
`AC Techs. S.A. v. Amazon.com, Inc., 912 F.3d 1358, 1367 (Fed. Cir. 2019) (cited by Reply (Paper 22), 4)
`
`The Federal Circuit has affirmed a finding of a negative limitation in a prior art reference
`when “a skilled artisan would recognize that the reference discloses a complete
`formulation” that lacks the negative element.
`Almirall, LLC v. Amneal Pharms. LLC, 28 F.4th 265, 273-74 (Fed. Cir. 2022) (cited by Reply (Paper 22), 4)
`
`“[Negative] limitations may be satisfied by silence in the prior art.”
`Juniper Networks, Inc. v. Swarm Tech. LLC, IPR2022-00141, Paper 14 at 37 (PTAB May 16, 2022)
`(citations omitted) (cited by Reply (Paper 22), 4)
`
`17
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition (Paper 1), 6
`
`
`
`Sano’s first embodiment is silent
`Patent Owner asserts that Sano’s first embodiment is “silent” as to register movement
`
`POR (Paper 19), 35
`
`18
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano’s first embodiment is silent
`
`Patent Owner’s declarant affirmatively testified:
`
`19
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX2019, ¶ 60
`(cited by POR (Paper 19), 35)
`
`
`
`Even if “fixed locations” were not a negative
`limitation, Sano’s first embodiment at least
`renders obvious affirmatively keeping
`registers fixed during clock tree generation
`(claims 1, 14, 25)
`
`
`
`Sano’s First Embodiment, alone, renders obvious
`claims 1-7, 11-19, and 23-25
`“Sano’s first embodiment renders obvious claims 1-7, 11-19, and 23-25.”
`Petition (Paper 1), 25
`
`21
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Reply (Paper 22), 8
`
`
`
`Sano’s First Embodiment, alone, renders obvious
`claims 1-7, 11-19, and 23-25
`
`22
`
`See POR, 35
`(citing Sano (EX1004), 17:20-26:3)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Registers remain fixed during the clock tree generation
`process of Sano’s First Embodiment
`
`Sano (EX1004), FIGs. 8A-8C
`(as annotated by Reply (Paper 22), 6)
`
`23
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Registers remain fixed during the clock tree generation
`process of Sano’s First Embodiment
`
`Sano (1004), Fig. 2
`(cited by Petition (Paper 1), 22)
`(highlighting added)
`
`24
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano’s First Embodiment clusters register pairs based
`on “evaluation value”
`
`Sano (1004), 20:24-29
`(cited by Petition (Paper 1), 35, 48, 50;
`POR (Paper 19), 18)
`(highlighting added)
`
`25
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Registers Remain Fixed
`
`A POSITA would have implemented Sano’s clock tree clustering with registers (FFs) in fixed locations
`
`26
`
`EX1003, ¶ 85 (cited by Petition (Paper 1), 30)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Registers Remain Fixed
`
`A POSITA would have implemented Sano’s clock tree clustering with registers (FFs) in fixed locations
`
`EX1019, ¶ 20
`(cited by Reply (Paper 22), 7)
`
`27
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Registers Remain Fixed
`
`28
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1019, ¶ 21
`(cited by Reply (Paper 22), 7)
`
`
`
`Sano Registers Remain Fixed
`
`29
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1019, ¶ 21
`(cited by Reply (Paper 22), 7)
`
`
`
`Sano Registers Remain Fixed
`
`30
`
`EX1019, ¶ 11
`(cited by EX1019, ¶ 21 (cited by Reply (Paper 22), 7))
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Registers Remain Fixed
`
`31
`
`EX1019, ¶¶ 12-13
`(cited by EX1019, ¶ 21 (cited by Reply (Paper 22), 7))
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Registers Remain Fixed
`
`32
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1019, ¶ 21
`(cited by Reply (Paper 22), 7)
`
`
`
`Sano Computes Timing Slack,
`Or At Least Renders It Obvious To Do So
`(Claims 2, 14)
`
`
`
`Sano Computes Timing Slack
`’567 Claim 2:
`
`2. The method of claim 1, wherein obtaining the timing criticality between a pair of
`registers in the set of registers involves computing a timing slack between the pair
`of registers based on the received placement.
`
`POR (Paper 19), 43
`
`34
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Computes Timing Slack
`
`• Synopsys’s Construction of “timing slack”
`
`POR (Paper 19), 43
`
`35
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Computes Timing Slack
`
`• Synopsys’s Construction of “timing slack”
`
`36
`
`Reply (Paper 22), 9
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Computes Timing Slack
`
`Sano (EX1004), FIG. 7 (cited by Petition (Paper 1), 21, 31)
`(highlighting added)
`
`37
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Computes Timing Slack
`
`38
`
`EX1003, ¶ 90 (cited by Petition (Paper 1), 32 (cross-
`referenced by Petition (Paper 1), 43)) (highlighting added)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Computes Timing Slack
`
`39
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Sano (EX1004), FIGs. 9A-E, as annotated in
`Petition (Paper 1), 44
`
`
`
`Sano relies on the slack values to fix timing violations
`
`40
`
`Sano (EX1004), FIGs. 8A-C
`(cited by Petition (Paper 1), 39) (highlighting added)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Computes Timing Slack
`
`41
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1003, ¶ 90 (cited by Petition (Paper 1), 32-33 (cross-
`referenced by Petition (Paper 1), 43)) (highlighting added)
`
`
`
`Sano Computes Timing Slack
`
`42
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1003, ¶ 105 (cited by Petition (Paper 1),
`44)
`
`
`
`Sano Computes Timing Slack
`
`43
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1003, ¶ 105 (cited by Petition (Paper 1),
`44-45)
`
`
`
`Sano Computes Timing Slack
`
`44
`
`EX1019, ¶ 25
`(cited by Reply (Paper 22), 10)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Computes Clock Skew,
`Or At Least Renders That Obvious
`(Claims 3, 15)
`
`
`
`Sano Computes Clock Skew
`
`• Agreed construction of “clock skew”
`
`46
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition (Paper 1), 15
`
`
`
`Sano Computes Clock Skew
`
`47
`
`EX1019, ¶28
`(cited by Reply (Paper 22), 11)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`In Sano, Registers In A Given Cluster
`Share Clock Nets
`(Claims 7, 19)
`
`
`
`Sano Clustered Registers Share Clock Nets
`
`49
`
`Sano (EX1004), Fig. 3E
`(annotated by Petition (Paper 1), 49)
`(cross-referenced by Petition (Paper 1), 50)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Clustered Registers Share Clock Nets
`
`50
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Reply (Paper 22), 12
`
`
`
`Sano Clustered Registers Share Clock Nets
`Synopsys’s Expert Confirmed
`
`EX1018, 157:6-8
`
`51
`
`EX1018, 157:17 - 158:4
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Clustered Registers Share Clock Nets
`
`• Patent Owner’s Expert Confirmed
`
`52
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1018, 158:12-16
`
`
`
`Sano’s Fourth Embodiment Completes
`The Claimed Clock Tree Generation
`Without Movement Of Registers, Prior To Any
`Alleged Movement Of Registers At S128
`
`
`
`Sano Fourth Embodiment + First Embodiment:
`Clock Tree Generated Without Movement Of Registers
`
`Sano First Embodiment clustering in
`Steps 513-515 …
`Were obvious to use in S124 of
`Fourth Embodiment …
`
`Were obvious to use in S127 of
`Fourth Embodiment …
`
`54
`
`Petition (Paper 1), 51 (annotated)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Fourth Embodiment + First Embodiment:
`Clock Tree Generated Without Movement Of Registers
`
`Sano First Embodiment
`clustering (S513-515)
`obvious to use in S124 of
`Fourth Embodiment
`
`Sano First Embodiment clustering
`(S513-515) obvious to use in
`S127 of Fourth Embodiment
`
`55
`
`Sano (EX1004), Fig. 21 (excerpted and annotated to reflect description of Sano at
`Petition (Paper 1), 52)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Fourth Embodiment + First Embodiment:
`Clock Tree Generated Without Movement Of Registers
`
`Petition (Paper 1), 52
`
`56
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano Embodiment 4:
`Clock Tree Generated Without Movement Of Registers
`
`57
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Sano (EX1004), Fig. 21 (excerpted)
`(as annotated by Petition (Paper 1), 24)
`
`
`
`Sano Embodiment 4:
`Clock Tree Generated Without Movement Of Registers
`
`58
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Sano (EX1004), Figs. 26, 30, 32
`(as annotated by Reply (Paper 22), 16)
`
`
`
`Sano’s “placement restriction area” is used in only its Fourth Embodiment,
`at step S128
`
`…
`
`59
`
`Sano (EX1004), 32:16-42;
`compare with Sano (EX1004),
`12:64-13:12 (cited by Sur-reply,
`1-2, 6, 8 n.1)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Sano FIGs. 38-39 relate to S128 of the fourth embodiment
`
`• Sano Figs. 38-39 correspond to S128 of its fourth embodiment (and are not part
`of the first embodiment)
`
`60
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Sano (EX1004), 15:45-56
`See Sur-reply, 6
`
`
`
`Sano’s Fourth Embodiment Uses
`Geometric-Based Clustering That
`Considers User Constraints
`
`
`
`Sano User Constraints
`• The ‘567 Describes Its Location-Based Clustering As “Conventional”
`
`EX1001, 7:38-42
`(cited by Reply (Paper 22), 18; Petition (Paper 1), 83)
`
`62
`
`EX1001, 7:58-64 (cited by Reply (Paper 22),
`18; Petition (Paper 1), 83)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng-based Grounds
`Cheng-based Grounds
`
`Klarquist
`
`
`
`A POSITA would have naturally implemented
`Cheng to calculate and store timing slack
`information for each register path, and cluster
`registers from highest to lowest priority using
`that timing slack information
`(claims 1-2, 13-14, and 25)
`
`
`
`’567 Claim 1
`1. A method for generating a clock-tree on an integrated circuit (IC) chip, comprising:
`receiving a placement for a chip layout, where the placement includes a set of
`registers at fixed locations in the chip layout;
`generating, using a computer, a timing criticality profile for the set of registers,
`wherein the timing criticality profile specifies timing criticalities between pairs of registers
`in the set of registers; and
`clustering the set of registers based on the timing criticality profile to create a
`clock-tree for the set of registers, wherein clustering the set of registers involves
`clustering a first pair of registers which has a higher timing criticality between each other
`prior to clustering a second pair of registers which has a lower timing criticality between
`each other;
`wherein clustering registers based on the timing criticality profile facilitates using
`commonly-shared clock paths in the clock-tree to provide clock signals to timing critical
`register pairs.
`
`65
`
`’567 patent (EX1001), claim 1
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`“Timing Criticality Profile …” – PO Construction
`
`66
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition (Paper 1), 17
`
`
`
`“Timing Criticality …” – D. Ct. Construction
`
`67
`
`EX2001, 4
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`’567 Claim 2
`2. The method of claim 1, wherein obtaining the timing criticality between a pair of
`registers in the set of registers involves computing a timing slack between the pair
`of registers based on the received placement.
`
`68
`
`’567 patent (EX1001), claim 2
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng discloses to identify timing violations (480) and
`then cluster registers to fix those violations (490)
`
`69
`
`Cheng (EX1005), FIG. 4 (excerpt)
`(as annotated in Petition (Paper 1), 61); see also
`Petition (Paper 1), 64
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng discloses to identify timing violations (480) and
`then cluster registers to fix those violations (490)
`
`• In step 480, the “clock tree is tested for setup time … violations.”
`EX1005, 8:25-30 (quoted by Petition (Paper 1), 68)
`
`• Then, the registers are clustered in Step 490, “in order to correct any setup time
`and/or hold time violations.” EX1005, 8:25-30 (quoted by Petition (Paper 1), 68)
`
`70
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Cheng (EX1005), FIG. 4 (excerpted)
`(as annotated by Petition, 64)
`
`
`
`Cheng discloses to identify timing violations (480) and
`then cluster registers to fix those violations (490)
`
`• “[A] POSITA would have understood that the Cheng timing criticalities (setup
`violation values) needed to be stored somewhere on the computer, such as the
`temporary memory and/or permanent memory shown in FIG. 7.” EX1003, ¶164
`(cited by Petition (paper 1), 69) (citing EX1005, 10:34-38)
`
`71
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng computes timing slack as part of identifying
`timing violations (480)
`
`• “[A] POSITA would have reasonably understood that Cheng computes slack
`values (including skew) as part of testing setup timing violations, using an
`approach mathematically equivalent to that of the ’567 patent, and which
`satisfies Synopsys’s construction of ‘timing slack.’ … if Cheng did not calculate
`specific slack values for each register at step 480 then it would be unable to
`properly evaluate [and address] timing violations at the later step 490.”
`
`EX1019, ¶53 (cited by Reply (Paper 22), 23) (citing Cheng (EX1005), 8:26-27);
`see also Petition (Paper 1), 69 (citing EX1003, 162-64 & 166-67 and explaining why it would have been at least
`obvious to store timing criticality information in a data structure to inter alia correct all the timing violations in step 490)
`
`72
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng’s computed slack values (480) must be stored
`in order to fix the corresponding timing violations (490)
`
`EX1019, ¶55 (cited by Reply (Paper 22), 23-24)
`
`73
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng Step 480 uses the well-known equation for
`analyzing setup timing violations
`
`EX1005, 9:51-52 (cited by Petition (Paper 1),
`64-66)
`
`Which can be rewritten, mathematically as:
`
`Petition (Paper 1), 65-66
`
`74
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng Step 480 uses the well-known equation for
`analyzing setup timing violations
`
`• Max delay 557 = maximum data path delay
`• Period 660 = clock period
`• setup 663 = setup requirement of the receiving flop
`• Skew = clock skew for the register pair.
`Petition (Paper 1), 64-66 (citing inter alia EX1005, 9:25-52; EX1003, ¶154);
`compare with EX1001, 5:44-6:12
`
`75
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng Step 480 uses the well-known equation for
`analyzing setup timing violations
`
`Petition (Paper 1), 64-66 (citing EX1005, 9:51-52)
`
`76
`
`Petition (Paper 1), 67 (showing Cheng (EX1005), FIG. 5 and FIG. 6)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`The Cheng Step 480 equation is mathematically
`equivalent to the well-known “timing slack” of the ‘567
`
`Petition (Paper 1), 64-65 (citing EX1005, 9:51-52)
`
`77
`
`EX1008, 6 (cited by Petition (Paper 1), 17-18); see also POR
`(Paper 19), 43 (highlighting added)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`The Cheng Step 480 equation is mathematically
`equivalent to the well-known “timing slack” of the ‘567
`
`78
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1003, ¶157 (cited by Petition, 66);
`see also EX1019, ¶53-55 (cited by
`Reply (Paper 22), 23)
`
`
`
`Cheng FIG. 5 and ‘567 FIG. 3
`
`79
`
`Reply (Paper 22) 21-22 (discussing Cheng, FIG. 5 and ‘567 patent, FIG. 3)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Patent Owner’s declarant testified that it was known to
`evaluate timing violations by calculating timing slack
`
`EX1018, 31:4-25 (cited by Reply (Paper 22), 23)
`
`80
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`A POSITA would have naturally implemented Cheng to
`prioritize higher priority, i.e., worse violations
`
`EX1019, ¶57 (cited by Reply (Paper 22), 24)
`
`81
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`A POSITA would have naturally implemented Cheng to
`prioritize higher priority, i.e., worse violations
`
`82
`
`EX1019, ¶59 (cited by Reply (Paper 24), 24);
`see also EX1019, ¶58.
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Patent Owner’s declarant testified that “it would be
`natural” to address more serious violations first
`
`83
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1018, 178:12-25
`(cited by Reply (Paper 22), 24)
`
`
`
`Patent Owner’s declarant testified that this well-known
`technique was referred to as a “greedy” approach
`
`84
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1018, 85:14-86:7
`(cited by Reply (Paper 22), 23-
`24)
`
`
`
`The ‘567 patent background described prior art that
`clustered register pairs in order of timing criticality
`
`EX1001, 1:64-67
`(cited by Petition (Paper 1), 71-
`72) (highlighting added)
`
`“[I]t is appropriate to rely on admissions in a patent’s specification
`when assessing whether that patent’s claims would have been
`obvious.”
`Qualcomm Inc. v. Apple Inc., 24 F.4th 1367, 1375 (Fed. Cir. 2022)
`(citations omitted) (cited by Reply (Paper 22), 24-25 n.5)
`
`85
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng discloses clustering clock buffers
`(claims 5/17)
`
`
`
`’567 Claim 5
`5. The method of claim 1, wherein clustering the set of registers based on the
`timing criticality profile to create a clock-tree for the set of registers involves:
`
`clustering the set of registers at a leaf-level to generate a disjoint set of
`leaf-level clusters;
`
`assigning a clock buffer to each of the leaf-level clusters to generate a set
`of clock-buffers; and
`
`clustering the set of clock-buffers to generate a disjoint set of non-leaf
`level clusters.
`
`87
`
`’567 patent (EX1001), claim 5
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng FIG. 5 shows clock buffer clustering
`
`88
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng discloses clustering registers and clock buffers,
`just as shown in Cheng FIG. 5
`
`89
`
`EX1003, ¶191 (cited by Petition (Paper 1), 78)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng renders obvious prioritizing clustering
`based on timing criticalities (timing slack)
`(claims 6/18, depending from claims 5/17)
`
`
`
`’567 Claim 6
`6. The method of claim 5, wherein clustering the set of registers at the leaf-level
`involves:
`prioritizing the pairs of registers based on the associated timing
`criticalities, wherein a more timing critical pair of registers receives a higher
`priority; and
`attempting to assign a pair of registers to the same cluster based on the
`associated priority, thereby substantially maximizing the inclusion of the timing
`critical register pairs into the same clusters.
`
`91
`
`’567 patent (EX1001), claim 6
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng discloses clustered registers as
`sharing clock nets
`(claims 7/19, depending from claims 6/18)
`
`
`
`’567 Claim 7
`7. The method of claim 6, wherein the registers within the same cluster share
`clock-buffers and clock-nets along associated clock paths in the clock-tree.
`
`93
`
`’567 patent (EX1001), claim 7
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng FIG. 5 shows sharing of clock nets and buffers
`
`94
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1005, FIG. 5
`(cited by Petition (Paper 1), 79-80)
`
`
`
`Cheng FIG. 5 shows sharing of clock nets and buffers
`
`95
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Reply (Paper 22), 27
`(annotating EX1005, FIG. 5)
`
`
`
`Cheng FIG. 5 shows sharing of clock nets and buffers
`
`EX1019, ¶ 65
`(cited by Reply (Paper 22), 27)
`
`96
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`The ‘567 patent indicates that sharing of clock paths
`includes sharing of clock nets
`
`EX1001, 5:5-9 (highlighting added) (cited by Reply (Paper 22), 2);
`see also EX1003, ¶60 (explaining how alleged invention provides clock
`path sharing, which includes sharing of clock buffers and clock nets)
`
`97
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Cheng and Sherwani
`Cheng and Sherwani
`
`Klarquist
`
`
`
`’567 Claim 8
`8. The method of claim 6, wherein prior to clustering the set of registers based on
`the timing criticality profile, the method further comprises:
`
`clustering the set of registers using a geometric location-based
`clustering process to obtain a temporary partial-clock-tree, which comprises a
`disjoint set of clusters;
`
`extracting a set of constraints from the set of clusters; and
`
`discarding the temporary partial-clock-tree.
`
`99
`
`’567 patent (EX1001), claim 8
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`A POSITA would have combined Cheng and Sherwani
`
`100
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1003, ¶ 203
`(cited by Petition, 83)
`
`
`
`A POSITA would have combined Cheng and Sherwani
`
`101
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1003, ¶ 205
`(cited by Petition, 83)
`
`
`
`Sherwani clusters based on proximity
`
`102
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1019, ¶ 70
`(cited by Reply (Paper 22), 29); see
`also EX1019, ¶¶ 71-74
`
`
`
`Cheng-Sherwani discards its temporary clock tree
`
`EX1003, ¶ 211
`(cited by Petition, 85)
`
`103
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`IPR2021-01212
`Patent 7,546,567
`
`CERTIFICATE OF SERVICE
`IN COMPLIANCE WITH 37 C.F.R. § 42.6 (e)(4)
`The undersigned certifies that on October 14, 2022, a complete copy of
`
`EXHIBIT 1025 - PETITIONER’S DEMONSTRATIVES was served on Patent
`
`Owner via electronic mail as follows:
`
`David B. Cochran
`Joseph M. Sauer
`Robert M. Breetz
`Jones Day
`901 Lakeside Avenue
`Cleveland, OH 44114
`Email: dcochran@jonesday.com
`jmsauer@jonesday.com
`rbreetz@jonesday.com
`
`Evan M. McLean
`Jones Day
`1755 Embarcadero Road
`Palo Alto, CA 94303
`Email: emclean@jonesday.com
`
`
`
`
`Joshua R. Nightingale
`Matthew W. Johnson
`Marlee H. Hartenstein
`Jones Day
`500 Grant Street, Suite 4500
`Pittsburgh, PA 15219
`Email: jrnightingale@jonesday.com
`mwjohnson@jonesday.com
`mhartenstein@jonesday.com
`
`
`
`
`
`
`By: /Andrew M. Mason/
`Andrew M. Mason, Reg. No. 64,034
`andrew.mason@klarquist.com
`Cameron Clawson, Reg. No. 73,509
`cameron.clawson@klarquist.com
`Todd M. Siegel, Reg. No. 73,232
`todd.siegel@klarquist.com
`Samuel Thacker, Reg No. 78,633
`samuel.thacker@klarquist.com
`KLARQUIST SPARKMAN, LLP
`One World Trade Center, Suite 1600
`121 S.W. Salmon Street
`Portland, Oregon 97204
`Tel: 503-595-5300
`
`CERTIFICATE OF SERVICE
`
`
`
`Page 1
`
`
`
`IPR2021-01212
`Patent 7,546,567
`
`Fax: 503-595-5301
`
`Counsel for Petitioner
`
`
`
`CERTIFICATE OF SERVICE
`
`
`
`Page 2
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
