synqr.book Page i Thursday, May 23, 2002 4:42 PM
`
`Synthesis
`Quick Reference
`
`Version 2002.05, June 2002
`
`Comments?
`E-mail your comments about Synopsys
`documentation to doc@synopsys.com
`
`synoPSYS"
`
`

`

`synqr.book Page ii Thursday, May 23, 2002 4:42 PM
`
`Copyright Notice and Proprietary Information
`Copyright  2002 Synopsys, Inc. All rights reserved. This software and documentation
`contain confidential and proprietary information that is the property of Synopsys, Inc. The
`software and documentation are furnished under a license agreement and may be used or
`copied only in accordance with the terms of the license agreement. No part of the software
`and documentation may be reproduced, transmitted, or translated, in any form or by any
`means, electronic, mechanical, manual, optical, or otherwise, without prior written
`permission of Synopsys, Inc., or as expressly provided by the license agreement.
`Right to Copy Documentation
`The license agreement with Synopsys permits licensee to make copies of the
`documentation for its internal use only. Each copy shall include all copyrights,
`trademarks, service marks, and proprietary rights notices, if any. Licensee must
`assign sequential numbers to all copies. These copies shall contain the following
`legend on the cover page:
`“This document is duplicated with the permission of Synopsys,
`Inc., for the exclusive use of
`__________________________________________ and its
`employees. This is copy number __________.”
`Destination Control Statement
`All technical data contained in this publication is subject to the export control laws
`of the United States of America. Disclosure to nationals of other countries
`contrary to United States law is prohibited. It is the reader’s responsibility to
`determine the applicable regulations and to comply with them.
`Disclaimer
`SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY
`KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,
`INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
`MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
`Registered Trademarks (®)
`Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, CoCentric,
`COSSAP, CSim, DelayMill, DesignPower, DesignSource, DesignWare, Eaglei,
`EPIC, Formality, in-Sync, LEDA, ModelAccess, ModelTools, PathBlazer, PathMill,
`PowerArc, PowerMill, PrimeTime, RailMill, SmartLogic, SmartModel, SmartModels,
`SNUG, Solv-It, SolvNet, Stream Driven Simulator, System Compiler, TestBench
`Manager, TetraMAX, TimeMill, and VERA are registered trademarks of Synopsys,
`Inc.
`Trademarks (™)
`BCView, Behavioral Compiler, BOA, BRT, Cedar, ClockTree Compiler, DC Expert,
`DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design
`Analyzer, Design Compiler, DesignSphere, DesignTime, Direct RTL, Direct Silicon
`Access, DW8051, DWPCI, ECL Compiler, ECO Compiler, ExpressModel, Floorplan
`Manager, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, HDL
`Advisor, HDL Compiler, Integrator, Interactive Waveform Viewer, Liberty, Library
`Compiler, ModelSource, Module Compiler, MS-3200, MS-3400, NanoSim,
`OpenVera, Physical Compiler, Power Compiler, PowerCODE, PowerGate,
`ProFPGA, Protocol Compiler, RoadRunner, Route Compiler, RTL Analyzer,
`Schematic Compiler, Scirocco, Shadow Debugger, SmartLicense, SmartModel
`Library, Source-Level Design, SWIFT, Synopsys EagleV, SystemC, SystemC
`(logo), Test Compiler, TestGen, TimeTracker, Timing Annotator, Trace-On-Demand,
`VCS, VCS Express, VCSi, VHDL Compiler, VHDL System Simulator, VirSim, and
`VMC are trademarks of Synopsys, Inc.
`Service Marks (SM)
`DesignSphere, SVP Café, and TAP-in are trademarks of Synopsys, Inc.
`
`Printed in the U.S.A.
`
`Document Order Number: 13482-000 MA
`Synthesis Quick Reference, v2002.05
`
`ii
`
`

`

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`
`Contents
`
`Man Page Viewing and Printing Instructions . . . . . . . . . 1
`
`User Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
`
`Synthesis Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
`
`Synthesis Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
`
`iii
`
`

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`
`iv
`
`

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`
`Man Page Viewing and Printing
`Instructions
`The following sections describe how to set up your
`UNIX environment so you can view and print man pages.
`
`Setting Up the UNIX Environment
`Edit your .cshrc file to contain these lines:
`setenv SYN_MAN_DIR synopsys_root/doc/syn/man
`setenv MANPATH ${MANPATH}:${SYN_MAN_DIR}
`SYN_MAN_DIR is a variable that contains the path to
`the man page directories, and synopsys_root represents
`the specific path to the Synopsys synthesis software
`directory at your site.
`
`Viewing Man Pages From UNIX
`Command
`% man command_name
`Variable
`% man variable_name
`Variable group
`% man variable_group_name
`All attributes
`% man attributes
`Attribute group
`% man attribute_group_name
`Error, warning, or information message
`% aman message_id
`
`Viewing Man Pages From dc_shell
`Command
`dc_shell> man command_name
`Variable
`dc_shell> man variable_name
`
`Man Page Viewing and Printing Instructions 1
`
`

`

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`
`Variable group
`dc_shell> man variable_group_name
`All attributes
`dc_shell> man attributes
`Attribute group
`dc_shell> man attribute_group_name
`Error, warning, or information message
`dc_shell> man message_id
`
`Printing Man Pages From UNIX
`User command
`% lpr -t -P printer_name \
` $SYN_MAN_DIR/fmt1/command_name.1
`Synopsys command
`% lpr -t -P printer_name \
` $SYN_MAN_DIR/fmt2/command_name.2
`Variable
`% lpr -t -P printer_name \
` $SYN_MAN_DIR/fmt3/variable_name.3
`Variable group
`% lpr -t -P printer_name \
` $SYN_MAN_DIR/fmt3/variable_group_name.3
`All attributes
`% lpr -t -P printer_name \
` $SYN_MAN_DIR/fmt3/attributes.3
`Attribute group
`% lpr -t -P printer_name \
` $SYN_MAN_DIR/fmt3/attribute_group_name.3
`You cannot print error, warning, or information message
`man pages from UNIX.
`
`Printing Man Pages From dc_shell
`You cannot print man pages from dc_shell.
`
`2 Man Page Viewing and Printing Instructions
`
`

`

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`
`User Commands
`Invoke user commands from a UNIX shell.
`
`bc_view
`Runs the BCView performance analysis tool.
`
`bc_view
`[-f project_file]
`[-license_preference package | individual]
`
`aman
`Displays Synopsys extended error messages.
`
`aman [error_message_code]
`
`cache_ls
`Lists elements in a Synopsys cache.
`
`cache_ls
`cache_dir
`reg_expr
`
`cache_rm
`Removes elements from a Synopsys cache.
`
`cache_rm
`cache_dir
`reg_expr
`
`create_types
`Extracts user-defined type information from VHDL
`package files.
`
`create_types
`[-nc]
`[-w lib]
`[-v]
`[-o logfile]
`file_list
`
`User Commands 3
`
`

`

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`
`dc_shell-t
`Invokes the Design Compiler shell in dctcl mode. For
`more information, see the man page for dc_shell.
`
`dc_shell-t
`[-f script_file]
`[-x command_string]
`[-no_init]
`[-checkout feature_list]
`[-wait wait_time]
`[-timeout timeout_value]
`[-version]
`[-behavioral]
`[-fpga]
`[-syntax_check | -context_check]
`
`dc_shell
`Invokes the Design Compiler command shell.
`
`dc_shell
`[-f script_file]
`[-x command_string]
`[-no_init]
`[-checkout feature_list]
`[-tcl_mode]
`[-wait wait_time]
`[-timeout timeout_value]
`[-version]
`[-behavioral]
`[-fpga]
`[-syntax_check | -context_check]
`
`design_analyzer
`Runs the Design Analyzer menu interface in the X
`Window System.
`
`design_analyzer
`[-menu_script]
`[-no_menu_script]
`[-f script_file]
`[-x command_string]
`[-no_init]
`[-checkout feature_list]
`[-timeout timeout_value]
`[-version]
`[-behavioral]
`[-fpga]
`[-syntax_check | -context_check]
`
`4 User Commands
`
`

`

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`design_vision
`Runs Design Vision visualization for Synopsys
`synthesis products.
`
`design_vision
`[-f script_file]
`[-x command_string]
`[-no_init]
`[-checkout feature_list]
`[-timeout timeout_value]
`[-version]
`[-behavioral]
`[-syntax_check | -context_check]
`[-tcl_mode]
`
`lc_shell
`Runs the Library Compiler command shell.
`
`lc_shell
`[-f script_file]
`[-x command_string]
`[-no_init]
`[-version]
`
`library_compiler
`Runs the Library Compiler graphical interface in the
`X window system.
`
`library_compiler
`[-f script_file]
`[-x command_string]
`[-no_init]
`[-version]
`
`ra_shell
`Runs the RTL Analyzer command shell.
`
`ra_shell
`[-f script_file]
`[-x command_string]
`[-no_init]
`[-checkout feature_list]
`[-timeout timeout_value]
`[-version]
`
`User Commands 5
`
`

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`
`synenc
`Runs the Synopsys Encryptor for HDL source code.
`
`synenc
`[-r synopsys_root]
`file_list
`
`synopsys_users
`Lists the current users of the Synopsys licensed
`features.
`
`synopsys_users [feature_list]
`
`6 User Commands
`
`

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`
`Synthesis Commands
`This section contains the following subsections:
`• Command Syntax
`• Commands Specific to dcsh Mode
`• Commands Specific to dctcl Mode
`
`Command Syntax
`Invoke these commands from within a synthesis tool.
`Unless otherwise noted, all commands are available in
`both dcsh and dctcl mode.
`
`acs_check_directories (dctcl-mode only)
`Checks Automated Chip Synthesis (ACS) directory
`structure settings for correctness. For use in dc_shell-t
`(Tcl mode of dc_shell) only.
`
`int acs_check_directories
`
`acs_compile_design (dctcl-mode only)
`Compiles the constrained RTL to a netlist using
`constraints propagated from the top-level design. For
`use in dc_shell-t (Tcl mode of dc_shell) only.
`
`int acs_compile_design
`[-destination pass_name]
`[-prepare_only]
`[-force]
`[-update]
`[-update_source source_pass]
`design_name
`
`acs_create_directories (dctcl-mode only)
`Creates the project directory tree for Automated Chip
`Synthesis. For use in dc_shell-t (Tcl mode of
`dc_shell) only.
`
`int acs_create_directories
`
`Synthesis Commands 7
`
`

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`acs_get_parent_partition (dctcl-mode only)
`Creates a collection of designs that are compile
`partitions and that contain the specified subdesign.
`For use in dc_shell-t (Tcl mode of dc_shell) only.
`
`string acs_get_parent_partition
`design_name
`[-hierarchy]
`[-list]
`
`acs_get_path (dctcl-mode only)
`Gets the path location for the specified file. To specify
`a file, specify its file type and, for pass-dependent
`files, its pass directory. For use in dc_shell-t (Tcl
`mode of dc_shell) only.
`
`string acs_get_path
`-file_type filetype
`[-mode read | write]
`[-pass pass_name]
`[[-name filename]
`[-append]]
`[-relative]
`
`acs_merge_design (dctcl-mode only)
`Preprocesses a design for incremental design update
`by merging the modified designs and their parent
`compile partitions with the mapped design being
`updated. For use in dc_shell-t (Tcl mode of dc_shell)
`only.
`
`int acs_merge_design
`-update design_list
`[-unmapped source_dir]
`[-mapped data_dir]
`[-type pre | post]
`[-destination dest_dir]
`design_name
`
`8 Synthesis Commands
`
`

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`
`acs_read_hdl (dctcl-mode only)
`Reads in the HDL source code of a design and
`generates the GTECH representation in memory. For
`use in dc_shell-t (Tcl mode of dc_shell) only.
`
`int acs_read_hdl
`[design_name]
`[-hdl_source file_or_dir_list]
`[-exclude_list file_or_dir_list]
`[-format {verilog | vhdl}]
`[-recurse]
`[-no_dependency_check]
`[-no_elaborate]
`[-ignore_analyze_errors]
`[-library design_lib_name]
`[-verbose]
`
`acs_recompile_design (dctcl-mode only)
`Compiles an unmapped constrained .db file using
`time budgets. The time budgets are created by using a
`previously-mapped design. For use in dc_shell-t (Tcl
`mode of dc_shell) only.
`
`int acs_recompile_design
`-budget_source budget_pass
`-destination destination_pass
`[-source source_pass]
`[-prepare_only]
`[-force]
`[-update]
`[-update_source source_pass]
`design_name
`
`acs_refine_design (dctcl-mode only)
`Refines an already mapped design. For use in
`dc_shell-t (Tcl mode of dc_shell) only.
`
`int acs_refine_design
`[-source pass_name]
`[-destination pass_name]
`[-prepare_only]
`[-force]
`[-update]
`[-update_source source_pass]
`design_name
`
`Synthesis Commands 9
`
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`acs_report_directories (dctcl-mode only)
`Reports the current directory structure settings. For
`use in dc_shell-t (Tcl mode of dc_shell) only.
`
`int acs_report_directories
`[-file_types type_list]
`
`add_module
`Reads in a specified library file containing module
`functional information and uses it to update an
`existing technology library.
`
`int add_module
`[-overwrite]
`[-permanent]
`file_name
`library_name
`[-no_warnings]
`
`add_to_collection (dctcl-mode only)
`Adds objects to a collection, resulting in a new
`collection. The base collection remains unchanged.
`
`collection add_to_collection
`base_collection
`object_spec
`[-unique]
`
`after (dctcl-mode only)
`Built-in Tcl command.
`
`alias
`Defines an alias for a command, or lists current alias
`definitions.
`
`int alias [identifier [expansion]]
`
`all_clocks
`Returns a list of all clocks in the current design. In
`dctcl mode, a collection is returned.
`
`list all_clocks()
`
`10 Synthesis Commands
`
`

`

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`
`all_cluster_cells
`Returns a list of cells contained in the specified
`cluster. In dctcl mode, a collection is returned.
`
`list all_cluster_cells
`[-hierarchy]
`cluster_name
`
`all_clusters
`Returns a list of subclusters associated with a
`specified cluster or with the current design. In dctcl
`mode, a collection is returned.
`
`list all_clusters
`[-cluster cluster_name]
`[-leaf]
`
`all_connected
`Returns the objects connected to a net, port, pin, or a
`net or pin instance.
`
`list all_connected object
`
`all_critical_cells
`Returns a list of critical leaf cells in the top hierarchy
`of the current design. In dctcl mode, a collection is
`returned.
`
`list all_critical_cells
`[-slack_range range_value]
`
`all_critical_pins
`Returns a list of critical endpoints or startpoints in the
`current design. In dctcl mode, a collection is returned.
`
`list all_critical_pins
`[-type endpoint | startpoint]
`[-slack_range range_value]
`
`all_designs
`Returns a list of all designs in the current design. In
`dctcl mode, a collection is returned.
`
`list all_designs
`
`Synthesis Commands 11
`
`

`

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`
`all_fanin
`Reports pins, ports, or cells in the fanin of specified
`sinks.
`
`list all_fanin
`-to sink_list
`[-startpoints_only]
`[-exclude_bboxes]
`[-break_on_bboxes]
`[-only_cells]
`[-flat]
`[-levels count]
`
`all_fanout
`Returns a set of pins, ports, or cells in the fanout of
`the specified sources.
`
`list all_fanout
`-clock_tree
`-from source_list
`[-endpoints_only]
`[-exclude_bboxes]
`[-break_on_bboxes]
`[-only_cells]
`[-flat]
`[-levels count]
`
`all_inputs
`Returns a list of input or inout ports in the current
`design. In dctcl mode, a collection is returned.
`
`list all_inputs
`[-clock clock_name]
`[-edge_triggered | -level_sensitive]
`
`all_outputs
`Returns a list of output or inout ports in the current
`design. In dctcl mode, a collection is returned.
`
`list all_outputs
`[-clock clock_name]
`[-edge_triggered | -level_sensitive]
`
`12 Synthesis Commands
`
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`
`all_registers
`Returns a list of sequential cells or pins in the current
`design. In dctcl mode, a collection is returned.
`
`list all_registers
`[-no_hierarchy]
`[-clock clock_name]
`[-cells]
`[-data_pins]
`[-clock_pins]
`[-slave_clock_pins]
`[-inverted_output]
`[-output_pins]
`[-level_sensitive | -edge_triggered]
`[-master_slave]
`
`allocate_budgets (dcsh-mode only)
`Allocates budgets to the specified cells.
`
`string allocate_budgets
`[-incremental]
`[-check_only]
`[-create_context]
`[-no_boundary_annotations]
`[-effort allocation_effort]
`[-min_register_to_output minimum_budget]
`[-min_input_to_output minimum_budget]
`[-min_input_to_register minimum_budget]
`[-no_environment]
`[-interblock_logic]
`[-file_format_spec format_spec]
`[-format script_format]
`[-separator name_separator]
`[-levels budget_levels]
`[-write_context]
`[-budget_design_ware]
`[cell_list]
`
`Synthesis Commands 13
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`
`allocate_partition_budgets (dctcl-mode only)
`Creates budgets for the compile partitions in the
`specified design. For use in dc_shell-t (Tcl mode of
`dc_shell) only.
`
`int allocate_partition_budgets
`-source src_pass
`-destination dst_pass
`[-absolute_paths]
`[-budget_shell budget_shell_exec]
`[-transcript_exec transcript_exec]
`[-format dcsh | dctcl]
`[-overconstrain overcstr]
`[-effort allocation_effort]
`[-interblock_logic]
`[-min_register_to_output minimum_budget]
`[-min_input_to_output minimum_budget]
`[-min_input_to_register minimum_budget]
`[-no_environment]
`[-generate_script_only]
`[-remove]
`design
`
`analyze
`Analyzes HDL files and stores the intermediate
`format for the HDL description in the specified
`library.
`
`int analyze
`[-library library_name]
`[-work library_name]
`[-format vhdl | verilog]
`[-create_update]
`[-update]
`[-define define_list]
`[schedule]
`file_list
`
`14 Synthesis Commands
`
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`
`annotate_activity
`Sets (or resets) the toggle_rate and static_probability
`values for specified objects in the current design.
`
`int annotate_activity
`[-static_probability sp_value]
`[-toggle_rate tr_value]
`[-clock clock_port_name]
`[-period period_value]
`[-hier]
`[-reset]
`[-select ports|regs|all]
`[-objects object_list]
`[-instances instance_list]
`
`append (dctcl-mode only)
`Built-in Tcl command.
`
`apropos (dctcl-mode only)
`Search the command database for a pattern.
`
`string apropos
`[-symbols_only]
`pattern
`
`array (dctcl-mode only)
`Built-in Tcl command.
`
`attach_region
`Attaches cells to an existing region.
`
`int attach_region
`[-name region_name]
`cell_list
`
`auto_execok (dctcl-mode only)
`Built-in Tcl command.
`
`auto_import (dctcl-mode only)
`Built-in Tcl command.
`
`auto_load (dctcl-mode only)
`Built-in Tcl command.
`
`auto_load_index (dctcl-mode only)
`Built-in Tcl command.
`
`Synthesis Commands 15
`
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`
`auto_qualify (dctcl-mode only)
`Built-in Tcl command.
`
`balance_buffer
`Builds a balanced buffer tree on user-specified nets
`and drivers.
`
`int balance_buffer
`[-verify]
`[-verify_hierarchically]
`[-verify_effort low | medium | high]
`[-from start_point_list]
`[-to end_point_list]
`[-net net_list]
`[-force]
`[-library library_name]
`[-prefer buffer | inverter | lib_cell_name]
`
`balance_registers
`Moves the registers of a design to achieve a minimum
`cycle time.
`
`int balance_registers [design_name]
`
`bc_check_design
`Performs a quick check of Behavioral Compiler
`scheduling information on the current design and
`reports incorrect coding styles.
`
`int bc_check_design
`[-io_mode cycle_fixed | superstate_fixed]
`[-constraints]
`
`bc_dont_register_input_port
`For Behavioral Compiler, disables automatic register
`allocation for the specified input port.
`
`int bc_dont_register_input_port port_name
`
`16 Synthesis Commands
`
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`

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`
`bc_dont_ungroup
`Prevents the compile command from ungrouping cells
`grouped by Behavioral Compiler, for the specified
`group classes or for all grouped cells in the current
`design.
`
`int bc_dont_ungroup
`[-register]
`[-fsm]
`[-random_logic]
`[-prio_logic]
`[-array_logic]
`
`bc_group_process
`For Behavioral Compiler, creates one level of
`hierarchy instead of flattening each process after
`scheduling.
`
`int bc_group_process [-with_memory]
`
`bc_margin
`Sets the timing margin used by Behavioral Compiler.
`
`int bc_margin
`[-process process_name]
`[-global margin]
`[-reg margin]
`[-fsm margin ]
`[-mux margin]
`[-preferred_FF cell_name]
`[-report_FF]
`
`bc_report_arrays
`Reports conflicting and non-conflicting accesses to
`arrays mapped to register files within an elaborated
`behavioral design.
`
`int bc_report_arrays
`[-conflicting]
`[-non_conflicting]
`
`Synthesis Commands 17
`
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`

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`
`bc_report_memories
`Reports specific information about the memories
`instantiated within an elaborated behavioral design
`and in the available synthetic libraries.
`
`int bc_report_memories
`[-synthetic_libraries]
`[-bindings]
`[-used_memories]
`[-conflicting]
`[-non_conflicting]
`
`bc_time_design
`Calculates timing and area estimates and annotates
`them on the current design for Behavioral Compiler
`and SystemC Compiler.
`
`int bc_time_design
`[-force]
`[-fastest]
`[-cache_preserved_functions library_name
`[-except designs]]
`[-use_cached_preserved_functions
`library_name [-recompile designs]]
`
`bc_view
`Invokes BCView on the current design.
`
`int bc_view
`[-output out_db_file]
`[-project_file project_file_name]
`[-dont_start]
`[-cossap]
`[-search_additional path_list]
`[-host machine_name]
`[-arch architecture_name]
`
`binary (dctcl-mode only)
`Built-in Tcl command.
`
`break
`Immediately exits a loop structure.
`
`int break
`
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`
`calculate_rtl_load
`Calculates RTL load values using layout-based
`annotation.
`
`int calculate_rtl_load
`-capacitance
`-delay pin_net_list
`
`catch (dctcl-mode only)
`Built-in Tcl command.
`
`cd
`
`Changes the current directory.
`
`int cd [directory]
`
`cell_of
`Returns the cell objects for given pins in the current
`design.
`
`list cell_of [object_list]
`
`chain_operations
`Specifies a list of operations to be scheduled by
`Behavioral Compiler for a specified process or for all
`processes.
`
`int chain_operations
`[-process process_name] operation_names
`
`change_link
`Changes the design to which a cell is linked.
`
`int change_link
`object_list
`design_name
`
`change_names
`Changes the names of ports, cells, and nets in a
`design.
`
`int change_names
`[-rules name_rules]
`[-hierarchy]
`[-verbose]
`[-names_file names_file]
`[-log_changes log_file_name]
`
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`characterize
`Captures information about the environment of
`specific cell instances, and assigns the information as
`attributes on the design to which the cells are linked.
`
`int characterize
`cell_list
`[-no_timing]
`[-constraints]
`[-connections]
`[-power]
`[-verbose]
`
`check_bindings
`Checks the bindings in a synthetic library module
`definition.
`
`int check_bindings
`[-bindings binding_list]
`[-pin_widths pin_width_list]
`module_name
`
`check_bsd
`Checks whether a design's boundary-scan
`implementation is compliant with IEEE Std 1149.1.
`
`int check_bsd
`[-verbose]
`[-effort low | medium | high]
`
`check_budget
`Checks that user-specified budgets and fixed delays
`are consistent with path constraints.
`
`string check_budget
`[-verbose]
`[-tolerance tolerance]
`[-from object_list]
`[-to object_list]
`[-no_environment]
`[-interblock_logic]
`[cell_list]
`
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`check_design
`Checks the current design for consistency.
`
`int check_design
`[-summary]
`[-no_warnings]
`[-one_level]
`[-post_layout | -only_post_layout]
`
`check_dft
`Checks a design against the design rules of a scan test
`methodology with test points that have been inserted
`by either Autofix or Shadow LogicDFT.
`
`int check_dft
`[-verbose]
`[-check_contention true | false |
`scan_shift_only | capture_only]
`[-check_float true | false | scan_shift_only
`| capture_only]
`
`check_error
`Prints extended information on errors from last
`command.
`
`int check_error
`[-verbose]
`[-reset]
`
`check_implementations
`Checks the implementations in a synthetic library
`module definition.
`
`int check_implementations
`[-implementations implementation_list]
`[-parameters parameter_list]
`module_name
`
`check_scan
`Checks a design against the design rules of a scan test
`methodology.
`
`int check_scan
`[-verbose]
`[-check_contention true | false]
`[-check_float true | false]
`
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`
`check_synlib
`Performs semantic checks on synthetic libraries.
`
`int check_synlib
`
`check_test
`Checks a design against the design rules of a scan test
`methodology.
`
`int check_test
`[-verbose]
`[-check_contention true | false
`| scan_shift_only | capture_only]
`[-check_float true | false
`| scan_shift_only | capture_only]
`
`check_timing
`Warns about possible timing problems in the current
`design.
`
`int check_timing
`[-overlap_tolerance minimum_distance]
`
`check_unmapped (dcsh-mode only)
`Checks for any unmapped design below the current
`design.
`
`int check_unmapped
`
`clean_buffer_tree
`Removes the buffer tree at a given driver pin on a
`mapped design.
`
`int clean_buffer_tree
`[-from start_point_list |
`-to end_point_list | -net net_list]
`[-hierarchy]
`
`clock (dctcl-mode only)
`Built-in Tcl command.
`
`close (dctcl-mode only)
`Built-in Tcl command.
`
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`
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`
`compare_collections (dctcl-mode only)
`Compares the contents of two collections. If the same
`objects are in both collections, the result is 0 (like
`string compare). If they are different, the result is
`nonzero. The order of the objects can optionally be
`considered.
`
`int compare_collections
`[-order_dependent]
`collection1
`collection2
`
`compare_design
`Compares two designs for functional equivalence.
`
`int compare_design
`[-effort low | medium | high]
`[-jtag]
`[-fsm]
`[-verbose]
`[-hierarchical]
`design1 design2
`
`compare_fsm
`Compares the sequential behavior of two finite state
`machine designs.
`
`int compare_fsm
`design1
`design2
`
`compare_lib
`Performs a cross-reference check between a
`technology library and a symbol library.
`
`int compare_lib
`library1
`library2
`
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`
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`
`compile
`Performs logic-level and gate-level synthesis and
`optimization on the current design. Performs
`logic-level and gate-level synthesis and optimization
`on the current design.
`
`int compile
`[-no_map]
`[-map_effort low | medium | high]
`[-area_effort none | low | medium | high]
`[-incremental_mapping]
`[-exact_map]
`[-verify]
`[-verify_hierarchically]
`[-verify_effort low | medium | high]
`[-ungroup_all]
`[-boundary_optimization]
`[-auto_ungroup area | delay]
`[-no_design_rule | -only_design_rule |
`-only_hold_time]
`[-scan]
`[-background run_name]
`[-host machine_name]
`[-arch architecture]
`[-xterm]
`[-top]
`
`compile_partitions (dctcl-mode only)
`Distributes compile jobs for a design. For use in
`dc_shell-t (Tcl mode of dc_shell) only.
`
`compile_partitions
`-destination pass
`
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`
`compile_preserved_functions
`Compiles and/or writes netlists for preserved
`functions.
`
`int compile_preserved_functions
`[preserved_functions]
`[-exclude preserved_functions]
`[-no_compile]
`[-compile_effort low | medium | high |
`1 | 2 | 3]
`[-include_script script_name]
`[-write]
`[-filename filename]
`[-design_library library_name]
`[-force_recompile]
`[-stages number_of_stages]
`[-clock_port_name clock_port_name]
`[-output_delay delay_value]
`[-input_delay delay_value]
`[-sync_reset reset_port_name]
`[-async_reset reset_port_name]
`[-reset_polarity high | low]
`
`compile_systemc
`Reads a SystemC source file, checks for compliance
`with SystemC Compiler synthesis policy and syntax,
`and creates an internal database (.db) if there are no
`errors.
`
`int compile_systemc
`[-cpp cpp_program]
`[-cpp_options options]
`[-verbose]
`[-preserve functions]
`[-unroll loop_labels]
`[-trace]
`[-hls]
`[-rtl]
`[-rtl_format db | verilog]
`[-output output_file]
`[-single_file]
`[-w/-library directory_name]
`[-param module_spec_list]
`[-dont_rename module_list]
`file_name
`
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`
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`

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`
`compile_ultra
`Performs a two-pass, high-effort compile flow on the
`current design for better QOR results.
`
`int compile_ultra
`[-scan]
`[-no_uniquify]
`[-no_autoungroup]
`
`concat (dctcl-mode only)
`Built-in Tcl command.
`
`connect_net
`Connects a specified net to specified pins or ports.
`
`int connect_net
`net
`object_list
`
`context_check
`Enables or disables the Syntax Checker
`context_check mode in which commands issued are
`checked for context errors.
`
`int context_check true | false
`
`continue
`Begins the next loop iteration.
`
`int continue
`
`copy_collection (dctcl-mode only)
`Duplicates the contents of a collection, resulting in a
`new collection. The base collection remains
`unchanged.
`
`collection copy_collection collection1
`
`copy_design
`Copies a design to a new design, or copies a list of
`designs to a new file in dc_shell memory.
`
`int copy_design
`source_design_name
`target_design_name
`
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`
`create_bsd_patterns
`Generates a set of functional patterns for a
`boundary-scan design.
`
`int create_bsd_patterns
`[-output test_program_name]
`[-effort low | medium | high]
`[-type vector_type_list]
`
`create_bounds
`Creates a fixed movebound or floating group bound in
`the design.
`
`int create_bounds
`[-name bound_name]
`[-coordinate {llx1 lly1 urx1 ury1 ...}]
`[-dimension {width height}]
`[-effort low | medium | high | ultra]
`[-type soft | hard]
`cell_list
`
`create_bus
`Creates a port bus or a net bus.
`
`int create_bus
`object_list
`bus_name
`[-type type_name]
`[-sort]
`[-no_sort]
`[-start start_bit]
`[-end end_bit]
`
`create_cache
`Populates the cache directories with instances of the
`requested synthetic modules.
`
`int create_cache
`-module module_list
`[-implementation implementation_list]
`[-parameters parameter_list]
`[-operating_condition operating_condition]
`[-wire_load list]
`[-report]
`
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`
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`
`create_cell
`Creates cells in the current design.
`
`int create_cell
`cell_list
`[reference_name]
`[-logic logic_value]
`[-only_physical]
`
`create_clock
`Creates a clock object and defines its waveform in the
`current design.
`
`int create_clock
`[port_pin_list]
`[-name clock_name]
`[-period period_value]
`[-waveform edge_list]
`
`create_cluster
`Creates a cluster in the physical hierarchy of the
`design.
`
`int create_cluster
`[-name cluster_name]
`[-keep]
`[-multibits]
`[-parent parent_cluster_object]
`object_list
`
`create_command_group (dctcl-mode only)
`Creates a new command group.
`
`string create_command_group group_name
`
`create_design
`Creates a design in dc_shell memory.
`
`int create_design
`design_name
`[file_name]
`
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`
`create_generated_clock
`Creates a generated clock object.
`
`string create_generated_clock
`[-name clock_name]
`-source master_pin
`[-divide_by divide_factor | -multiply_by
`multiply_factor]
`[-duty_cycle percent]
`[-invert]
`[-edges edge_list]
`[-edge_shift edge_shift_list]
`port_pin_list
`
`create_multibit
`Creates a multibit component for the specified list of
`cells in the current design.
`
`int create_multibit
`object_list
`[-name multibit_name]
`[-sort]
`[-no_sort]
`
`create_net
`Creates nets in the current design.
`
`int create_net
`[-instance instance]
`net_list
`
`create_operating_conditions
`Creates a new set of operating conditions in a library.
`
`int create_operating_conditions
`-name name
`-library library_name
`-process process_value
`-temperature temperature_value
`-voltage voltage_value
`[-tree_type tree_type]
`[-calc_mode calc_mode]
`[-rail_voltages rail_value_pairs]
`
`create_pass_directories (dctcl-mode only)
`Creates the directory structure required for storing
`ACS data. For use in Tcl mode of dc_shell only.
`
`int create_pass_directories pass_list
`
`Synthesis Commands 29
`
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`
`create_port
`Creates ports in the current design.
`
`int create_port
`port_list
`[-direction dir]
`
`create_schematic
`Generates a schematic for the current design.
`
`int create_schematic
`[-hierarchy]
`[-size sheet_size]
`[-portrait]
`[-fill_percent fill_value]
`[-outputs_attract]
`[-order_outputs output_port_list]
`[-sort_outputs]
`[-dont_left_justify_inputs]
`[-schematic_view]
`[-symbol_view]
`[-hier_view]
`[-no_bus]
`[-bit_mappers]
`[-implicit]
`[-no_rippers]
`[-sge]
`[-no_type_mappers]
`[-reference]
`[-gen_database]
`
`create_test_clock
`Defines the timing of a clock applied to a design
`during manufacturing test.
`
`int create_test_clock port_list
`-waveform two_value_rise_fall_edge_list
`[-period period_value]
`[-internal_clocks true | false | default]
`
`create_test_patterns
`This command is obsolete. Use the command
`estimate_test_coverage for test coverage estimation
`and see the man page for syntax. To generate test
`vectors, use TetraMAX ATPG.
`
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`
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`
`create_test_schedule
`Define a series of test modes for the purpose of core
`test scheduling.
`
`int create_test_schedule
`
`create_wire_load
`Creates wire load models for the current design.
`
`int create_wire_load
`[-design design_name]
`[-cell cell_list]
`[-cluster cluster_name]
`[-hierarchy]
`[-this_level_nets_only]
`[-mode top | enclosed]
`[-name model_name]
`[-output file_name]
`[-update_lib library_name]
`[-write_script script_file_name]
`[-dont_smooth]
`[-trim trim_value]
`[-percentile percentile_value]
`[-total_area area]
`[-statistics]
`
`current_design
`Sets the working design in dc_shell.
`
`string current_design [design]
`
`current_design_name (dctcl-mode only)
`Built-in Tcl command.
`
`current_instance
`Sets the working instance object in dc_s