(12) United States Patent
`Philipp
`
`USOO6466036B1
`US 6,466,036 B1
`(10) Patent No.:
`Oct. 15, 2002
`(45) Date of Patent:
`
`(54)
`
`(76)
`
`(*)
`
`(21)
`(22)
`
`(60)
`
`(51)
`(52)
`(58)
`
`(56)
`
`CHARGE TRANSFER CAPACITANCE
`MEASUREMENT CIRCUIT
`
`Inventor: Harald Philipp, 7 Cirrus Gardens,
`Hamble Hampshire SO31 4RH (GB)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`Notice:
`
`Appl. No.: 09/390,869
`Sep. 7, 1999
`Filed:
`Related U.S. Application Data
`Provisional application No. 60/109,889, filed on Nov. 25,
`1998.
`Int. Cl................................................. G01R 27/26
`U.S. Cl. ........................................ 324/678; 324/658
`Field of Search ................................. 324/678, 658,
`324/661, 663, 665, 676, 679
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3,886,447 A *
`4,054,833. A *
`4,806.846 A
`4977,480 A *
`5,329.239 A *
`5,343,157 A *
`5,537,054 A *
`
`5/1975
`10/1977
`2/1989
`12/1990
`7/1994
`8/1994
`7/1996
`
`Tanaka ....................... 324/678
`Briefer ......
`... 324/679
`Kerber ......
`... 324/678
`Nishihara ................. 73/724 X
`Kindermann et al. ....... 324/678
`Deschamps ................. 324/678
`Suzuki et al. ............... 324/770
`
`5,705,807 A * 1/1998 Throngnumchai et al. .. 250/214
`P
`3/1998 Vranish ...................... 324/688
`5,726,581. A
`5,730,165 A 3/1998 Philipp .......................... 137/1
`6,188,228 B1 * 2/2001 Philipp ....................... 324/658
`6,242.927 B1
`6/2001 Adams et al. .............. 324/664
`6,278,283 B1 * 8/2001 Tsugai ........................ 324/678
`OTHER PUBLICATIONS
`“Capacitive Sensors and Sensing Theory,” Product Catalog,
`Gordon Products, Inc., Brookfield, CT, USA, Oct. 1997.*
`* cited by examiner
`Primary Examiner N. Le
`ASSistant Examiner T. R. Sundaram
`(74) Attorney, Agent, or Firm-David Kiewit
`(57)
`ABSTRACT
`Pulse circuits for measuring the capacitance to ground of a
`plate may be used in control equipment to provide an
`indication of the proximity of a perSon or object to be
`Sensed. Pulse circuits are disclosed that are made from Sets
`of three or more electrical Switching elements arranged So
`that each of the Switching elements has one side electrically
`connected to either a Supply Voltage or to an electrical
`ground. These arrangements are compatible with existing
`integrated circuit fabrication technology. In addition, the
`circuitry can be configured as a proximity Sensing Switch
`that requires only a two wire connection to a host apparatus.
`
`39 Claims, 14 Drawing Sheets
`
`SWITCH
`CONTROL
`
`24-y
`
`
`
`
`
`CONTROL
`CKT
`
`12
`
`S3 ,
`
`SENSE PLATE
`
`CS
`
`S2 CX T U-13
`
`18
`
`FREE SPACE
`OR GROUND
`
`
`
`SIGNAL
`PROCESSING
`
`
`
`RESULT
`
`10
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 1 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 1 of 14
`
`US 6,466,036 B1
`
`FIG. 1
`
`|
`S1
`+Vr H-1 - --
`SWITCH
`CONTROL
`
`m
`
`
`
`S3 -
`
`CS
`
`wa
`
`17
`
`revor
`SIGNAL
`PROCESSING
`
`SENSE PLATE
`
`S2 CX T U-13
`
`18
`
`FREE SPACE
`OR GROUND
`
`RESULT
`
`f O
`
`STEP
`
`S1,
`
`w
`
`s
`X
`
`A
`
`B
`C
`D
`N- E
`
`5
`C
`
`F
`
`w
`
`S2
`
`X
`
`S3
`
`X
`
`FUNCTION
`
`RESET ALL
`
`-
`
`X
`
`X
`
`-
`
`-
`
`DEADTIME
`CHARGE-TRANSFER
`DEADTIME
`HOLD
`
`MEASURE
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 2 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 2 of 14
`
`US 6,466,036 B1
`
`CS
`
`VOS
`
`VCX
`
`FIC. 3
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 3 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 3 of 14
`
`US 6,466,036 B1
`
`FIG. 6
`
`
`
`v
`
`S3
`
`X
`
`FREE SPACE
`OR GROUND
`
`FUNCTION
`
`RESET ALL
`DEADTIME
`CHARGE
`DEADTIME
`TRANSFER
`MEASURE
`
`STEP
`
`A
`B
`C
`D
`E
`F
`
`S1
`
`X
`
`w
`X
`X
`
`S2
`
`X
`
`-
`-
`
`5
`C
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 4 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 4 of 14
`
`US 6,466,036 B1
`
`FIC. 7
`
`MSMT
`CKT
`
`14 SENSE PLATE
`
`S1
`
`-
`
`W.
`
`
`
`CS
`
`\S2
`
`-18
`/,
`
`T
`
`-13
`
`-18
`FREE SPACE
`OR GROUND
`
`S3
`
`M
`
`STEP
`
`S1
`
`S2
`
`S3
`
`FUNCTION
`
`5
`C
`
`A
`B
`C
`D
`E
`F
`
`an
`
`X
`
`X
`
`X
`-
`w
`
`-
`X
`X
`
`-
`
`-
`
`RESET ALL
`DEADTIME
`CHARGE-TRANSFER
`DEADTIME
`HOLD
`MEASURE (HOLD)
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 5 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 5 of 14
`
`US 6,466,036 B1
`
`FIG. 9
`
`SENSE PLATE
`
`f3
`
`FREE SPACE
`OR GROUND
`
`s1 \
`18 |
`7714
`
`
`
`STEP
`
`S1
`
`S2
`
`S3
`
`FUNCTION
`
`A
`
`X
`
`X
`
`RESET Cs, CHARGE Cx
`
`w
`
`o
`
`DEADTIME
`
`X
`
`CHARGE
`DEADTIME
`TRANSFER
`
`al
`
`s
`
`MEASURE
`
`X
`
`X
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 6 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 6 of 14
`
`US 6,466,036 B1
`
`
`
`N AT LEAST ONE OF
`
`FIC. 1 1
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 7 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 7 of 14
`
`US 6,466,036 B1
`
`Cx FUNCTION
`STEP S1 S2 S3 S4 CX1
`CX2
`A
`-
`X -
`X RESET
`RESET
`B
`-
`-
`-
`-
`DEADTIME
`DEADTIME
`C
`25(
`X -
`-
`-
`CHARGE
`CHG-TRANS
`9\ D
`-
`-
`-
`-
`DEADTIME
`DEADTIME
`E
`-
`-
`-
`X TRANSFER
`HOLD
`F
`-
`-
`-
`-
`DEADTIME
`DEADTIME
`G
`-
`-
`-
`X
`MEASURE 2
`G'
`X -
`-
`-
`MEASURE 1
`FIG. 12
`
`5
`C
`
`CX FUNCTION
`STEP S1 S2, S3 S4 CX1
`CX2
`A
`-
`X -
`X RESET
`RESET
`B
`-
`-
`-
`-
`DEADTIME
`DEADTIME
`C
`-
`-
`X -
`CHG-TRANS CHARGE
`D
`-
`-
`-
`-
`DEADTIME
`DEADTIME
`E
`-
`X -
`-
`HOLD
`TRANSFER
`F
`-
`-
`-
`-
`DEADTIME
`DEADTIME
`G
`- X -
`-
`MEASURE 2
`G'
`-
`-
`X
`MEASURE 1
`
`FIG. 13
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 8 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 8 of 14
`
`US 6,466,036 B1
`
`
`
`13 - SENSE PLATE
`
`SENSE PLATE
`
`AT LEAST ONE OF
`
`FIG. 14
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 9 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 9 of 14
`
`US 6,466,036 B1
`
`
`
`
`
`CS
`(PIEZO
`BEEPER) S4
`8
`f
`
`
`
`26
`VOLTAGE
`COMPAR
`ATOR
`
`SWITCH
`CONTROL
`S1 S2 S3 S4
`
`24-y
`
`CONTROL LOGIC OR MICROCONTROLER
`
`28
`
`?
`
`22-
`
`OUTPUT
`
`FIG. 16
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 10 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 10 of 14
`
`US 6,466,036 B1
`
`FIG. 16
`
`D
`
`D
`SIGNAL D =
`THRESHOLD
`
`
`
`SIGNAL <
`THRESHOLD
`
`3
`
`4.
`
`6
`
`
`
`
`
`SIGNAL D =
`THRESHOLD
`
`6 is 5 -6)
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 11 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 11 of 14
`
`US 6,466,036 B1
`
`- 14
`
`MSMT
`CKT 1
`
`N
`
`S1
`
`1- N -
`
`S2
`
`SENSE PLATE
`
`CS
`
`LARGE)
`(
`SENSE PLATE
`
`
`
`MSMT
`CKT 2
`
`/
`
`- 14
`
`S3
`N- +Vr
`
`f8
`
`S6
`
`FIC. 1 7
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 12 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 12 of 14
`
`US 6,466,036 B1
`
`
`
`TTV/ LEISER
`
`E|W|LOW/EC
`
`0 = ZO ‘ESO»JVHO
`
`EWNI LOVEO
`
`0 = ZO ‘HEHSNV HL
`
`EWNI LOVENCI
`
`ZO ESO}}\/HO
`
`SO SXAOTTE ZO
`
`
`
`EVNI LOVEO
`
`
`
`ZXO ENTIS\/E||W
`
`EW|LOVEC
`
`8/ (f)I, H.
`
`
`
`CHOOT NOI LWTTE ONVO HELDO :E CHOOT
`
`
`
`
`
`
`
`cHOOT LÒ (HENNI :\/ CHOOT
`
`| S
`
`d'El LS
`
`W OOT
`
`/
`9 OOT
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 13 of 24
`
`

`

`U.S. Patent
`
`Oct. 15, 2002
`
`Sheet 13 of 14
`
`US 6,466,036 B1
`
`
`
`SENSE PLATE
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 14 of 24
`
`

`

`US. Patent
`
`Oct. 15, 2002
`
`Sheet 14 0f 14
`
`US 6,466,036 B1
`
`MODULE
`
`
` QT SENSOR
`
`\\\\\\\\\
`\\\\\\\\\
`\\\\\\\\\
`\\\\\\\\\
`\‘\\‘\\‘\\\\
`\\\\\\\\\
`\\\\\\\\\
`\\\\\\\\\
`\\\\\\\\\
`\\\\\\\\\
`\\\\\\\\\
`\\\\\\\\\
`
`\\\\\\\\
`
`\\\\\\\\
`
`
`
`\ \\\\\\\
`
`‘\‘\‘\\\‘\‘\\
`
`FIG. 20
`
`Petitioner STMICROELECTRONICS, INC,
`
`EX. 1027, IPR2021-01161 Page 15 of 24
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 15 of 24
`
`

`

`1
`CHARGE TRANSFER CAPACITANCE
`MEASUREMENT CIRCUIT
`
`US 6,466,036 B1
`
`15
`
`2
`Yet another benefit of the invention is that it provides a
`Small, inexpensive “beeper Switch having an audible output
`responsive to a users touch and taking up no more room
`than a conventional Silent Switch.
`Although it is believed that the foregoing recital of
`features and advantages may be of use to one who is skilled
`in the art and who wishes to learn how to practice the
`invention, it will be recognized that the foregoing recital is
`not intended to list all of the features and advantages,
`Moreover, it may be noted that various embodiments of the
`invention may provide various combinations of the herein
`before recited features and advantages of the invention, and
`that less than all of the recited features and advantages may
`be provided by some embodiments.
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`FIG. 1 a Schematic block circuit diagram showing an
`implementation of the invention using three Switches.
`FIG. 2 a Switching table depicting the Switching Sequence
`of the three Switches of FIG. 1.
`FIG. 3 is a Schematic circuit diagram depicting a rear
`rangement of the circuit of FIG. 1.
`FIG. 4 is a plot of a Voltage acroSS CS as a function of
`cycle number during a burst-mode operation.
`FIG. 5 is a Schematic circuit diagram depicting a circuit
`having topology analogous to that depicted in FIG. 1.
`FIG. 6 is a Switching table describing the Switching
`sequence of the three Switches of FIG. 5.
`FIG. 7 is a Schematic circuit diagram depicting a rear
`rangement of the Switches of FIG. 1.
`FIG. 8 is a Switching table corresponding to the Switch
`array of FIG. 7.
`FIG. 9 is a Schematic circuit diagram depicting a rear
`rangement of the Switches of FIG. 5.
`FIG. 10 is a Switching table corresponding to the Switch
`array of FIG. 9.
`FIG. 11 is a Schematic circuit diagram depicting a Switch
`arrangement that can provide the functions of the arrange
`ments depicted in FIGS. 7 and 9, and by inference, those
`depicted in FIGS. 1 and 5.
`FIG. 12 is a Switching table corresponding to the Switch
`arrangement of FIG. 11, wherein the depicted Sequence
`provides the functionality of FIG. 7 with respect to CX2, and
`the functionality of FIG. 9 with respect to Cx1.
`FIG. 13 is a Switching table corresponding to the Switch
`arrangement of FIG. 11, wherein the depicted Sequence
`provides the functionality of FIG. 9 with respect to CX2, and
`the functionality of FIG. 7 with respect to Cx1.
`FIG. 14 is a schematic circuit diagram similar to that of
`FIG. 11, but wherein a resistor is placed across Cs, and the
`Sensor is operated in a continuous ("CW") mode as opposed
`to a burst mode.
`FIG. 15 is a schematic block diagram of an embodiment
`of the invention wherein CS is a portion of a piezoelectric
`transducer, thus providing a touch Switch having an audible
`beeper.
`FIG. 16 is a flow diagram depicting the operation of the
`circuit of FIG. 15.
`FIG. 17 is a Schematic circuit diagram depicting a Sensor
`of the invention incorporating a charge cancellation means.
`FIG. 18 is a Switching table depicting one possible
`Sequence of incorporating charge cancellation in the circuit
`of FIG. 17.
`
`25
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`This application claims the priority o of a U.S. Provisional
`Application for Patent filed on Nov. 25, 1998 and having
`Ser. No. 60/109,889.
`STATEMENT REGARDING FEDERALLY
`SPONSORED RESEARCH OR DEVELOPMENT
`Not Applicable
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The invention pertains to the Sensing or measurement of
`electrical capacitance, and in particular to the Sensing an
`object's proximity to or contact with a Sense plate connected
`to a capacitance measurement circuit
`2. Background Information
`In his U.S. Pat. No. 5,730,165, the inventor teaches a
`capacitive field Sensor employing a single coupling plate and
`a method of detecting a change in capacitance of the
`coupling plate, CX, to ground. The apparatus taught in U.S.
`Pat. No. 5,730,165 comprises pulse circuitry for charging
`the coupling plate and for Subsequently transferring the
`charge from the plate into a charge detector, which may be
`a Sampling capacitor, Cs. The transferring operation is
`carried out by means of a transfer Switch electrically con
`nected between the coupling plate and the charge detector.
`The disclosure of U.S. Pat. No. 5,730,165 is herein incor
`porated by reference.
`In U.S. Pat. No. 4,806,846, Kerber teaches a pulse circuit
`for measuring an unknown capacitance. His arrangement is
`characterized by careful elimination of effects of Stray
`capacitances, Such as a capacitance to ground. Kerber
`employs two clocked Switches and a buffer amplifier to
`charge and discharge the capacitor under test.
`40
`BRIEF SUMMARY OF THE INVENTION
`The invention provides apparatus and method for mea
`Suring an absolute or relative value of the capacitance of a
`capacitor or other element having the electrical property of
`capacitance, as well as for measuring changes in a capacitive
`value. In many uses of interest, a change in the capacitance
`to ground of a Sense plate is measured and a control output
`is generated responsive to the change.
`A feature of Some embodiments of the invention is the
`provision of novel pulse circuitry for measuring capacitance
`to ground, the circuitry comprising a plurality of electrical
`Switching elements, each of which has one side electrically
`connected to either a power Supply Voltage or to a circuit
`ground point. This circuit arrangement is more compatible
`with available integrated circuit design and manufacturing
`practices than is prior art pulse circuitry, which commonly
`had one side of at least one Switching element floating.
`These improved arrangements thereby provide Superior per
`formance at a lower manufacturing cost.
`Another aspect of the invention is that it provides a
`proximity Sensing means having only two electrical wires
`connecting it to a host apparatus. This Sensing means can
`directly replace a magnetic reed Switch or a mechanical
`Switch having two contacts and connecting wires.
`Another benefit of the invention is the ability to compen
`Sate for environmental changes Such as Signal drift and
`erroneous stuck Sensor conditions.
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 16 of 24
`
`

`

`25
`
`3
`FIG. 19 is a schematic block diagram depicting a 2-wire
`configuration of the Sensor.
`FIG. 20 is a schematic view depicting a sensor of the
`invention being employed to monitor the level of fluid in a
`glass or plastic tank.
`GLOSSARY OF TERMS
`The symbols and terms used herein are defined as follows
`unless Specifically noted otherwise within a particular con
`text:
`Sensor a circuit for measuring the absolute or relative
`capacitance of either a two-leaded capacitor or of a
`free-space Sense plate, and for providing as an output,
`a measurement of the capacitance in a usable form. A
`15
`device only capable of generating a single-bit thresh
`olded “detect' output is still considered a “sensor' for
`purposes of this disclosure.
`Sensing the Sensing of capacitance by means of a Sensor.
`Of particular interest to the invention is the Sensing of
`"ground referenced capacitance', which refers to
`capacitance from a Sense plate to any object in the
`environment thereof.
`CX an unknown capacitance to be measured by the Sensor.
`CX may be either a 2-leaded capacitor or a free-space
`Sense plate. Plural unknown capacitances are referred
`to as Cxl, CX2 etc.
`CS a Sample capacitor having a fixed value, normally
`much larger than the value of Cx. One of the two
`terminals of Cs, hereinafter called the proximal
`terminal, is connected to CX. The Second terminal of CS
`is Sometimes referred to hereinafter as the distal ter
`minal. The Voltage acroSSCS is used as an indication of
`the value of Cx.
`Switch an electronically controlled Switch, which may be
`a bipolar or field effect transistor (“FET"), relay, opto
`electronic device, or Similar circuit.
`proximity any event or circumstance resulting in a mea
`Surable capacitance or a measurable change in capaci
`tance. Specific examples hereinafter provided are often
`drawn with respect to the physical proximity of a user
`to a Sense plate.
`Q The symbol of the fundamental unit of charge,
`expressed in Coulombs.
`QT (Also referred to as charge-transfer) A method of
`Sensing capacitance by transferring electrical charge in
`a controlled manner by the use of one or more Switch
`ing elements, which are preferably FETs.
`burst a finite, discrete number of QT cycles used to
`accumulate charge on Cs, where the accumulated
`charge is representative of the value of CX. Burst
`operation differs from continuous QT cycling.
`measurement circuit-A Voltage Sensing means that mea
`Sures a Voltage on CS and converts that Voltage to a
`55
`another form. A "measurement circuit' can be an
`Analog-To-Digital converter (“ADC), a simple volt
`age comparator (which can be viewed as an
`ADC having only a single output bit), an analog buffer or
`amplifier chain, etc., all of which are well known in the art.
`In Several of the figures, this element is indicated as a block
`labeled “MSMT CKT
`controller A control means comprising a circuit or System
`capable of generating digital control Signals. The con
`troller may control the Sensor (including control of
`Switching elements therein) and the measurement cir
`cuit and may generate a decision output if required. The
`
`4
`controller preferably comprises digital logic means
`Such as random logic, a State machine, or a micropro
`CCSSO.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`Turning now to FIG. 1, one finds a Schematic depiction of
`a first embodiment of the invention 10. In the circuit
`depicted in FIG. 1 a first Switching element, S1, is used to
`drive electric charge through both a Sampling capacitor, Cs,
`and a capacitance to be measured, Cx, during Step C (as
`summarized in the table of FIG. 2). This leaves residual
`charges on both Cs and CX after S1 opens in step D of FIG.
`2. Kirchoff's current law and the principle of charge con
`Servation dictate that these charges, QX and QS, are equal.
`However, because CSD>CX, a greater residual Voltage is
`found on CX, and conversely, a lesser Voltage is measured on
`Cs. FIG.3 reveals that the arrangement of FIG. 1 may be
`Viewed as a capacitive Voltage divider in considering the
`closure of S1 in step C of FIG. 2.
`In FIG. 1, as in Some other figures of the drawing, a Sense
`plate 13 is explicitly depicted to indicate that in many uses
`of the invention the presence or motion of an object that is
`not part of the apparatus of the invention is to be Sensed by
`a capacitive measurement. Although the drawing Sometimes
`shows both a Sense plate 13 and an unknown capacitance,
`Cx, it will be understood to those skilled in the art that in
`these depictions CX is the capacitance of the Sense plate 13
`to free Space or to an electrical ground.
`Again referring to the depiction of FIG. 1, a Second
`Switching element, S2, is used to clear the Voltage and
`charge on CS, and also to allow the measurement of Vcs, the
`voltage across Cs. It may be noted that the use of S2 allows
`S1 to be cycled repeatedly in order to build up the charge on
`CS. This provides a larger measurable Voltage value and
`greater accuracy, increasing Sense gain or Sensitivity without
`the use of active amplifiers. A third Switching element, S3,
`acts as a reset Switch and is used to reset the charge on CS
`prior to beginning a QT burst as explained below.
`A preferred control circuit 12 of FIG. 1 controls the
`Switching Sequence and also the operation of the measure
`ment circuit 14. A signal processing module, indicated as
`block 16, may be required to translate an output of the
`measurement circuit into a usable form. For example, this
`may involve converting cycle counts to a binary represen
`tation of Signal Strength. The Signal processing block 16 may
`also contain other linear Signal processing elements Such as
`filters and/or nonlinear functions Such as threshold compari
`Sons as described elsewhere herein, So as to provide an
`output Suitable for an intended application Although the
`control circuit 12 and processing circuit 16 are depicted only
`in FIG. 1, it will be clear to those skilled in the art that Such
`circuit elements would be used with the circuits depicted
`elsewhere in the drawing (e.g., as indicated by the bold
`output arrow from the MSMT CKT), but that these elements
`have been omitted in the interest of clarity of presentation.
`The table of FIG. 2 shows the Switching sequence
`required in one implementation using the circuit of FIG. 1.
`First, in step A, Switching elements S2 and S3, which were
`previously in their respective open States, are closed to clear
`charge on Cs and CX. After a Suitable pause in Step A, S1 is
`closed to drive charge through Cs and Cx (Step C). The
`resulting first voltage increment acroSS CS is defined by the
`capacitive divider equation:
`(Eqn. 1)
`AVCS(1)=V,Cxf(Cs+Cx),
`where Vr is the reference voltage connected to S1.
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`US 6,466,036 B1
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 17 of 24
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`US 6,466,036 B1
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`In Step E of the table in FIG. 2, S2 is closed, and AVcs
`appears as a ground-referenced signal on the positive, distal,
`terminal of Cs. Deadtime steps B and D are employed to
`prevent Switch cross-conduction, which would degrade the
`charge build-up on CS. Deadtime can be quite short, mea
`Suring a few nanoSeconds, or longer if desired. Steps B
`through E may be repeated in a looping manner, to provide
`a “burst' of QT cycles. After a suitable QT burst length, the
`QT cycle is terminated and Vcs is measured in the afore
`mentioned manner, perhaps by an ADC, in Step F, with S2
`closed and the other Switches open. Following the measure
`ment of Vcs, S3 may also be closed to reset CS in preparation
`for the next OT burst.
`In an alternative embodiment, steps E and F of FIG. 2 are
`combined So that a measurement is made at each QT cycle.
`This Switch Sequence variation is also applicable to all the
`variants of the circuit to be discussed below in conjunction
`with the remaining figures. By combining Steps E and F,
`which are functionally identical, the measurement circuit
`can be made to consist of a simple Voltage comparator with
`a fixed reference. In Such cases, the looping action of the QT
`cycles is terminated when the Voltage comparison indicates
`that Vcs has risen above a selected threshold value. The
`number of cycles taken to reach this point becomes the
`Signal reading. This method is explained in greater detail
`hereinafter.
`During the repeating loop of steps B through E of FIG. 2,
`Voltage builds up on CS but not CX. CX is continuously being
`discharged in Step E, and hence CX cannot build up an
`increasing amount of charge. However, Cs freely accumu
`lates charge, So that the resulting incremental Voltage is
`dependent on the difference in the voltages Vr and Vcs as
`follows:
`
`where
`Vr is a Supply Voltage that may be a fixed reference
`Voltage;
`n is the QT cycle number; and
`K=CX/(Cs+Cx).
`The final Voltage acroSS Vcs is equal to the Sum of the first
`value of Vcs plus all Subsequent values of AVcs. That is:
`
`Or,
`
`Vcs(N)=XAVcs(n)=KX(AVr-Vcs(n-1)),
`(Eqn. 4)
`where the Summation runs over the range from n=1 to n=N.
`During each QT cycle, the additional incremental Voltage on
`Vcs is less than the increment from the prior cycle and the
`Voltage build-up can be described as a limiting exponential
`function:
`
`V(N)=V-Vre
`(Eqn. 5)
`where d is a time Scaling factor, as shown in FIG. 4.
`In practice, a burst is terminated well before Vcs rises to
`be approximately the same as Vr. In fact, if the rise in Vcs
`is limited to <10% of Vr, the linearity can be made accept
`able for most applications. For simple limit Sensing appli
`cations Vcs can be permitted to rise higher, at the expense
`of increasingly degraded signal-to-noise ratioS in the thresh
`old comparison function.
`The OT burst can be terminated after a fixed or after a
`variable number of cycles. If a fixed number is used, the
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`measurement circuit should be capable of representing con
`tinuous signals much as in the fashion of an ADC or an
`analog amplifier. If a variable burst length is used, a simple
`comparator with a fixed reference can be employed for the
`measurement circuit, and the length of the burst required is
`that at which Vcs has built up to a level where it equals the
`comparison Voltage. The burst can continue beyond the
`required number, but the extra QT cycles are Superfluous. A
`count of the QT cycles required to achieve the comparison
`Voltage is the output result, and for all practical purposes is
`indistinguishable from an ADC result
`Note that in FIG. 1 the voltage measuring means 14 is
`connected to the (+), distal, Side of Cs, and the reading is
`taken when S2 is closed. Although the (+) side of Cs is the
`most convenient measurement point for a ground-referenced
`Signal, it is also possible to measure Vcs on the (-),
`proximal, side of Cs by holding S1 dosed instead of S2. The
`reading is then Vr-referenced instead of ground referenced,
`which most designers will recognize as being generally
`inferior but still possible. In either case, the measurement
`being made is the de facto value of Vcs. Whether the reading
`is made with respect to ground or Vr is irrelevant to the
`invention; what is important is the differential Voltage acroSS
`Cs.
`A Switch arrangement similar to that of FIG. 1 is depicted
`in FIG. 5, where the connections to Vr and the ground
`Voltages are reversed. AS depicted in the corresponding
`Switching table of FIG. 6, the charge and transfer operations
`are separated into two distinct StepSC and D, whereas in the
`circuit of FIG. 1 they were combined in a single step (labeled
`C in FIG. 2). The circuit of FIG. 5 first charges Cx to Vr, but
`the charge on Cx is not transferred into Cs until S1 closes.
`Accordingly the Switch Sequence is different from that used
`with the circuit of FIG. 1, but the looping process to create
`a QT burst requires the same number of steps. Also, the QT
`equations (Eqn. 1) through (Eqn. 5) hold exactly the same
`for the circuit of FIG. 5 as for that of FIG.1. Note that the
`measurement circuit 14 depicted in FIG. 5 monitors the
`voltage on the (+) side of Cs. This is the most convenient
`location to measure a ground-referenced reading of Cs.
`Moreover, a measurement can also be made on the (-),
`distal, terminal of Cs by holding S2 closed during the
`measurement. The comments made above with respect to
`FIG. 1 apply to these measurements as well.
`FIG. 7 shows a variation of the circuit of FIG. 1 that is
`identical as to form and that illustrates that the circuit of FIG.
`1 can be modified slightly without altering its purpose or
`function. In FIG. 7 the reset Switch S3, which had shunted
`the sample capacitor Cs of FIG. 1, is now a ground
`referenced switch. The reset of Cs, as depicted in the
`corresponding Switching table of FIG. 8, is accomplished by
`holding both S2 and S3 closed, thus shorting both ends of Cs
`to ground. The net result is absolutely identical to that
`provided by the circuit of FIG. 1 in all respects, including
`even the required Switching Sequence. An advantage of FIG.
`7 over FIG. 1 is that the circuit of FIG.7 has one side of each
`Switching element connected either to the DC power Supply,
`Vr, or to a chassis or circuit ground 18. That is, the circuit
`of FIG. 7 does not require a floating Switch, which is more
`difficult to manufacture in a CMOS integrated circuit than is
`a ground or Vr referenced Switch. Thus, FIG. 7 represents a
`preferred embodiment of the circuit of FIG. 1 in most cases.
`In all the cases disclosed herein, each of the Switching
`elements S1, S2, S3 has both an open State and a single
`respective closed State.
`FIG. 9 similarly alters the basic circuit of FIG. 5 into an
`all Supply-rail referenced Switching circuit operated in
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-01161 Page 18 of 24
`
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`accordance with the Switching table shown in FIG. 10. The
`circuit of FIG. 9 has the same advantages over that of FIG.
`5 that the circuit of FIG. 7 has over that of FIG. 1. Hence,
`FIG. 9 depicts an embodiment that is preferred to that of
`FIG. 5 in most cases.
`In both FIG. 7 and FIG. 9, a Switching element S2 can be
`reconnected to the opposing Supply rail (Vr or ground) with
`no change in functionality except for the reset Step. Varia
`tions in Switch configuration, as shown in FIGS. 1 through
`FIG. 5, use the same inventive principles of operation,
`resulting in identical functionality, and are all well within the
`Scope and Spirit of the invention as they do not change the
`fundamental mechanism of Sensing and measurement.
`FIG. 11 shows a unified version of the circuits of FIG. 7
`and 9 and, by inference, the circuits of FIGS. 1 and 5. The
`circuit of FIG. 11 can be operated in several Switch
`Sequences, and the measurement can be made at either
`terminal of the sample capacitor CS. The Switching tables of
`FIGS. 12 and 13 show how the circuit can be made to
`simulate action of any of the circuits of FIGS. 1 though 9.
`Importantly, the plate capacitance, CX can be attached to
`either end of the Sample capacitor, Cs, and the circuit will
`Still function. It is also possible to attach two plate loads,
`CX1 and CX2, and to measure the Sum of both of these
`unknown capacitance values at once.
`The tables of FIGS. 12 and 13 show two possible Switch
`sequences for the circuit of FIG. 11. The function of each
`Switch state with respect to CX1 and CX2 is shown in the
`right two columns of each table. AS can be seen, depending
`on the position of the load, CX, the function of each
`Switching stage can be different. If both Cx1 and CX2 are
`present, both Sets of functions apply simultaneously with
`respect to the respective CX. Steps G and G' of FIGS. 12 and
`13 depict two different ways of measuring the charge,
`depending on whether the Voltage measurement means 14 is
`connected as indicated by the block labeled MSMT CKT1 or
`as indicated by the block labeled MSMT CKT2. Again, it is
`possible to combine the measurement function Specified in
`G or G' with a prior Step, and use a simple Voltage com
`parator circuit along with a cycle counting means to generate
`40
`a value representative of CX, as was explained in conjunc
`tion with FIG. 1 above.
`Several variations of the Switching sequence of FIG. 11
`are permissible and fall well within the scope of the inven
`tion. The inventive aspects of all of FIGS. 1 through 11
`comprise the ability to measure charge transfer through the
`use of a plurality of Switches, none of which is interposed
`between the Sample capacitor, Cs, and the unknown
`capacitance, CX. Moreover, all of the circuits discussed
`Supra are compatible with the use of repetitive QT cycles to
`accumulate charge within Cs, thus increasing uSable gain,
`resolution, and intrinsic noise filtering ability (via the inher
`ent mechanism of charge averaging within CS during the
`burst).
`FIGS. 7 and 9, and by inference FIG. 1 and 5, can be seen
`as parings-down of the circuit of FIG. 11, i.e., versions that
`Simply have the respective unused Switches removed.
`Examples of Superfluous Switching elements include the
`Switch labeled S1 in the Switching sequence of FIG. 13, and
`the Switch labeled S3 in the Switching sequence of FIG. 12.
`In essence, all of FIGS. 1 through 9 are subsets of the circuit
`of FIG 11.
`Turning now to FIG. 14, one finds a variation of FIG. 11
`that uses a shunting resistor, labeled RS, that is electrically
`connected acroSS the Sample capacitor, Cs. In this case, the
`Switches must be cycled for a longer duration, or perhaps
`continuously, to develop a stable Voltage acroSS CS that is
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`representative of the value of CX. In this circuit, the Steady
`State average Voltage developed acroSS RS is given by:
`
`where Vs.<<Vr and f is the frequency of Switch operation.
`In this circuit, unlike in burst-mode QT operation, CS does
`not play a part in determining gain. Here, CS only acts
`to low-pass filter the Voltage Vs. Hence, CS must be
`sized with respect to RS to make Superimposed Voltage
`ripple acroSSRS appropriately low. The use of a resistor
`acroSS CS has the advantage that the measured result is
`dependent on the Stability of the resistor, and not on the
`Stability of Cs. It is generally easier to make Stable
`resistors than to make Stable capacitors, So Some cost
`benefit may arise from the use of a circuit Such as that
`depicted in FIG. 14. However, this circuit will normally
`take longer to acquire Signals than will a pure burst
`mode circuit, because the Voltage acroSS RS rise