DATASHEET
`
`FN9134
`Rev 2.00
`Nov 18, 2005
`
`Features
`• Two Synchronous-Rectified Buck Controllers
`- Voltage Mode Control
`- VIN Range up to 12V
`- VOUT Range from 0.6V to 6V
`- 12V LGATE Drivers; up to 12V Boot Strap for UGATE
`• Switcher References
`- 0.6V Reference for OUT1
`- 3.3V Reference Output for OUT2
`- External Reference Input for OUT2
`- Buffered VTT Reference Output
`• Switcher Clocking
`- Phase Options for Optimal Clock Relationship
`- Resistor-Selectable Switching Frequency (300kHz
`default; Resistor to Ground for 300kHz to 1MHz range)
`- Synchronization-Capable Switching Frequency
`(Connect FS_SYNC to Separate Regulator)
`• Single Linear Controller
`- Drives N-Channel MOSFET
`- 0.6V Reference
`- VIN Range up to 12V
`- VOUT Range from 0.6V to 3.3V
`• 12V and 5V Supplies Required (but optional shunt
`regulator can generate VCC = 5.8V from 12V)
`• Three Independent Soft-Start/Enable Pins
`- Gang Together or Control Independently
`• PGOOD Output Indicates All Outputs Available
`• Thermally Enhanced QFN or TSSOP Package
`• QFN Package:
`- Compliant to JEDEC PUB95 MO-220
`QFN - Quad Flat No Leads - Package Outline
`- Near Chip Scale Package footprint, which improves
`PCB efficiency and has a thinner profile
`• Pb-Free Plus Anneal Available (RoHS Compliant)
`
`ISL6534
`Dual PWM with Linear
`
`The ISL6534 is a versatile triple regulator that has two
`independent synchronous-rectified buck controllers with
`integrated 12V gate drivers (OUT1 and OUT2) and a linear
`controller (OUT3) to offer precision regulation of up to three
`voltage rails. An optional shunt regulator allows 12V only
`operation, when a 5V supply is not available.
`Each controller has independent soft-start and enable
`functions combined on a single pin. A capacitor from each
`SS/EN pin to ground sets the soft-start time, and pulling
`SS/EN below 1.0V disables the controller. The SS/EN pins
`can be controlled independently or they can be ganged
`together to provide complete control of start-up coordination.
`The PGOOD function indicates when all regulators have
`completed their soft-start and provides an indication of short-
`circuit conditions on either switching regulator.
`There are two ways to control the switching frequency of the
`PWM regulators. The default switching frequency is 300kHz
`(FS_SYNC to ground). A resistor from FS_SYNC to ground
`increases the switching frequency (up to 1MHz). Connecting
`the gate signal from another PWM IC synchronizes the
`ISL6534 switchers to the frequency of the other controller.
`This allows independent regulators operating at a common
`frequency to avoid low-frequency beats. The gate drivers for
`DDR mode can be staggered by 90° in order to minimize
`cross-conduction.
`Switcher OUT1 has an internal reference for regulating any
`voltage down to 0.6V. OUT2 has current sinking capability
`and an external reference input allowing convenient
`connection to OUT1 through a resistor divider for DDRAM
`applications. The 3.3V reference pin provides the option for
`independent regulation of OUT2. The linear controller drives
`an external N-Channel MOSFET, making the ISL6534 one of
`the most versatile regulators available.
`Simplified Block Diagram
`
`SS1/EN1
`COMP1
`FB1
`
`SS2/EN2
`REFIN
`FB2
`COMP2
`
`VREF
`
`SS3/EN3
`FB3
`
`OUT1
`PWM CONTROLLER
`
`OUT2
`PWM CONTROLLER
`
`3.3V
`
`OUT3
`LINEAR CONTROLLER
`
`BOOT1
`UGATE1
`LGATE1
`
`BOOT2
`UGATE2
`LGATE2
`
`REFOUT
`PGOOD
`FS/SYNC
`DRIVE3
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Page 1 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`
`Ordering Information
`PART MARKING
`PART NUMBER
`ISL6534CV
`ISL6534CV
`ISL6534CVZ
`ISL6534CVZ (See Note)
`ISL6534CR
`ISL6534CR
`ISL6534CRZ
`ISL6534CRZ (See Note)
`EVAL board
`ISL6534EVAL2
`NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
`termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
`classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
`Add “-T” suffix for tape and reel.
`
`PKG. DWG. #
`M24.173B
`M24.173B
`L32.5x5
`L32.5x5
`
`TEMP. (°C)
`0 to 70
`0 to 70
`0 to 70
`0 to 70
`
`PACKAGE
`24 Ld EPTSSOP (exposed pad)
`24 Ld EPTSSOP (exposed pad) (Pb-free)
`32 Ld 5x5 QFN
`32 Ld 5x5 QFN (Pb-free)
`
`24
`
`23
`
`22
`
`21
`
`20
`
`19
`
`18
`
`17
`
`UGATE1
`
`PGND_1
`
`VCC12_1
`
`LGATE1
`
`LGATE2
`
`VCC12_2
`
`PGND_2
`
`NC
`
`32 LD 5x5 QFN
`TOP VIEW
`
`BOOT1
`
`25
`
`NC
`
`NC
`
`27
`
`26
`
`VCC
`
`28
`
`FB1
`
`29
`
`COMP1
`
`30
`
`COMP2
`
`31
`
`FB2
`FB2
`
`32
`
`GND
`BOTTOM
`SIDE PAD
`
`1 2 3 4 5 6 7 8
`
`REFIN
`
`NC
`
`REFOUT
`
`SS1/EN1
`
`SS2/EN2
`
`SS3/EN3
`
`VREF
`
`DRIVE3
`
`16
`
`BOOT2
`
`15
`
`NC
`
`14
`
`UGATE2
`
`13
`
`GND
`
`12
`
`PGOOD
`
`11
`
`FS_SYNC
`
`10
`
`FB3
`
`9
`
`NC
`
`NOTES:
`1. BOOT2 and UGATE2 are different order in QFN.
`2. NC is No Connect
`
`Pinouts
`
`24 LD EPTSSOP
`TOP VIEW
`
`GND
`BOTTOM
`SIDE PAD
`
`24
`23
`22
`21
`20
`19
`18
`17
`16
`15
`14
`13
`
`VCC
`BOOT1
`UGATE1
`VCC12
`LGATE1
`LGATE2
`PGND
`UGATE2
`BOOT2
`GND
`PGOOD
`FS_SYNC
`
`1 2 3 4 5 6 7 8 9
`
`10
`11
`12
`
`FB1
`COMP1
`COMP2
`FB2
`REFIN
`REFOUT
`SS1/EN1
`SS2/EN2
`SS3/EN3
`VREF
`DRIVE3
`FB3
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Page 2 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`Block Diagram
`
`VCC
`
`VREF
`
`VCC12
`
`VCC5
`
`30µA
`
`VCC5
`
`30µA
`
`VCC5
`
`30µA
`
`3.3V
`
`POWER
`ON
`RESET
`AND CONTROL
`
`VCC5
`
`5.8V
`
`REFERENCE
`BIAS CURRENT
`
`3.3V
`
`0.6V
`
`3.3V
`
`CLOCK AND
`SAWTOOTH
`GENERATOR
`
`PGOOD =
`all 3 SS ramps done
`with no COMP short
`
`0.6V
`
`3.3V
`
`1-2 CLOCK
`CYCLE
`FILTER
`
`MONITOR
`COMP PINS
`FOR SHORTS
`
`IF SHORT > FILTER,
`SHUT DOWN ALL
`3 OUTPUTS
`
`SS1/EN1
`
`SS2/EN2
`
`SS3/EN3
`
`PGOOD
`
`COMP1
`
`FB1
`
`REFIN
`
`FB2
`
`COMP2
`
`OUTPUT1
`DRIVERS
`
`GATE CONTROL
` LOGIC
`
`DEAD-TIME
` CONTROL
`
`OUTPUT2
`DRIVERS
`GATE CONTROL
` LOGIC
`
`DEAD-TIME
` CONTROL
`
`0.6V
`
`BOOT1
`
`UGATE1
`
`LGATE1
`
`BOOT2
`
`UGATE2
`
`LGATE2
`
`FS/SYNC
`
`REFOUT
`
`FB3
`
`DRIVE3
`
`GND
`
`PGND
`
`FIGURE 1. BLOCK DIAGRAM
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Page 3 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`Typical Application, DDRAM Controller
`
`VOLTAGE INPUTS REQUIRED
`VCC12 (12V)
`VCC (5V OR 5.8V FROM SHUNT)
`VIN1, VBS1
`VIN2, VBS2
`VIN3
`
`ISL6534
`DDR MODE
`
`VCC
`
`VCC12
`
`VCC
`
`VCC12
`
`VOUT1
`
`VOUT2
`
`VOUT1 (DDR)
`
`VTTREF
`
`VREF
`
`COMP1
`
`FB1
`
`COMP2
`
`FB2
`
`REFIN
`
`REFOUT
`
`VREF
`
`PGOOD
`
`FS/SYNC
`
`SS1/EN1
`
`SS2/EN2
`
`SS3/EN3
`
`VCC
`
`DDR
`
`ISL6534
`
`BOOT1
`
`UGATE1
`
`LGATE1
`
`BOOT2
`
`UGATE2
`
`LGATE2
`
`DRIVE3
`
`FB3
`
`GND
`
`PGND
`
`VOLTAGE OUTPUTS
`VOUT1
`VOUT2
`VOUT3
`
`OPTIONAL R FOR
`SHUNT REGULATOR
`
`VBS1
`
`VCC12
`
`VIN1
`
`VBS2
`
`VCC12
`
`VIN2 = VOUT1 (DDR)
`OR OTHER
`
`VIN3
`
`VOUT1
`
`VOUT2
`
`VOUT3
`
`NOTE: Not all components are necessary in all applications.
`
`FIGURE 2. TYPICAL APPLICATION, DDRAM CONTROLLER
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Page 4 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`Typical Application, Independent Mode
`
`VOLTAGE INPUTS REQUIRED
`VCC12 (12V)
`VCC (5V OR 5.8V FROM SHUNT)
`VIN1, VBS1
`VIN2, VBS2
`VIN3
`
`ISL6534
`INDEPENDENT MODE
`
`VCC
`
`VCC12
`
`VCC
`
`VCC12
`
`VOLTAGE OUTPUTS
`VOUT1
`VOUT2
`VOUT3
`
`OPTIONAL R FOR
`SHUNT REGULATOR
`
`VBS1
`
`VCC12
`
`VIN1
`
`VOUT1
`
`VOUT2
`
`VREF (IND)
`
`VTTREF
`
`VREF
`
`COMP1
`
`FB1
`
`COMP2
`
`FB2
`
`REFIN
`
`REFOUT
`
`VREF
`
`PGOOD
`
`FS/SYNC
`
`SS1/EN1
`
`SS2/EN2
`
`SS3/EN3
`
`VCC
`
`IND
`
`BOOT1
`
`UGATE1
`
`LGATE1
`
`VBS2
`
`VCC12
`
`ISL6534
`
`BOOT2
`
`VIN2
`
`UGATE2
`
`LGATE2
`
`DRIVE3
`
`FB3
`
`VIN3
`
`VOUT1
`
`VOUT2
`
`VOUT3
`
`GND
`
`PGND
`
`NOTE: Not all components are necessary in all applications.
`
`FIGURE 3. TYPICAL APPLICATION, INDEPENDENT MODE
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Page 5 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`
`Absolute Maximum Ratings
`Supply Voltage (VCC12) . . . . . . . . . . . . . . . . . GND - 0.3V to 14.0V
`Supply Voltage (VCC, separate supply). . . . . . . GND - 0.3V to 5.5V
`Supply Voltage (VCC, shunt regulator) . . . . . . . GND - 0.3V to 6.0V
`UGATE1, UGATE2, BOOT1, BOOT2 . . . . . . . . . GND - 0.3V to 36V
`LGATE1, LGATE2, DRIVE3. . . . . . . . . . . . . . GND - 0.3V to VCC12
`FS_SYNC (through 10k resistor) . . . . . . . . . . . . . GND - 0.3V to 12V
`REFIN, REFOUT, PGOOD, VREF. . . . . . . . . . . GND - 0.3V to VCC
`FB1, COMP1, FB2, COMP2, FB3 . . . . . . . . . . . GND - 0.3V to VCC
`SS1/EN1, SS2/EN2, SS3/EN3. . . . . . . . . . . . . . GND - 0.3V to VCC
`PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to GND + 0.3V
`ESD Rating
`Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1500V
`Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .100V
`Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
`
`Thermal Information
`JC (°C/W)
`Thermal Resistance (Typical, Notes 3, 4) JA (°C/W)
`4
`TSSOP Package . . . . . . . . . . . . . . . . .
`37
`4
`QFN Package. . . . . . . . . . . . . . . . . . . .
`32
`Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
`Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
`Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
`
`Operating Conditions
`Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
`VCC12 Supply Voltage Range (Typical) . . . . . . . . . . . . . 12V ±1.2V
`VCC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . 5V ±0.25V
`VCC Shunt Regulator Voltage Range (Typical) . . . . . . . 5.8V ±0.2V
`
`CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
`device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
`NOTES:
`3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
`Tech Brief TB379.
`4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
`Electrical Specifications Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0°C to 70°C, Unless Otherwise Specified
`PARAMETER
`TEST CONDITIONS
`MIN
`TYP
`MAX
`INPUT SUPPLY POWER
`Input Supply Current (Quiescent)
`
`UNITS
`
`mA
`mA
`mA
`mA
`V
`mA
`V
`V
`V
`V
`
`4
`6
`50
`7
`5.8
`40
`4.23
`4.0
`7.8
`7.3
`
`Input Supply Current (Dynamic)
`
`Shunt Regulator Output Voltage
`Shunt Regulator Current
`Power-On Reset Threshold
`
`SYSTEM ACCURACY
`Output 1 (measured at FB1)
`Output 3 (measured at FB3)
`Output 1 (measured at FB1)
`Output 3 (measured at FB3)
`Min Output Voltage (VOUT1, VOUT2)
`Max Output Voltage (VOUT1, VOUT2)
`OSCILLATOR
`Accuracy
`Frequency
`Adjustment Range
`Sawtooth Amplitude
`Duty-Cycle Range
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`VCC; outputs disabled
`VCC12; outputs disabled
`VCC12; UGATEs, LGATEs CL = 1nF, 300kHz
`VCC; UGATEs, LGATEs CL = 1nF, 300kHz
`40mA current; ~equivalent to 150 resistor VCC to 12V
`150 resistor VCC to 12V
`VCC rising
`VCC falling
`VCC12 rising
`VCC12 falling
`
`5.6
`
`4.15
`3.8
`
`6.0
`
`4.5
`4.15
`
`0.5997 0.6070 0.6142
`VCC = 4.75 to 5.25V; TA = 0°C to 70°C; (Note 5)
`VCC = 4.75 to 5.25V; TA = 0°C to 70°C; (Note 5)
`0.6027 0.6100 0.6173
`VCC = ~5.8V (@ 20mA shunt current); TA = 0°C to 70°C; (Note 5) 0.6027 0.6100 0.6173
`VCC = ~5.8V (@ 20mA shunt current); TA = 0°C to 70°C; (Note 5) 0.6057 0.6130 0.6203
`(Note 9)
`0.6
`(Note 9)
`6.0
`
`FS_SYNC pin to GND
`FS_SYNC pin: resistor to GND; (see Figure 12 for curves)
`(Note 7)
`
`-20
`240
`300
`
`0
`
`300
`
`2.1
`
`20
`360
`1000
`
`87.5
`
`V
`V
`V
`V
`V
`V
`
`%
`kHz
`kHz
`V
`%
`
`Page 6 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`Electrical Specifications Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0°C to 70°C, Unless Otherwise Specified (Continued)
`PARAMETER
`TEST CONDITIONS
`MIN
`TYP
`MAX
`UNITS
`ERROR AMPLIFIER (OUT1 and OUT2)
`Open-Loop Gain
`RL = 10k to ground; (Note 7)
`Open-Loop Bandwidth
`CL = 100pF, RL = 10k to ground; (Note 7)
`Slew Rate
`CL = 100pF, RL = 10k to ground; (Note 7)
`EA Offset
`COMP1/2 to FB1/2; compare to internal VREF/REFIN; (Note 7)
`VCC = 5V; RL = 10k to ground; (may trip short-circuit)
`Maximum Output Voltage
`Output High Source Current
`COMP1/2
`Output Low Sink Current
`COMP1/2
`PROTECTION AND MONITOR
`Undervoltage Threshold (COMP1 and
`COMP2)
`UV Filter Time
`
`3.6
`
`85
`15
`4
`2
`4.1
`-8
`6
`
`3.3
`
`1-2
`
`dB
`MHz
`V/µs
`mV
`V
`mA
`mA
`
`V
`
`clock
`pulses
`V
`
`0.1
`
`0.3
`
`0.6
`3.3
`2
`9
`0.4
`0.4
`
`V
`V
`mV
`V
`mA
`mA
`
`3.307
`
`3.370
`
`V
`
`3.335
`
`0.6
`3.3
`
`0.4
`2.2
`4.7
`
`3.385
`2.0
`
`+2.5
`VCC-
`1.8
`
`+10
`20
`0.48
`
`VCC
`
`V
`mA
`
`mV
`V
`
`V
`V
`mV
`mA
`mA
`µF
`µF
`V
`
`Page 7 of 29
`
`Causes PGOOD to go low; if there for a filter time,
`Implies the COMP pin(s) is out -of-range, and shuts down IC
`Based on internal oscillator clock frequency
`(nominal 300kHz = 3.3µs clock period)
`IPGOOD = 2mA
`
`(As determined by resistor divider into FB3); (Note 8)
`(As determined by resistor divider into FB3); (Note 8)
`DRIVE3 to FB3; compare to internal VREF; (Note 7)
`
`VCC = 4.75 to 5.25V; TA = 0°C to 70°C; (Note 5)
`1.1µF max capacitance
`VCC = ~5.8V (@ 20mA shunt current); TA = 0°C to 70°C; (Note 5) 3.285
`
`3.244
`
`VCC can be external or internal shunt regulator voltage
`
`Determined by REFIN voltage
`Determined by REFIN voltage
`REFIN = 3.3V
`
`External
`External
`To select 0 degree phase; (see Table 1)
`
`-2.5
`0.6
`
`-10
`0.2
`
`PGOOD Low Voltage
`LINEAR REGULATOR (OUT3)
`Min Output Voltage
`Max Output Voltage
`EA Offset
`DRIVE3 High Output Voltage
`DRIVE3 High Output Source Current
`DRIVE3 Low Output Sink Current
`VREF
`Output Voltage
`
`Output Voltage
`Source Current
`REFIN
`Input Offset Voltage
`Common Mode Input Range
`
`REFOUT (VTTREF)
`Min Output Voltage
`Max Output Voltage
`Offset Voltage
`Source Current
`Sink Current
`Min Output Capacitance
`Max Output Capacitance
`Output High Voltage Minimum
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`Electrical Specifications Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0°C to 70°C, Unless Otherwise Specified (Continued)
`PARAMETER
`TEST CONDITIONS
`MIN
`TYP
`MAX
`UNITS
`ENABLE/SOFT-START (SS/EN 1, 2, 3)
`Enable Threshold
`
`EN Rising
`EN falling
`(Note 7)
`ISS
`End of ramp
`To select DDR mode; (see Table 1)
`
`1.05
`0.95
`6
`-30
`3.3V
`4.7
`
`VCC
`
`V
`V
`µs
`µA
`V
`V
`
`Use a 10k series resistor (from LG pin of another IC, for example)
`
`Maximum DC Voltage with respect to GND; also depends upon
`VIN, Phase, VOUT, and threshold of NFET; ringing should not
`exceed max rating of BOOT (36V)
`
`300
`1000
`12
`
`27
`
`kHz
`kHz
`V
`
`V
`
`Noise Immunity (noise de-glitch)
`Soft-Start Current
`Soft-Start High Voltage
`Output High Voltage
`FS/SYNC PLL
`Min Frequency Range of Lock-In
`Max Frequency Range of Lock-In
`Maximum High Voltage
`BOOT PINS (BOOT1, 2)
`High Voltage
`
`UGATE1, UGATE2; DC maximum voltage
`LGATE1, LGATE2; DC maximum voltage = VCC12
`UGATE1, UGATE2 = 3V; BOOT = 12V; IGATE = 100mA
`LGATE1, LGATE2 = 3V; IGATE = 100mA
`UGATE1, UGATE2 = 3V; BOOT = 12V; IGATE = 100mA
`LGATE1, LGATE2 = 3V; IGATE = 100mA
`
`10% - 90%; 2nF Load; BOOT = 12V
`90% - 10%; 2nF Load; BOOT = 12V
`10% - 90%; 2nF Load; BOOT = 24V
`90% - 10%; 2nF Load; BOOT = 24V
`10% - 90%; 2nF Load
`90% - 10%; 2nF Load
`
`GATE DRIVERS
`Output Voltage
`Output Voltage
`Upper Driver Source Resistance
`Lower Driver Source Resistance
`Upper Driver Sink Resistance
`Lower Driver Sink Resistance
`GATE DRIVERS SWITCHING TIME
`UGATE Rise Time
`UGATE Fall Time
`UGATE Rise Time
`UGATE Fall Time
`LGATE Rise Time
`LGATE Fall Time
`NOTES:
`5. Operating range is: 12V ±10%; 5V ±5% for no shunt regulator; 12V ±10%; VCC5 = ~5.8V (approximate shunt voltage at a shunt current of
`20mA). The accuracy specs are slightly different for the two cases.
`6. Thermal comments.
`7. Design guidance only; not production tested.
`8. The maximum output voltage of VOUT3 can go higher than 3.3V, with the proper precautions. These include making sure: the input voltage is
`higher than the desired output, with sufficient current available; the DRIVE3 voltage can go high enough to drive the FET, with an acceptable
`VGS for the load current desired; the FET is chosen and mounted to handle the power dissipation at full load.
`9. The maximum output voltage of VOUT1 and VOUT2 is determined by the following factors: the VIN (usually 12V or less; take into account its
`min and max variation as well); the maximum duty cycle (with a perfect 12V input, that limits the output to 10.5V); the bootstrap voltage used;
`the FETs chosen. Since the upper FET will be on most of the time, it must be sized accordingly. The output capacitors also need to be rated for
`the higher voltage.
`
`27
`13.2
`2
`2
`2.8
`2.8
`
`17
`17
`27
`25
`17
`17
`
`V
`V
`
`
`
`
`
`
`
`
`
`ns
`ns
`ns
`ns
`ns
`ns
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Page 8 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`Pin Description
`VCC
`This power pin supplies bias to the control functions. It can
`be connected to a nominal 5V (±5%) supply, or it can
`function as a shunt regulator (nominal 5.8V), with an
`external pull-up resistor (nominally 150 to 12V).
`GND
`This pin is the signal ground for the IC. The metal thermal
`pad under both packages is connected to the GND potential
`(through the IC substrate; the pad does NOT substitute for
`the GND pin connection). But the GND pin and the metal
`pad should be connected together on the board, and tied to
`a good GND plane (both for electrical and thermal
`conduction). The thermal pad on both packages limits metal
`interconnect traces underneath the package.
`VCC12 (QFN: VCC12_1, VCC12_2)
`This power pin (nominal 12V) supplies the output gate
`drivers, as well as some other control functions.
`The QFN package has two power pins; one for each
`switcher. They are electrically connected internally, but allow
`for separate decoupling caps to better isolate the switching
`noise, if necessary. Even if they share one capacitor, they
`should both be connected externally, for lower resistance.
`PGND (QFN: PGND_1, PGND_2)
`This pin is the Power GND for the gate drive circuits. It is not
`directly tied to GND inside the IC; it should be tied to GND
`on the board.
`The QFN package has two Power GNDs; one local to each
`switcher; both should be connected externally to the GND
`plane on the board.
`SS1/EN1, SS2/EN2, SS3/EN3
`These analog input pins have two functions. A 30µA current
`source charges an external capacitor (to GND), to provide a
`soft-start timing ramp; their respective Output voltage will
`follow the ramp voltage as it powers up. The 2nd function is
`Enable; when the input is left open (with the soft-start cap),
`the respective output will be Enabled after the ramp reaches
`the 1V level. If the input is pulled to a low logic level, the
`output will be disabled.
`SS2/EN2 also has a special mode function; see Table 1.
`Tying it to VCC (5V) selects the DDR mode (where both
`OUT1 and OUT2 share the SS1 ramp); otherwise it will be in
`the Independent mode.
`COMP1, COMP2
`These analog output pins are used to externally compensate
`the error amplifiers for their respective regulators.
`FB1, FB2, FB3
`These analog input pins are used to set their respective
`regulator output voltages. A resistor divider from the output
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`to GND is compared to a reference voltage (0.6V for OUT1
`and OUT3; REFIN pin for OUT2). The compensation
`components also connect to these pins.
`UGATE1, UGATE2
`These output pins provide the gate drive for the upper
`MOSFETs of OUT1 and OUT2 respectively; the voltage
`comes from its bootstrap pin, typically 12V (minus the diode
`drop) above the VCC12 pin.
`LGATE1, LGATE2
`These output pins provide the gate drive for the lower
`MOSFETs of OUT1 and OUT2 respectively; the voltage
`comes from VCC12.
`BOOT1, BOOT2
`These pins feed the bootstrap voltage (externally generated
`with a diode and a capacitor) to the upper MOSFETs,
`through the UGATE pins. Either BOOT pin can be connected
`directly to a power supply instead (but only if the VIN voltage
`of the regulator is sufficiently lower than that supply, such
`that the FETs have enough gate-source voltage).
`REFIN
`This analog input is used as the reference voltage for OUT2
`(the error amplifier compares it to the feedback resistor
`divider at FB2). This voltage is also fed into a buffer, which is
`output on the REFOUT pin. Note from the Electrical
`Specifications Table that there is a common-mode limit for
`this input; in particular, if an external 5V supply is used for
`VCC, then the 3.3V from VREF should not be used directly;
`it should be divided down to avoid running out of headroom.
`REFOUT (VTT Buffer)
`This analog output provides a buffered version of the REFIN
`input, to be used by other IC’s in the system. In the DDR
`mode, where VTT is generated from VDDQ, this output can
`be used as a VTT Buffer.
`In addition, it can be used to select the phase relationship,
`but it disables the buffer in that case (see Table 1). Tying it to
`VCC (5V) selects 0 degrees phase (in either mode); leaving
`it open (where it can also be used as a reference output)
`selects 90 degrees phase (in DDR mode) and 180 degrees
`phase (in Independent Mode). A capacitor to GND is
`recommended for stability (see Application Considerations).
`VREF
`This analog output pin is a 3.3V nominal reference, which
`can be used by this IC (or others) as a voltage reference. A
`capacitor to GND is recommended for stability (see
`Application Considerations).
`DRIVE3
`This pin drives the gate of an external N-Channel MOSFET,
`for OUT3, which is a linear regulator.
`
`Page 9 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`
`PGOOD
`This digital output is an open-drain pull-down device. When
`power is first applied to the IC, the output is pulled low, for
`power “Not Good”. After all 3 soft-start pins complete their
`ramp up with no faults (no short detected on switchers) the
`power is considered “Good”, and the output pin is high-
`impedance (to be pulled up to a logic high level with an
`external pull-up resistor). See the PGOOD section under
`Functional Description for more details.
`FS/SYNC
`This input allows the user to adjust the internal oscillator
`used for the PWM outputs; a pull-down resistor will speed up
`the oscillator; use a 0 resistor (or a trace) to GND to get the
`default 300kHz. In addition, a digital clock signal can be fed
`into this input, in order to SYNC its clock with the external
`one; this allows the clock edges to line up in a way that won’t
`interfere with each other.
`Functional Description
`Overview
`There are two single-phase synchronous buck converters,
`and one linear regulator. Except for a common clock, the two
`PWM regulators are independent. Refer to Figures 2 and 3
`for a quick discussion of the circuit. The right side of the
`diagram shows the 3 output stages with their components;
`each switcher has an upper and lower FET, input capacitor,
`bootstrap diode and capacitor, an LC output filter, and an
`optional snubber.
`The 3rd regulator (OUT3) is a linear, with an external NFET,
`input and output capacitor. The output voltage is divided to
`FB3, and compared to an internal 0.6V reference. An RC is
`used for compensation.
`The left side of the diagrams show the various control and
`programming components. Each switcher has a compensation
`network for stability that includes the output resistor divider.
`VREF and REFOUT can be used as reference voltages. There
`are three SS/EN pins to set the soft-start ramp of each output,
`and a PGOOD output to signal when they are all done. The
`FS_SYNC pin allows options for the oscillator frequency. Each
`of these features will be described in more detail, either in the
`Functional Description or the Application Considerations.
`The first regulator (OUT1) has an internal 0.6V reference. To
`set the output voltage level, connect a resistor divider
`between VOUT1 and FB1.
`The second regulator (OUT2) requires an external reference
`connected to REFIN. For DDR memory applications
`(Figure 2), connect a divide-by-two resistor divider from
`VOUT1 to ground with the center point connected to REFIN.
`This causes VOUT2 to track VOUT1 at one-half its value.
`Connect VOUT2 to FB2 (through the compensation
`resistor). A buffered copy of REFIN is provided on REFOUT.
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`For Independent mode operation on OUT2 (Figure 3), a 3.3V
`reference is provided on VREF which can be used directly (if
`VCC is high enough), or divided down for REFIN. A resistor
`divider from VOUT2 to FB2 sets the output voltage.
`Operational Modes
`Table 1 shows how to select the various modes and phasing
`between the two switching regulators.
`TABLE 1. MODE AND PHASE SELECTION
`EN_SS2 REFOUT
`PWM1/2
`CH1/2
`VCC
`VCC
`0 degree EN1/SS1 enables
`CH1 and CH2
`“
`90 degree
`0 degree EN1/SS1 for CH1;
`EN2/SS2 for CH2
`“
`
`MODE
`DDR
`
`VCC
`DDR
`Independent SS2 cap
`
`Open
`VCC
`
`Independent SS2 cap
`
`Open
`
`180 degree
`
`DDR mode is chosen by connecting the SS2/EN2 pin to
`VCC (5V). In this mode, SS1/EN1 is used to enable and soft-
`start both OUT1 and OUT2 (a single 30µA current source is
`charging a single soft-start capacitor). In addition, VOUT1
`(usually divided by 2) can be used as the REFIN for OUT2.
`VOUT1 is often used as VIN2 (especially when the VOUT2
`current is low enough) although it is not necessary. And
`OUT2 does allow both sinking and sourcing of current for the
`DDR.
`For Independent mode, SS2/EN2 is not connected to VCC.
`Instead it is connected to a soft-start capacitor to GND,
`similar to SS1/EN1. The capacitors will ramp each output
`independently, and each can be turned off by pulling its
`SS/EN pin to GND; releasing will start a new soft-start ramp.
`SS3/EN3 is also independent of the first two. As explained
`earlier, one capacitor can be shared by more than one
`SS/EN pin.
`To select the Phase shift between Channel 1 and 2, the
`REFOUT pin is used. Tie it to the VCC pin to get 0 degrees
`in either mode (which means both switchers are in phase). In
`this case, the REFOUT pin is not available for use
`elsewhere; the buffer is disabled. Leave REFOUT open
`(driven to whatever voltage is supplied at REFIN) and it
`selects 90 degrees in the DDR mode, or 180 degrees in
`Independent mode; REFOUT can be used as a reference in
`this case. The advantage of Phase shift is to keep the
`switching current spikes from lining up to create even higher
`noise, or interaction between the channels; it also reduces
`the RMS current through the input capacitors, allowing fewer
`caps to be employed. However, depending on the VOUT to
`VIN ratios of both, there is no guarantee that opposite edges
`might not line up, depending on the duty cycles; so the user
`should check for that possibility.
`Figure 4 shows the phases. The rising edge of LGATE1
`(LG1) and LGATE2 (LG2) is fixed; the phase difference is
`relative to the rising edges. The falling edge of each is the
`
`Page 10 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`ISL6534
`
`variable one (determined by the duty cycle). LG1 is shown
`with a pulse width shorter than LG2; this is just an arbitrary
`example, and it does not affect the rising edges.
`
`VOUT1 (INDEPENDENT OR DDR MODE)
`
`LG1
`
`VOUT1
`
`R5
`
`COMP1
`
`FB1
`
`R6
`
`EA
`
`0.6V
`
`FIGURE 5. RESISTOR DIVIDER FOR VOUT1 (DDR OR
`INDEPENDENT MODE)
`
`LG2 (0 degree)
`
`LG2 (90 degree)
`
`LG2 (180 degree)
`
`0
`
`90
`
`180
`
`270
`
`0
`
`FIGURE 4. PHASE OF LG2 WITH RESPECT TO RISING EDGE
`OF LG1
`
`Output Regulation
`The basic PWM regulator voltage is usually set up as
`follows: FB and the internal reference are the two inputs to
`the error amplifier, which are forced to be equal. The output
`voltage is externally divided down to the FB pin, to equal the
`reference. In the ISL6534, VOUT1 uses an internal nominal
`0.6V reference; VOUT2 uses an external REFIN pin for the
`reference. There are many variations of the above,
`especially when the modes (Independent or DDR) are also
`considered. Below are some of the cases that can be used,
`along with the advantages or disadvantages of each.
`The following figures show the compensation circuit for
`VOUT1 and VOUT2; they include a full type-3 compensation
`network. Also shown is the resistor divider for REFIN.
`Several notes:
`1. The labeling of the resistors may not match other
`diagrams; they should be used just for the equations
`included.
`2. The VREF pin (nominal 3.3V) is assumed here (the
`VREF pin supplies a soft-start ramp that other external
`sources may not), but any other appropriate fixed voltage
`reference can be used as REFIN for OUT2.
`3. One percent (or better) resistors are typically used for
`these resistor dividers; the overall system accuracy
`depends directly upon them. Exact ratios are not always
`possible, due to the limited values of standard resistors
`available; these errors must also be added to the
`tolerance.
`
`FN9134 Rev 2.00
`Nov 18, 2005
`
`Figure 5 shows the resistors for VOUT1, and the equation
`below shows that R5 and R6 divide VOUT1 down to match
`the 0.6V internal reference. VOUT1 must be greater than
`0.6V and 2 resistors are needed, and their accuracy directly
`affect the regulator tolerance.
`R6
`----------------------
`R5 R6+
`
`FB1
`
`=
`
`VOUT1
`
`
`
`=
`
`R6
`
`Use the following equation to choose the resistor values. R5
`is part of the compensation network, and should be selected
`to be compatible; 1k is a good starting value. Find FB1
`from the Specification Table for the right condition, plug in
`the desired value for VOUT1, and solve for R6.
`FB1 R5
`---------------------------------------
`VOUT1 FB1
`–
`VOUT2 (INDEPENDENT MODE)
`Figure 6 shows the resistors for VOUT2; it is similar to
`VOUT1 in that 2 resistors divide down VOUT2 to FB2; the
`difference is that a second resistor divider may be used to
`divide an external reference REF (such as VREF pin; see
`Specification Table for details) or some other voltage (such
`as VOUT1 for DDR mode).
`Use the following equations; first decide what reference will
`be used (REF), and whether it will be divided down (to
`REFIN); choose a nominal value for R3 (such as 1k and
`solve for R4. Assume a value for R1 (part of the
`compensation calculation); 1k is good starting value. Now
`that REFIN is determined, plug it in for FB2, plug in the
`desired VOUT2, and solve for R4.
`
`R4
`
`=
`
`R2
`
`=
`
`REFIN R3
`--------------------------------------
`REF REFIN
`–
`FB2 R1
`---------------------------------------
`VOUT2 FB2
`–
`
`The same equations are used for following cases; some of
`them get simplified by removing one or both dividers.
`Case 1 is the most general case (no restriction on VREF > or
`< VOUT2), and the most flexible. Both VREF and the output
`are divided down to the same arbitrary reference (in the 0.6V
`
`Page 11 of 29
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-01160
`
`

`

`Three resistors are needed, two of which affect the accuracy.
`Since the DDR mode almost always uses the divide by two,
`no flexibility is lost here; just change the VOUT1 resistor
`divider to change the value of VDDQ, and VOUT2 will still
`track at 1/2 the value.
`Cases 3 and 4 don’t apply for DDR.
`
`Soft-Start/Enable
`Numerous combinations of independent and dependent
`start-up are possible by the various methods of connecting
`the three SS/EN pins; some combinations are shown in
`Figures 7 and 8. In Figure 7, the three regulators enable
`independently and rise at rates selected by their individual
`soft-start capacitors CSS1, CSS2, and CSS3. In Figure 8, two
`diodes are used to connect to a single open-drain pull-down
`device (not shown); this allows one FET to disable both
`channels. When enabled, they will each rise at their own
`ramp rate. If they could use the same ramp rate, then both
`pins could share one capacitor and the one FET, and the
`diodes are not necessary. The 3rd channel is disabled and
`ramped independently.
`Since the EN trip point is around 1V, some care should be
`taken to guarantee the diode drop and the FET in series
`with it will always be below it (including manufacturing
`tolerances, temperature extremes, etc.); schottky diodes,
`with their lower voltage drop, are preferred. Also, beware of
`diodes with high reverse leakage, especially at high
`temperatures. If the pull-down FET also has a pull-up
`resistor to 12V, for example (not recommended), then the
`SS/EN pin could be pulled too high, and interfere with
`normal operation; the voltage on the EN pins should not
`exceed VCC.
`
`ISL6534
`
`SS1/EN1
`
`SS2/EN2
`
`SS3/EN3
`
`OPEN-DRAIN
`LOGIC SIGNALS
`
`EN1
`
`EN2
`
`EN3
`
`CSS1
`
`CSS2
`
`CSS3
`
`FIGURE 7. CONNECTIONS FOR INDEPENDENT ENABLE
`AND SOFT-START
`
`ISL6534
`
`to 3.3V range for best performance). The advantage is that if
`either the VREF or desired output voltage changes going
`forward, the only board change needed is the value of 1 or
`more resistors. The disadvantage is that since there are two
`resistor dividers, both of them add to the error budget of the
`regulator output. The total number of resistors used is 4.
`Case 2 can be used when VOUT2 is less than VREF. R3 and
`R4 divide the reference to match VOUT2. It saves a resistor
`(R2); R1 (usually ~1k) is still needed as part of the
`compensation, but it doesn’t affect the accuracy of the output.
`Three resistors are needed; this is the most