(12) United States Patent
`Askew
`
`USOO6350951B1
`US 6,350,951 B1
`(10) Patent No.:
`*Feb. 26, 2002
`(45) Date of Patent:
`
`(54)
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`(75)
`(73)
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`(21)
`(22)
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`ELECTRIC SHIELDING OF ON-BOARD
`DEVICES
`
`Notice:
`
`Inventor: Ray Askew, Hillsboro, OR (US)
`Assignee: Intel Corporation, Santa Clara, CA
`(US)
`This patent issued on a continued pros
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`Appl. No.: 08/999,089
`Filed:
`Dec. 29, 1997
`
`Int. Cl............................. H01L23/28; H05K 5/06
`
`U.S. Cl. ............... 174/52.2; 174/35 R; 174/35 MS;
`257/659; 257/660; 361/753; 361/799; 361/800;
`361/816; 361/818
`
`Field of Search ................................. 257/659, 660;
`174/35 R, 35MS, 52.2; 361/753, 799,
`800, 816, 818
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,561.265 A 10/1996 Livshits et al.
`5,639,989 A * 6/1997 Higgins, III ........... 174/35 MS
`5,703,761. A 12/1997 Heiss ......................... 361/800
`5,814,882 A
`9/1998 Shimada et al. ............ 257/704
`
`OTHER PUBLICATIONS
`Title 47 Telecommunications, Code of Federal Regula
`tions; vol. 1, Parts 0 to 19; 47CFR 15.107 pp. 655–656, Oct.
`1, 1998.
`Title 47 Telecommunications. Chapter 1 Federal Commu
`nications Commission, Part 15, Radio Frequency Devices.
`Sec. 15.109, Oct. 1, 1993.
`Title 47 Telecommunications. Chapter 1 Federal Commu
`nications Commission, Part 15 Radio Frequency Devices.
`Sec. 15.31, Aug. 7, 1998.
`Title 47 Telecommunications. Chapter 1 Federal Commu
`nications Commission, Part 15 Radio Frequency Devices.
`Sec. 15.32, Aug. 4, 1997.
`U.S. application No. 08/998,615, Askew.
`* cited by examiner
`Primary Examiner William A. Cuchlinski, Jr.
`ASSistant Examiner Ronnie Mancho
`(74) Attorney, Agent, or Firm-Blakely, Sokoloff, Taylor &
`Zafman LLP
`ABSTRACT
`(57)
`Improved electromagnetic compatibility for integrated
`motherboard or device board designs is provided by mag
`netic shielding, electric Shielding, or both integrated into the
`chip packaging materials. Motherboard emissions may be
`reduced by use of the shielding. A nonconductive primary
`and tertiary layer Sandwich a high-conductivity metal Sec
`ondary layer forming a Faraday cage for electric field
`Shielding. A nonconductive primary layer is covered by a
`tertiary layer formed of a composite having permeable
`material for magnetic Shielding. The tertiary layer formed of
`a composite could include a high permeability particulate
`ferrous material. Both the Secondary layer and the tertiary
`layer formed of a composite could be used for both electric
`and magnetic Shielding of chips.
`22 Claims, 5 Drawing Sheets
`
`200
`
`26
`
`
`
`
`
`28
`
`26
`
`(2 2 %.
`2 t7a, NS
`18
`24
`18
`1RNS /N
`
`10
`
`16 14
`
`
`
`12
`
`14
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 001
`
`

`

`U.S. Patent
`
`Feb. 26, 2002
`
`Sheet 1 of 5
`
`US 6,350,951 B1
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`50
`
`
`
`
`
`18
`18
`1SNS /N
`
`10
`
`16 14
`
`12
`
`14
`
`16
`
`20
`
`FIG. 1
`(PRIOR ART)
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 002
`
`

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`U.S. Patent
`
`Feb. 26, 2002
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`Sheet 2 of 5
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`US 6,350,951 B1
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`100
`
`N
`
`
`
`18
`18
`1 ran as /N
`
`27
`6 16 14
`
`12
`
`14
`
`16
`
`FIG. 2
`
`200
`
`
`
`
`
`M
`
`2 2 %
`Arts 10
`27
`18
`41
`18
`1. NNNNNNNN/N 2
`16
`
`
`
`16 14
`
`20
`
`12
`
`14
`
`FIG. 3
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`300
`
`N
`
`
`
`26
`
`22
`
`
`
`26
`
`10
`18 Se
`24-1
`7t 18
`A
`%2.
`1RNS X
`16
`
`
`
`12
`
`14
`
`
`
`16 14
`
`20
`
`FIG. 4
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 003
`
`

`

`U.S. Patent
`
`Feb. 26, 2002
`
`Sheet 3 of 5
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`US 6,350,951 B1
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`START
`
`
`
`COVER DEVICE WITH POLYMERLAYER
`
`COMBINE POLYMERMATERIAL AND
`MAGNETICALLY PERMEABLE MATERIAL TO
`FORM COMPOSITE POLYMERMATERIAL
`
`COVERPOLYMERLAYER WITH LAYER OF
`COMPOSITE POLYMERMATERAL
`
`FIG. 5
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 004
`
`

`

`U.S. Patent
`
`Feb. 26, 2002
`
`Sheet 4 of 5
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`US 6,350,951 B1
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`START
`
`
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`COVER DEVICE WITH POLYMERLAYER
`
`COVER DEVICE WITH A CONDUCTIVE
`FOMATERIAL
`
`COMBINE POLYMERMATERAL AND
`MAGNETICALLY PERMEABLE MATERIAL TO
`FORM COMPOSITE POLYMERMATERIAL
`
`COVER CONDUCTIVE FOILMATERIAL AND
`POLYMERLAYER WITH LAYER OF
`COMPOSTE POLYMERMATERIAL
`
`END
`
`FIG. 6
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 005
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`

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`U.S. Patent
`
`Feb. 26, 2002
`
`Sheet 5 of 5
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`US 6,350,951 B1
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`START
`
`
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`COVER DEVICE WITH FIRST POLYMER
`LAYER
`
`COVER DEVICE WITH CONDUCTIVE FOL
`MATERIAL
`
`COVER CONDUCTIVE FOILMATERIAL AND
`FIRST POLYMER WITH SECOND
`POLYMERLAYER
`
`FIG. 7
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 006
`
`

`

`1
`ELECTRIC SHIELDING OF ON-BOARD
`DEVICES
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The invention relates to packaging of circuit board
`devices, and, in particular, to circuit board device magnetic
`and electric field Shielding.
`2. Discription of Related Art
`Motherboard designers today are faced with tighter elec
`tromagnetic compatibility (“EMC”) regulations than previ
`ously. The Federal Communications Commission (“FCC)
`recently imposed the So-called “open box' electromagnetic
`interference (“EMI”) testing criteria. The open box criteria
`transferS responsibility to the manufacturer for the regula
`tion of computer System (i.e., unintentional radiator's) radi
`ated energy produced by on-board components, Such as
`application specific integrated circuits ("ASICs'), from a
`Shielded enclosure (e.g., a computer case or enclosure)
`housing the components to the internal components
`themselves, Specifically a motherboard. Such emissions,
`which previously could be sufficiently attenuated by the
`shielded enclosure to satisfy the prior “closed box”
`regulations, must now be Sufficiently attenuated without the
`Shielded enclosure being completely closed. The exposed
`motherboard must thereby Satisfy the open box regulations
`without relying on the Shielded enclosure to provide Suffi
`cient attenuation. Otherwise, a given motherboard can only
`be marketed with a particular case if, when closed, the case
`reduces the emissions Sufficiently.
`With the open box criteria, the FCC changed the proce
`dure for testing computer devices for radiated emissions.
`The FCC's regulations were incorporated in amendments to
`$15.32(a)(1) of Title 47 in the Code of Federal Regulations
`(“CFR”). These amendments were adopted for CPU boards
`or motherboards and power Supplies. Because of difficulties
`asSociated with determining the efficacy of Shielding with
`computer cases, the FCC did not adopt rules that authorize
`these enclosures. To ensure that computer Systems
`assembled from modular components comply with the tech
`nical Standards, the FCC adopted a two-step test procedure
`for authorizing the motherboards. The motherboard must
`first be tested when installed in a typical enclosure but with
`the enclosure's cover removed So that the internal circuitry
`is exposed at the top and on at least two Sides of the
`enclosure. Other components, including a power Supply,
`peripheral devices, and Subassemblies are to be added, as
`needed, to complete the personal computer System. If the
`oscillator and the microprocessor circuits of the computer
`System are contained on Separate circuit boards, both boards
`must be used in the test. Under this test procedure, radiated
`emissions from the System may be no more than 6 decibels
`(“dB”) above the limits specified in S15.109. These limits
`are shown in Table I below.
`
`TABLE I
`
`Field Strength Limits for Unintentional
`Radiators at a Distance of 3 Meters
`
`Frequency of Emission
`(MHz)
`30-88
`88-216
`
`Field Strength
`(microvolts/meter)
`1OO
`150
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`US 6,350,951 B1
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`2
`
`TABLE I-continued
`
`Field Strength Limits for Unintentional
`Radiators at a Distance of 3 Meters
`
`Frequency of Emission
`(MHz)
`216-960
`>960
`
`Field Strength
`(microvolts/meter)
`2OO
`500
`
`The testing is to be performed in accordance with the
`procedures Specified in the measurement Standards of
`S15.31. If the initial test shows that the open box computer
`system exceeds 6 dB above the limits shown in Table I, a
`further test is performed using the same configuration, but
`with the enclosure completely closed with all covers
`installed. Under these test conditions, the computer System
`under test shall not exceed the radiation limits Specified in
`S15.109 of the rules. However, if the first test demonstrates
`that the computer System is in compliance with the radiation
`emission standards in S15.109, it is not required that the
`additional test be performed. The system must also be tested
`for compliance with the AC power line conducted limits as
`Specified in S15.107, in accordance with the Specified pro
`cedures in S15.31. If emissions greater than 6 dB above the
`limits can be identified and documented as originating from
`components other than the motherboard, then these emis
`Sions may be dismissed.
`The test procedure of $15.32(a)(1) must be passed. Pass
`ing the first of the above tests, but failing the Second,
`Signifies a noncompliant product. If compliance cannot be
`demonstrated under the Second test, then an alternative
`testing procedure is available in which the motherboard may
`be tested for compliance within the limits of $15.109 using
`a specified enclosure with the cover installed. Such testing
`must also be in accordance with the procedure Specified in
`S15.31 and the motherboard that complies with the limits of
`S15.109 must be marketed together with the specific enclo
`Sure used for the test.
`
`PRIOR ART
`Reference is now made to FIG. 1 which shows a system
`50 for encapsulating or covering a conventional device 12
`(e.g., a chip) on a device board (e.g., a component board, a
`circuit board, a printed circuit board or PCB, a CPU board,
`a motherboard, and the like) known in the art. The encap
`Sulation is integrated into the device packaging materials.
`One exemplary type of board that the device board could be
`is the motherboard of a computer system. In FIG. 1 the
`device board includes a Surface 10 on which the device 12
`is mounted as is well known in the art. The device 12 may
`be an integrated circuit component (or Silicon die). The
`device 12 could be an ASIC, for example, a clock Source, in
`addition to other types of devices. The device 12 may be
`coupled to conductive leads or components (not shown) by
`bond wires 14 through contacts 16 and 18 on or in the
`surface 10 and the device 12, respectively. The contacts 18
`may be conductive contacts, ohmic contacts, Schottky bar
`rier contacts, and the like, depending on the Specific imple
`mentation of the system 50.
`A "primary layer 20 typically covers or encapsulates the
`device 12, the bond wires 14, and the contacts 16 and 18.
`However, due to other factors, for example, air bubbles or
`other imperfections, or by design, the primary layer 20 may
`only cover a portion of the device 12, the bond wires 14, and
`the contacts 16 and 18. The primary layer 20 is nonconduc
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`Momentum Dynamics Corporation
`Exhibit 1013
`Page 007
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`

`

`5
`
`3
`tive and is formed from an industry Standard encapsulant
`that is typically chemically resistant and thermally stable.
`The primary layer 20 may be, for example, an epoxy creSol
`novolac polymer (provided by Plaskon Singapore a division
`of Amoco Chemical), Shinetsu, Nitto Denko, or others), or
`other polymer. Such nonconductive polymers are typically
`used in packaging material for integrated circuits, and they
`may be composite polymer matrix materials having various
`components. The primary layer 20 Serves to protect the
`device 12 from possible oxidation, and to help maintain the
`structural integrity of the device 12, the bond wires 14, and
`the contacts 16 and 18, as is known in the art. However, the
`primary layer 20 offers no magnetic Shielding or electric
`shielding for the device 12 of emitted (or received) radiated
`energy, and will not aid a given System in achieving com
`15
`pliance with the FCC open box regulations.
`Thus, a need exists to Shield device board components
`using device-appropriate Shielding to facilitate compliance
`with the open box regulations instituted by the FCC. In the
`long term, this could simplify and reduce the cost of
`enclosing computer Systems, perhaps allowing the use of
`plastic or other casing not constructed of conductive mate
`rial.
`
`SUMMARY OF THE INVENTION
`In one aspect of the invention, a System 50 encapsulating
`a device on a device board having a ground is provided. The
`System includes a first polymer layer that covers a portion of
`the device and a conductive material that covers a portion of
`the first polymer layer and is coupled to the ground. The
`System also includes a Second polymer layer that covers a
`portion of the first polymer layer and the conductive mate
`rial.
`In another aspect of the invention, a method of encapsu
`lating a device on a device board having a ground is
`provided. The method includes covering a portion of the
`device with a first polymer layer and covering a portion of
`the first polymer layer with a conductive material coupled to
`the ground. The method also includes covering a portion of
`the conductive material and the first polymer layer with a
`Second polymer layer.
`BRIEF DESCRIPTION OF THE DRAWINGS
`Other objects and advantages of the invention will
`become apparent upon reading the following detailed
`description and upon reference to the drawings in which:
`FIG. 1 is a prior art System of encapsulating a device on
`a device board;
`FIG. 2 is a system in accordance with a first embodiment
`of the invention;
`FIG. 3 is a system in accordance with a second embodi
`ment of the invention;
`FIG. 4 is a system in accordance with a third embodiment
`of the invention; and
`FIGS. 5-7 are flowchart representations of methods in
`accordance with embodiments of the invention.
`While the invention is susceptible to various modifica
`tions and alternative forms, specific embodiments thereof
`have been shown by way of example in the drawings and are
`herein described in detail. It should be understood, however,
`that the description herein of Specific embodiments is not
`intended to limit the invention to the particular forms
`disclosed, but on the contrary, the intention is to cover all
`modifications, equivalents, and alternatives falling within
`the Spirit and Scope of the invention as defined by the
`appended claims.
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`US 6,350,951 B1
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`4
`DETAILED DESCRIPTION OF SPECIFIC
`EMBODIMENTS
`
`Illustrative embodiments of the invention are described
`below. In the interest of clarity, not all features of an actual
`implementation are described in this specification. It will of
`course be appreciated that in the development of any Such
`actual embodiment, numerous implementation-Specific
`decisions must be made to achieve the developerS Specific
`goals, Such as compliance with System-related and busineSS
`related constraints, which will vary from one implementa
`tion to another. Moreover, it will be appreciated that Such a
`development effort might be complex and time-consuming,
`but would nevertheless be a routine undertaking for those of
`ordinary skill in the art having the benefit of this disclosure.
`First Embodiment
`Reference is now made to FIG. 2, which shows a system
`100 for encapsulating the device 12 on the surface 10 of a
`device board (i.e., the device 12 may be an on-board device)
`in accordance with a first embodiment of the invention. The
`system 100 is somewhat similar to the system 50 except for
`the provision of a Secondary layer 22 that encapsulates or
`covers completely, or covers a portion of (e.g., a Substantial
`portion of), the primary layer 20. Covering only a portion
`may be due to, for example, air bubbles, imperfections, or it
`may be done by design. However, for Shielding purposes,
`complete or Substantial covering, as understood by those
`skilled in the art in the context of the present invention, may
`be desirable to maximize shielding. (This discussion of
`covering applies to all embodiments of the present
`invention, and for any type of covering layer, not just those
`of the first embodiment.) The secondary layer 22 may be a
`composite material, for example, a composite made of an
`industry Standard encapsulant, Such as the epoxy creSol
`novolac polymer, which is impregnated with magnetically
`permeable material particles. A high percentage of the total
`Volume or mass of the Secondary layer 22 may be composed
`of these permeable particles, which may have a high mag
`netic permeability. Examples of high permeability material
`include ferrous materials, Such as ferrite (a mixture of ferric
`oxide and oxides of other metals, Such as manganese, nickel,
`Zinc, and the like). A natural form of ferrite is hematite.
`Other high permeability material particles could be used.
`In regions external to or outside the Secondary layer 22 (or
`outside the device 12 or the device board), for example, at
`3 meters distance, the Strength of the magnetic field, whose
`flux lines may emanate from the device 12, will be reduced
`because of the presence of the high permeability particles in
`the Secondary layer 22. A relatively large portion of the
`energy of these magnetic fields may be used to align the
`dipoles of the permeable particles in the Secondary layer 22,
`and the magnetic flux lines will tend to be contained within
`the permeable material in the Secondary layer 22. The
`tertiary layer 22 will also function to shield the device 12
`from external magnetic fields derived from other Sources for
`Similar reasons. In making the composite material for the
`Secondary layer 22, the proportion of permeable particles to
`polymer material, and the thickness of the resulting Second
`ary layer 22 may be designed specifically to reduce magnetic
`field Strength due to the device 12 in regions external to the
`Secondary layer 22. It is understood that this proportion and
`this thickness, which are determinable in the art, would be
`at least Sufficient to bring about a reasonable reduction in
`magnetic field strength external to the System 100 (e.g., to
`prevent harmful effects on other Systems or people), and
`could be capable of complying with any anticipated future
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 008
`
`

`

`US 6,350,951 B1
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`S
`regulations that may be instituted regarding external mag
`netic field Strength.
`Second Embodiment
`Referring now to FIG. 3, a system 200 is shown in
`accordance with a Second embodiment of the invention. The
`system 200 is somewhat similar to the system 100, but the
`system 200 does not include a secondary layer like 22.
`Instead, the system 200 includes a secondary layer 24 that is
`electrically conductive, and may be highly conductive. The
`Secondary layer 24 is adjacent or layered on the primary
`layer 20 encapsulant, and may completely cover, or cover
`only a portion of, the layer 20. The secondary layer 24 also
`includes conductive Shielding contacts or Sections 26
`coupled to the contact 16 which, in turn, are coupled to a
`device board ground (not shown in Specific detail). The
`device contact 18 may also be coupled via the bond wire 14
`to the device board ground. An encapsulant layer 28 is
`included that is adjacent or layered on (and covers all of, or
`a portion of, e.g., a Substantial portion of) the Secondary
`layer 24 and the primary layer 20, Such that the Secondary
`layer is disposed between the encapsulant layer 28 and the
`primary layer 20. The layer 28 differs from the secondary
`layer 22 in the system 100 in that it contains no permeable
`particles. The layer 28 may be nonconductive, and it may be
`made from the same polymer material as is used in the
`primary layer 20, or it could be different.
`The Secondary layer 24 functions as a Faraday cage to
`effect electric shielding of radiated energy from the device
`12 and reduce electric field strength in regions outside (e.g.,
`at 3 meters distance) the Secondary layer 24 (or the device
`12 or the device board). Faraday cages, as known in the art,
`are used to shield electric fields. The Secondary layer 24 may
`likewise shield the device 12 from electric fields from
`Sources external to the system 100.
`The Secondary layer 24 may be made out of an electrically
`conductive metal or metal alloy (e.g., it may be a good
`conductor). Exemplary materials for the Secondary layer 24
`could be copper, gold, aluminum, or the like. These mate
`rials could be used in the form of foil material. ASSuming
`that copper is used for the material of the Secondary layer 24,
`an exemplary foil thickness of approximately 10 microns
`(s10 meters) may be sufficient to attenuate most radiated
`electric field energy at or above 100 MHZ emanating from
`the device 12. The thickness Sufficient to attenuate the
`energy at 100 MHZ can be determined using the standard
`relationship between Skin depth and frequency known in the
`art: 8=(t?uo)" meters, where 8 is the skin depth, f is the
`radiated energy temporal frequency, and it is the magnetic
`permeability and O is the electrical conductivity of copper.
`Because the skin depth for copper foil is approximately 6.1
`microns at 100 MHz, as determined by the above
`relationship, a thickness of approximately 10 microns (i.e.,
`a thickness approximately the skin depth plus an additional
`fraction of the skin depth of the conductive material forming
`the Secondary layer 24) should accommodate the currents
`induced by a majority of the frequencies shown in Table I
`higher than, as well as lower than, 100 MHz. To accommo
`date currents induced by even lower frequencies than the
`frequencies shown in Table I, the thickness of the Secondary
`layer 24 could be further increased. The resulting reduction
`in radiated electric field Strength due to the Secondary layer
`24 being present may be Sufficient to bring the device board,
`onto which the system 200 is integrated, into compliance
`with the FCC regulations discussed above. Appropriate foil
`thickneSS and properly designed packaging of the device 12
`should assure Such compliance.
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`Third Embodiment
`Referring now to FIG. 4, a system 300 is shown in
`accordance with a third embodiment of the invention. The
`system 300 incorporates all the functionality of, and similar
`features to, both the systems 100 and 200 shown in FIGS. 1
`and 2. The system 300 includes a primary layer 20' (similar
`to the primary layer 20), a secondary layer 24' (similar to the
`Secondary layer 24), and a tertiary layer 22" (similar to the
`secondary layer 22 in system 100). The secondary layer 24
`is adjacent or layered on (completely covering, or covering
`a portion of, e.g., a Substantial portion of) the primary layer
`20', analogous to the layering of the Secondary layer 24 on
`the primary layer 20 in the system 200. Moreover, the
`tertiary layer 22' is adjacent or layered on (completely
`covering, or covering a portion of, e.g., a Substantial portion
`of) the Secondary layer 24', Such that the Secondary layer is
`disposed between the tertiary layer 22 and the primary layer
`20', analogous to the layering of the encapsulant layer 28 on
`the secondary layer 24 in the system 200. Such a configu
`ration as the system 300 would be designed to be sufficient
`to reduce electrical energy radiating from the device 12 (e.g.,
`at 3 meters distance) to bring the device board, onto which
`the system 300 is integrated, also into compliance with the
`open box regulations discussed above, as well as to reduce
`the magnetic field strength outside the system 300.
`Any of the systems 100, 200, or 300 described above
`could be used in implementations that have highly Suscep
`tible ASICS as the device 12, Such as Super input/output
`ASICs (SIOs) with real-time clocks (RTCs), or other types
`of devices. These implementations could be made more EMI
`resilient without the addition of complicated and expensive
`Secondary Shielding hardware, Such as hermetically Sealed
`metal Faraday cages like those used for components in
`military applications, as Specified in military Specifications.
`Method Embodiments
`In the present invention, for any foregoing discussion
`about covering layers with polymer layers and for any Such
`discussion that follows, it is assumed that the polymer layers
`may be cured by any known technique, for example, with
`temperature, with chemicals, with ultraViolet light, etc. It
`may be possible that any polymer curing process that would
`be used in the present invention would also help with the
`adherence or attachment of the conductive foil layer in the
`systems 200 and 300, for example to the layers 20 and 28,
`or 20' and 22". Moreover, in the present invention, as
`discussed herein, covering a layer or layering on a layer
`includes the possibility that only a portion of the item being
`covered or layered on is actually covered (i.e., the covering
`may not be complete), due to, for example, imperfections, or
`by choice. Various methods of the present invention will
`now be discussed with reference to FIGS. 5–7.
`Referring to FIG. 5, a flowchart representation is shown
`of a method of encapsulating a device (e.g., the device 12)
`on a device board (e.g., on the surface 10 in the system 100),
`in accordance with an embodiment of the invention. At
`block 102, a first portion of the device is covered with a
`polymer layer (e.g., the primary layer 20, which may be an
`epoxy), said device being completely covered, or in the
`alternative, only Substantially covered, leaving no com
`pletely covered device. At block 104, a polymer material and
`a magnetically permeable material are combined (i.e., mixed
`together using known techniques in the art, for example, the
`mixing of ferrous particles and polymerS is well known in
`the art of electrophotography) to form a composite polymer
`material. At block 106, the polymer layer is covered with a
`
`Momentum Dynamics Corporation
`Exhibit 1013
`Page 009
`
`

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`US 6,350,951 B1
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`layer of the composite polymer material (e.g., the Secondary
`layer 22 which may be a composite of epoxy and magneti
`cally permeable particles).
`Referring now to FIG. 6, a flowchart representation is
`shown of a method of encapsulating a device (e.g., the
`device 12) on a device board (e.g., on the surface 10 in the
`system 300) having a ground in accordance with another
`embodiment of the invention. At block 202, a portion of
`device is covered with a polymer layer (e.g., the primary
`layer 20), leaving a second portion uncovered. At block 204,
`the device is covered (e.g., also covering the first polymer
`layer) with a conductive foil material (e.g., the Secondary
`layer 24). The covering of the device may include attaching
`the conductive foil material to the first polymer layer and
`coupling the conductive foil material to the ground. At block
`206, a polymer material (e.g., an epoxy) and a magnetically
`permeable material (e.g., ferrous particles) may be com
`bined to form a composite polymer material, and at block
`208, the conductive foil material and the polymer layer may
`be covered with a layer of the composite polymer material
`(e.g., the tertiary layer 22).
`Referring now to FIG. 7, a flowchart representation is
`shown of a method of encapsulating a device (e.g., the
`device 12) on a device board (e.g., on the surface 10 in the
`system 300) having a ground. At block 302, a first portion of
`the device is covered with a first polymer layer (e.g., the
`primary layer 20 which may be an epoxy), Said device being
`completely covered, or in the alternative, only Substantially
`covered, leaving no completely covered device. At block
`304, the device is covered with a conductive foil material
`(e.g., the Secondary layer 24). The covering of the device
`may include attaching the conductive foil material to the first
`polymer layer and coupling the conductive foil material to
`the ground. At block 306, the conductive foil material and
`the first polymer layer may be covered with a Second
`polymer layer (e.g., the encapsulant layer 28 which may be
`an epoxy).
`The particular embodiments disclosed above are illustra
`tive only, as the invention may be modified and practiced in
`different but equivalent manners apparent to those skilled in
`the art having the benefit of the teachings herein.
`Furthermore, no limitations are intended to the details of
`construction or design herein shown, other than as described
`in the claims below. It is therefore evident that the particular
`embodiments disclosed above may be altered or modified
`and all Such variations are considered within the Scope and
`Spirit of the invention. Accordingly, the protection Sought
`herein is as set forth in the claims below.
`What is claimed is:
`1. A System encapsulating a device on a device board
`having a ground, comprising:
`a first polymer layer covering and in contact with the
`device;
`a conductive material coupled to the ground and adjacent
`the first polymer layer; and
`a non-permeable encapsulant layer adjacent Said conduc
`tive material and in contact with both Said conductive
`material and Said first polymer layer.
`2. The system of claim 1, wherein the first polymer layer
`comprises nonconductive material.
`3. The system of claim 1, wherein the first polymer layer
`comprises a composite matrix material.
`4. The system of claim 1, wherein the first polymer layer
`comprises epoxy creSol nonvolac polymer.
`5. The system of claim 1, wherein said non-permeable
`encapsulant layer comprises nonconductive material.
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`6. The System of claim 1, wherein the device comprises an
`integrated circuit coupled to the device board by bond wires.
`7. The system of claim 6, wherein the integrated circuit
`comprises a Silicon die.
`8. The system of claim 1, wherein the first polymer layer
`covers a Substantial portion of the device.
`9. The system of claim 1, wherein said non-permeable
`encapsulant layer covers a Substantial portion of the con
`ductive material and the first polymer layer.
`10. The system of claim 1, wherein the conductive mate
`rial comprises foil material.
`11. The system of claim 1, wherein the conductive mate
`rial covers a Substantial portion of the first polymer layer.
`12. The system of claim 1, wherein the conductive mate
`rial forms a Faraday cage.
`13. The system of claim 1, wherein the conductive mate
`rial provides electric Shielding.
`14. A method of encapsulating a device on a device board
`having a ground, the method comprising:
`covering the device Substantially with a first polymer
`layer, wherein the first polymer layer is in contact with
`the device;
`covering a portion of the first polymer layer with a single
`conductive material coupled to the ground; and
`covering a portion of the Single conductive material and
`the first polymer layer with a nonconductive encapSu
`lant layer in contact with both Said Single conductive
`material and Said first polymer layer.
`15. The method of claim 14, wherein covering a portion
`of the Single conductive material comprises encapsulating
`the device.
`16. The method of claim 14, wherein covering a portion
`of the Single conductive material comprises covering the
`device with epoxy.
`17. The method of claim 14, wherein covering the portion
`of the first polymer layer comprises covering with a foil
`material.
`18. The method of claim 14, wherein covering the portion
`of the first polymer layer comprises covering the portion of
`the first polymer layer to provide electric Shielding.
`19. The method of claim 14, wherein covering the portion
`of the first polymer layer comprises covering a Substantial
`portion of the first polymer layer with the Single conductive
`material.
`20. The method of claim 14 wherein covering the portion
`of the Single conductive material and the first polymer layer
`comprises covering a Substantial portion of the conductive
`material and the first polymer layer with Said nonconductive
`encapsulant layer.
`21. The method of claim 14, wherein covering the portion
`of the first polymer layer comprises covering the portion of
`the first polymer layer with the Single conductive material to
`provide a Faraday cage.
`22. A System encapsulating a device on a device board
`having a ground comprising:
`a first polymer layer covering and in contact with a
`portion of the device;
`a grounded conductive material covering a portion of the
`first polymer layer, the grounded conductive material
`being a foil material; and
`a Second polymer layer covering and in contact with