I IIIII IIIIIIII II llllll lllll lllll lllll lllll lllll lllll lllll 1111111111111111111
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`US 20020027249Al
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`(19)United States
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`(12)Patent Application Publication
`(10) Pub. No.: US 2002/0027249 Al
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`(43) Pub. Date: Mar. 7, 2002
`Takemura
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`(54)SEMICONDUCTOR DEVICE AND METHOD
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`FOR FORMING THE SAME
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`Priority Data(30) Foreign Application
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`(76)Inventor: Yasuhiko Takemura, Kanagawa (JP)
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`Jun. 9, 1992 (JP) ............................................. 4 174883
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`Publication Classification
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`Correspondence Address:
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`NIXON PEABODY, LLP
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`8180 GREENSBORO DRIVE
`SUIT E 800
`MCLEAN, VA 22102 (US)
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`(21)Appl. No.:09/983,366
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`......................... HOlL 27/148 (51)Int. Cl.7 HOlL 27/01;
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`........................... 257/350; 257/365; 257/245 (52)U.S. Cl.
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`(57)
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`ABSTRACT
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`(22) Filed: Oct. 24, 2001
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`In a field effect type device having a thin film like active
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`layer, there is provided a thin film like semiconductor device
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`including a top side gate electrode on the active layer and a
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`bottom side gate electrode connected to a static potential, the
`(60)
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`Division of application No. 09/237,854, filed on Jan.
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`bottom side gate electrode being provided between the
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`27, 1999, which is a division of application No.
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`active layer and a substrate. The bottom side gate electrode
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`08/351,135, filed on Nov. 30, 1994, now Pat. No.
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`may be electrically connected to only one of a source and a
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`5,917,221, which is a continuation of application No.
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`drain of the field effect type device. Also, the production
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`08/072,127, filed on Jun. 7, 1993, now abandoned.
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`methods therefor are disclosed.
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`Related U.S. Application Data
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`Samsung Electronics Co., Ltd. v. Demaray LLC
`Samsung Electronic's Exhibit 1027
`Exhibit 1027, Page 1
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`Patent Application Publication Mar. 7, 2002 Sheet 1 of 6
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`US 2002/0027249 Al
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`A
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`FIG 1A)“GZV7
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`Ex. 1027, Page 2
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`Ex. 1027, Page 2
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`Patent Application Publication Mar. 7, 2002 Sheet 2 of 6
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`US 2002/0027249 Al
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`FIG. 3{A)
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`FIG. 3(B)
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`Vo Vs
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`Vo
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`Vo > Vs
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`Vo <Vs
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`FIG. 3(C)
`Vo <Vs
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`FIG. 3(D)
`Va >Vs
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`Vp> Vs
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`Vp> Vs
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`FIG. 3(E)
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`FIG. 3(F)
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`V6 < Vo
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`to
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`Vo> Vo
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`Vo < Vs
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`FIG. 3G)
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`F 1G. 3(H)
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`Va <Vs
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`Ex. 1027, Page 3
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`Ex. 1027, Page 3
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`Patent Application Publication Mar. 7,2002 Sheet 3 of 6
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`FIG. 4
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`US 2002/0027249 Al
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`V6 < Vs
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`V6> Vs
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`Vs < Vo
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`WILLA N-TYPE
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`REGION
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`Vs < Vo
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`(mm ~=WEAK INVERSION
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`REGION
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`DEPLETION REGION
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`INVERSION REGION
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`Ex. 1027, Page 4
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`Ex. 1027, Page 4
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`Patent Application Publication Mar. 7, 2002 Sheet 4 of 6
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`US 2002/0027249 Al
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`FIG. 5(A)
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`E
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`a
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`23
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`FIG. S(F)
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`FIG. 5(B)
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`FIG. 5(C)
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`FIG. 5(D)
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`FIG. 5(E)
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`Ex. 1027, Page 5
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`Ex. 1027, Page 5
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`Patent Application Publication Mar. 7,2002 Sheet 5 of 6
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`FIG. 6(A)
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`US 2002/0027249 Al
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`Vin
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`FIG. 6(B)
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`FIG. GC)
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`6]
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`63
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`FIG. 6(D)
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`——“6 —|
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`FIG. 6(E)
`FIG. 6(F)
`WYLi =tert
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`Y
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`Ex. 1027, Page 6
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`Ex. 1027, Page 6
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`Patent Application Publication Mar. 7,2002 Sheet 6 of 6
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`US 2002/0027249 Al
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` fflLLAALS
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` FIG. 7(B)
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` FIG.
`FIG.
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`|_|—aNSSBSNee aryayater
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`FIG. T(E)
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`y77 eaWSS
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`Ex. 1027, Page 7
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`Ex. 1027, Page 7
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`US 2002/0027249 Al
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`Mar. 7, 2002
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`SEMICONDUCTOR DEVICE AND METHOD FOR
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`FORMING THE SAME
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`BACKGROUND OF THE INVENTION
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`siderably limited by an inherent capacitance between the
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`substrate and wirings. In contrast, since the TFT is located
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`on the insulation substrate, such a limitation is no longer
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`needed and a considerably high speed operation is expected.
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`[0009] Also, it is possible to obtain PTFTs as well as
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`NTFTs from polycrystal silicon, and henceit is possible to
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`form a CMOScircuit thereby. For example,
`in a liquid
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`crystal display device, a so-called monolithic structure is
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`known in which not only active matrix portions but also
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`peripheral circuits (such as drivers or the like) are formed by
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`polycrystal CMOS TFTs. This point is noticed also in the
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`TFTs used in the aforesaid SRAMS. In this case, PMOSsare
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`formed by TFTs and are used as a loadtransistor.
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`[0010] However, in general, the polycrystal TFTs have an
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`increased leak current and a poor performance of holding the
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`electric charge of image elements of the active matrix since
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`the electric field mobility of the polycrystal TFTs is larger
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`than that of amorphous TFTs. For example,
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`where the polycrystal TFTs are used as the liquid crystal
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`display elements, since conventionally, the size of the image
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`elements is several hundreds of micrometers square and the
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`image element capacities are large,
`there have been no
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`serious problems. Howeverrecently,the fine image elements
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`have been used in accordancewith a high resolution, and the
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`image element capacities become small. The conventional
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`image elements would be insufficient for stable static dis-
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`[0011] There have been several solutions for the current
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`leakage problemsinherent in such polycrystal TFTs. One of
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`the methodsis to thin an active layer. It is reported that the
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`OFFcurrent would be small by the method. For instance, it
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`is known that a thickness of the active layer is 25 nm
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`whereby the OFF current might be less than 1071%A. It
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`would be however very difficult to crystallize a thin semi-
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`conductor film and it is actually known that the thin semi-
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`conductor film could not easily be crystallized.
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`[0012] The method in which the active layer is thinned
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`leads to the phenomenon in which a source/drain region is
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`that the source/drain region is produced simultaneously with
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`the formation of the active layer in accordance with a
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`conventional production method and the source/drain region
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`and the active layer have the same thickness. This would
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`region.
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`[0013] For this reason, a method is used in which a
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`thickness of almostall the source/drain region is increased.
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`This means that a mask processis additionally used. Thisis
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`undesired from the view point of productive yield.
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`[0014] Also, according to the present inventors’ knowl-
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`edge, in the TFT’s where a thicknessof the active layer is 50
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`nm or less, a MOSthreshold voltage is largely shifted, and
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`this phenomenon is remarkable in case of NMOS’s. The
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`threshold voltage would be zero or negative values. If, thus,
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`the CMOSis formed by the TFTs, the operation would be
`unstable.
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`[0001]
`1. Field of the Invention
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`[0002] The present invention relates to an insulation gate
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`type semiconductor device such as a thin film transistor
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`(TFT) having a thin film active layer (ie., an activated
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`region or a channel region) formed on an insulation sub-
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`strate. A field to which the invention pertains is a semicon-
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`ductor integrated circuit, a liquid crystal display device, an
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`optical reading device or the like.
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`2. Description of the Prior Art
`[0003]
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`[0004] Recently, researches and developments have been
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`made as to insulation gate type semiconductor devices
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`having thin film active layers on insulation substrates. In
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`particular, continuous efforts have been made on so-called
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`thin film transistors (TFTs). These TFTs are intended to be
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`used for controlling respective image elements of matrix
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`structure in a display device such as an LCD. Depending
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`upon a material to be used and a crystalline condition of the
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`semiconductors, TFTs are classified into amorphoussilicon
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`TFTs and polycrystal silicon TFTs. However, recently, a
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`material having an intermediate condition betweenthe poly-
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`crystalline condition and amorphous condition has been
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`studied. This is called a semi-amorphous condition and is
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`considered as a condition where small crystals are floated on
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`an amorphous formation.
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`[0005] Also, in a single crystal silicon IC, a polycrystal
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`silicon TFT is used as a so-called SOI technique. For
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`instance, this is used as a load transistor in a highly inte-
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`grated SRAM. However,in this case, an amorphoussilicon
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`TFTis hardly used.
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`[0006]
`In general, an electric field mobility of a semicon-
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`ductor under the amorphous condition is small, and it is
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`therefore impossible to use the semiconductor as TFTs
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`which need high speed operation. Also, in the amorphous
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`silicon, the electric field mobility of P-type is small, and it
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`is impossible to produce a P-channel type TFT (TFT of
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`PMOS). Accordingly, it is impossible to form a complemen-
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`tary MOScircuit (CMOS) in combination with N-channel
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`type TFT (TFT of NMOS).
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`[0007] However, TFTs formed of amorphous semiconduc-
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`tors have a feature that their OFF current is small. Therefore,
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`such TFTs have been used where an extremely high speed
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`operation is not needed like a liquid crystal active matrix
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`transistor, one-way conductive type TFTs may besatisfac-
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`torily used and TFTs having a high charge holding capacity
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`[0008] On the other hand, a polycrystal semiconductor has
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`a larger electric field mobility than that of an amorphous
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`semiconductor. Therefore, in this case, it is possible to effect
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`high speed operation. For example, with TFTs using a
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`silicon film recrystallized through a laser anneal technique,
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`it is possible to obtain a large electric field mobility of 300
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`cm?/Vs. This value is considered very high in view of the
`[0015] On the other hand, if the thickness of the active
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`layer would be increased,
`the leakage current would be
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`sistor formed onasingle crystal silicon substrate 1s approxi- increased. The magnitude thereofis not in proportion to the
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`mately 500 cm?/Vs. In addition, the operation speed of the
`thickness of the active layer. It is therefore reasonable that
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`MOScircuit on the single crystal silicon substrate is con-
`the leakage current would be increased in a non-linear
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`Ex. 1027, Page 8
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`Ex. 1027, Page 8
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`US 2002/0027249 Al
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`Mar. 7, 2002
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`rear electrode. The rear electrode is kept at a potential of the
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`source of the only one of the p-type transistor and the n-type
`transistor.
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`manner due to some causes. The present inventors have
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`studies and found that almost all the leakage current of the
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`TFs where the active layer is thick may flow througha part
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`of the active layer on the substrate side in a bypass fashion.
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`the gate electrode of P-channel type
`[0021] Preferably,
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`Two causes thereof might be found out. One causeis that
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`transistor is located out of the bottom side gate electrode.
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`there is a charge fixed to an interface energetic position
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`between the substrate and the active layer. The other cause
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`[0022] According to the invention,
`there is provided a
`is that movable ions such as sodium orthe like enter from
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`method for producinga thin film-like semiconductor device,
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`the substrate into the active layers to thereby make conduc-
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`comprising the following steps: selectively formingafirst
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`tive the part of the active layer on the substrate side. The
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`semiconductor coating film, havingafirst conductive (con-
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`later cause may be overcomeby increasing a performance of
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`ductivity) type, on a substrate having an insulating surface;
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`the cleaning process.
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`forming a first insulating coating film on the first semicon-
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`ductor coating film; forming a second semiconductor coat-
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`[0016] However, whatever the interface between the sub-
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`ing film for covering the first insulating coating film; form-
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`strate and the active layer was madeclean,it was impossible
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`ing a
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`to overcome the problem of the former cause. For example,
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`semiconductor coating film; forming at least two gate elec-
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`the direct formation of the active layer on the substrate
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`trode portions on the second insulating coating film; dis-
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`would lead to raising the interface energetic position.
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`persing impurities for the first conductive type into the
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`Accordingly, it was impossible to obviate the problem ofthe
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`second semiconductorcoating film in a self-alignment man-
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`leakage current even if an oxide layer (such as heat oxide
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`ner relative to the gate electrode portions; and after the
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`film of silicon) having a high quality to the same extent as
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`dispersing step, in a self-alignment mannerrelative to at
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`that of the gate oxide film was used as an underlayer and the
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`least one of the gate electrode portions, dispersing impurities
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`active layer was formed thereon. Namely, it has been found
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`for a conductive (conductivity) type opposite the first con-
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`that it is difficult to remove the fixed charge.
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`ductive type in the second semiconductorcoating film below
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`which the first semiconductor coating film is not present.
`SUMMARYOF THE INVENTION
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`[0023] According to the invention,
`there is provided a
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`[0017]
`In order to solve the above-noted defects or diffi-
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`method for producinga thin film-like semiconductor device,
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`culties, according to the present invention, an additional gate
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`comprising the following steps: forming, on a substrate
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`electrode (hereinafter referred to as a bottom side gate
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`having an insulating surface, a first conductive coating layer
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`electrode) is formed between a substrate and anactive layer,
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`made of one selected from the group essentially consisting
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`and this gate electrodeis kept at a suitable potential whereby
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`insulating
`of semiconductor and metal;
`forming a first
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`the stationary charge described above may becancelled.
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`coating film on the first conductive coating film; forming a
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`first semiconductor coating film on the first insulating coat-
`[0018] According to the present invention,in a field effect
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`ing film; forming a secondinsulating coating film onthefirst
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`type device having a thin film-like active layer, there is
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`semiconductor coating film; forming an etching mask mate-
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`provideda thin film-like semiconductor device comprising a
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`rial on the second insulating coating film; forming a hole in
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`top side gate electrode on the active layer and a bottom side
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`the etching mask material; forming a contact hole in the
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`gate electrode connectedto a static potential, the bottom side
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`second insulating coating film in accordance with an isotro-
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`gate electrode being provided between the active layer and
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`a substrate.
`pic etching process while using the etching mask material as
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`a mask, that is, through an opening of the etching mask;
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`forming a hole (an opening) in the first semiconductor
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`coating film in accordance with an anisotropic etching
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`process while using the etching mask material as a mask;
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`and forming a hole (an opening) in the first
`insulating
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`coating film in accordance with one of the isotropic etching
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`process and the anisotropic etching process while using the
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`etching mask material as a mask, thereby forming an elec-
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`trode connected between the first conductive coating film
`and the first semiconductor film.
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`[0019] According to another aspect of the invention, in a
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`field effect type device having a thin film-like active layer,
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`there is provided a thin film-like semiconductor device
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`comprising a top side gate electrode on the active layer and
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`a bottom side gate electrode (rear electrode) electrically
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`connected to only one of a source and a drain of the field
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`type device,
`the bottom side gate electrode being
`effect
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`provided between the active layer and a substrate.
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`[0020] According to still another aspect of the invention,
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`there is provided a thin film-like semiconductor device
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`comprising a bottom side gate electrode (rear electrode) on
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`a substrate having an insulating surface, a semiconductor
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`layer having N-type and P-type impurity regions for cover-
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`ing the bottom side gate electrode, and two gate electrodes
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`provided on the semiconductor layer, one of the last-men-
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`tioned gate electrodes being located out of the bottom side
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`gate electrode. A p-type transistor is provided on the insu-
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`lating surface and comprises an active region and a gate
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`electrode provided on the active region. An n-type transistor
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`is provided on the insulating surface and comprises another
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`active region and another gate electrode provided on the
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`another active region. The active region of only one of the
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`p-type transistor and the n-type transistor is provided on the
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0024]
`In the accompanying drawings:
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`[0025] FIGS. 1A and 1B are illustrations of inventive
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`concept of TFTs according to the invention;
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`[0026] FIGS. 2A and 2Bare cross-sectional views show-
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`ing examples of TFTs;
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`[0027] FIGS. 3A to 3H are illustrations showing the
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`operation of the TFTs according to the invention;
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`[0028] FIG. 4 showsthe operation of the TFTs according
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`to the prior art;
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`Ex. 1027, Page 9
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`Ex. 1027, Page 9
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`

`

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`US 2002/0027249 Al
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`Mar. 7, 2002
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`[0029] FIGS. 5A to 5F show the steps for producing the
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`TFTs according to the present invention;
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`[0030] FIGS. 6A to 6F show the application of the TFTs
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`according to the invention; and
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`[0031] FIGS. 7A to 7E show the process for manufactur-
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`ing the TFTs according to the invention.
`DESCRIPTION OF THE PREFERRED
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`EMBODIMENTS
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`[0032] The present invention will now be described with
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`reference to the accompanying drawings.
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`[0033] FIGS. 1A and 1B show an inventive conceptof the
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`present invention. Reference character A denotes a gate
`electrode which is well known in the art. Reference char-
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`acter B denotes a gate electrode provided on a bottom side.
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`Such a bottom side gate electrode B may be disposed so as
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`to be overlapped with the face surfaces of source/drain
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`regions as shown in FIG. 1A. However,in this arrangement,
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`additional capacitances between the source/drain regions
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`and the bottom side gate electrode would be increased. In the
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`case where the high speed operation or the like is required,
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`as shown in FIG.1B, it is possible to take the arrangement
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`where the bottom side gate electrode B is located so as not
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`to overlap with either one or both of the source region and
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`the drain region. In any case, it is important that the bottom
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`side gate electrode is overlapped with at least a part of the
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`active layer. In order to insure the advantage of the inven-
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`tion, it is located so as to transverse the active layer as much
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`as possible.
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`[0034] For instance, in a conventional NMOS, in the case
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`where the electric potentials of the source and the gate are
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`kept at zero and the potential of the drain is kept at 10V, the
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`drain current have to be zero in an ideal condition. However,
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`the fixed charge on the substrate cause the active layer to be
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`kept in a weak inversion state. Therefore, the drain current
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`will flow by a thermal excitation. This is shown in FIG.4.
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`Namely, in a conventional TFT, a weak inversion region is
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`formed bythe fixed charge on the substrate side as shown in
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`FIG.4. Since the fixed charge is present without any change
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`whatevervoltage is applied to the gate electrode, it becomes
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`a source of the leakage current. However, in the case where
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`a thickness of the active layer is extremely decreased, the
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`affect of the gate electrode is applied also to the substrate so
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`this weak reversed region will be obviated by the
`that
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`potential of the gate. It is assumed that various reports that
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`the leakage current may be reduced by thinning the active
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`layer without any good reason may be based upon the
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`foregoing reasons. However, in the models shownin FIG.4,
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`it has been foundthat the threshold voltage is readily shifted,
`and the conventional methodis not an essential solution.
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`[0035] The purpose of the present invention is to remove
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`the affect of the fixed charge by providing the above-
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`described bottom side gate electrode and keeping the poten-
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`tial of the bottom side gate electrode (rear electrode) at zero
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`or negative values. FIGS. 2A and 2B show examplesof the
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`present invention in which a bottom side gate electrode (a
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`rear electrode) is electrically connected to a source region
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`through a contact hole provided in a portion of an insulating
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`film so that the bottom side gate electrode may be always
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`kept at the same potential as that of the source. In FIG. 2A,
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`the bottom side gate electrode 9 is overlapped exactly with
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`the source region 6 and the drain region 5. In this case, the
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`manufacture process would berelatively simple andyield is
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`high since no stepped portion would be formed in the gate
`electrode 9.
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`[0036]
`In order to produce an element having such an
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`arrangement,
`the following steps should be carried out.
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`Namely, a coating film to be the bottom side gate electrode
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`9 and an insulating film 8 are formed on the substrate. A
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`contact hole 10 is formed in the insulating film 8 and a
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`semiconductor layer is formed therein. These components
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`are subjected to a patterning process. Then, the gate insu-
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`lating film 4 and the gate electrode 1 are formed and the
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`drain region 5 and the source region 6 are formed in a
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`self-alignment manner. Parts where no impurities are doped
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`will becomethe active layer 7. Finally, a drain electrode 2
`and a source electrode 3 are formed thereon. The number of
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`the masks used in the foregoing steps is four(five in the case
`where the source electrode 3 and the drain electrode 2 are
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`not simultaneously formed).
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`[0037] On the other hand, FIG. 2B shows the example
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`where the bottom side gate electrode 19 is not overlapped
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`with the drain region 15. The step of the bottom side gate
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`electrode causes an adverse affect to be applied to the gate
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`electrode 11. For this reason, there would be a fear that the
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`exfoliation or removal problem would be applied to the gate
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`electrode. Also, the numberof processing steps is increased
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`in comparison with the case shown in FIG. 2A. Namely,first
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`of all, the bottom side gate electrode 19 is patterned, and
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`subsequently, the insulating film 18 is formed to form a
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`contact hole 20. Then, the semiconductor layer is formed
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`and is patterned. Then, the gate electrode 11 is patterned.
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`The source region 14, drain region 15 and active region 17
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`are formedin a self-alignment manner. The source electrode
`13 and the drain electrode 12 are formed thereon. The
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`numberof the masks used in the foregoing steps is five or
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`six. It is an ideal condition that the additional capacitance is
`reduced and the bottom side electrode is formed in the
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`self-alignment manner with the source region and the drain
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`region in order to simplify the process.
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`[0038] The material for the bottom side gate electrode 9,
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`19 should be selected in view of the process to be applied to
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`the material. For
`instance,
`in the case where the gate
`insulation film is formed in accordance with the thermal
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`oxidation method, the material should stand the high tem-
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`perature corresponding to the method andthe dispersion of
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`the different harmful elements from the bottom side gate
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`material to the active layer should be avoided. For example,
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`if the active layer is formed ofsilicon and the gate insulation
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`film is a thermal oxidation film of silicon, in general, the
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`maximum processing temperature
`exceeds 1,000° C.
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`Accordingly, a doped polysilicon is desired as the material
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`for the bottom side gate electrode.
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`[0039] Also, in a low temperature process in which the
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`maximum processing temperature is about 600° C.,
`it is
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`possible to use the doped silicon but it is more preferable to
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`use lower resistance substances such as chrome, tantalum
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`and tungsten. Of course, any other material may be used as
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`a design choice as desired.
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`[0040] FIGS. 3A to 3H show the operation of the thus
`constructed TFT. FIGS. 3A to 3H show the case of an
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`NMOS. However, in case of a PMOS, the inequalities used
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`in these figures should be directed opposite those shown.
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`Ex. 1027, Page 10
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`Ex. 1027, Page 10
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`US 2002/0027249 Al
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`Mar. 7, 2002
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`invention will now be described. In this example, the gate
`Firstofall, the explanation will be madeas to the case where
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`electrode as well as the bottom side gate electrode was made
`the gate potential V,, is equal to either lower one of the
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`of doped polysilicon. The manufacturing process is well
`source potential V, or the drain potential V,. In this case, as
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`knownintheart, i.e., conventional processing techniques for
`shownin FIG.4, since the potentials of the source and the
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`various semiconductor integrated circuits and hence the
`drain are not symmetric with each other, the state depends
`detailed discussion thereof will be omitted.
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`upon the magnitude of the potential V,,. Whentherelation,
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`Vs<V,, Is established, as shown in FIG. 3A,
`the gate
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`[0047] A polycrystal silicon film which was doped with
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`electrode, the bottom side gate electrode and the source are
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`phosphorus of 10°° to 5x107° cm7°, for example, 8x107°
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`kept at the same potential so that the electrons are discharged
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`cm™* was formed on a quartz substrate 21 with a thickness
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`from these regions to form depletion regions or accumula-
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`of 100 to 500 nm, for example, 200 nm according to a low
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`tion region. Inversely, when the relation, V.<Vj, is estab-
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`pressure CVD process. This was thermally oxidized in an
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`lished, as shown in FIG. 3B, the gate electrode side is a
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`oxygen atmosphere kept at 1,000° C. to formasilicon
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`depletion region but an inversion region is formed on side of
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`coating film 22 andsilicon oxide film 23. A thickness of the
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`the bottom side gate electrode to allow the drain current to
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`silicon oxide was in the range of 50 to 200 nm,preferably
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`flow. The above discussion is very rough and morestrictly,
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`at 70 nm. In this case, a silicon film which is doped with no
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`the threshold voltage should be considered but the discus-
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`impurity may be formed and then the impurity may be doped
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