`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Samsung Electronics Co., Ltd. v. Demaray LLC
`Samsung Electronic's Exhibit 1054
`Exhibit 1054, Page 1
`
`

`

`
`
`US. Patent
`
`
`
`
`July 19, 1994
`
`
`
`Sheet 1 of 3
`
`
`5,331,218
`
`9 f1 95.22 WUfa
`
`
`
`
`
`
`
`
`
`fl
`'0‘
`
`:9
`
`FIG.
`
`PRIOR ART
`
`
`
`I
`
`
`
`
`
`
`
`
`
`
`
`27
`
`(b2
`
`
`
`92
`
`
`
`F l G. 3
`
`
`PRIOR ART
`
`Ex. 1054, Page 2
`
`Ex. 1054, Page 2
`
`

`

`US. Patent
`
`
`
`
`July 19, 1994
`
`
`
`
`
`Sheet 2 of 3
`
`
`5,331,218
`
`
`
`
`
`
`
`Ex. 1054, Page 3
`
`Ex. 1054, Page 3
`
`

`

`US. Patent
`
`
`
`
`July 19, 1994
`
`
`
`
`
`Sheet 3 of 3
`
`
`5,331,218
`
`
`
`
`
`I
`
`
`
`2
`
`
`
`
`
`
`
`
`3 4567890
`
`VOLTAGEDB
`
`
`FREQUENCY fK(KH2)
`
`
`3
`4
`5
`
`
`
`
`2
`
`
`
`6
`
`
`
`7
`
`
`
`
`8 9 IO
`
`82
`
`
`
`
`8!
`
`79
`
`
`
`78
`
`
`FIG. 9
`
`Ex. 1054, Page 4
`
`I
`
`
`0
`
`g
`Lu
`
`
`0-25
`E
`
`
`o>
`
`-50
`
`
`
`Ex. 1054, Page 4
`
`

`

`1
`
`
`
`5,331,218
`
`SWITCHED-CAPACITOR NOTCH FILTER WITH
`
`
`
`
`PROGRAMMABLE NOTCH WIDTH AND DEPTH
`
`
`
`
`
`BACKGROUND
`
`This invention relates to an active notch filter circuit
`
`
`
`
`
`
`
`
`
`
`
`
`
`employing switched-capacitor resistors and more par-
`
`
`
`
`
`
`
`
`ticularly to such filter circuits that include simultane-
`
`
`
`
`
`ously-digitally-programmable capacitor arrays for con-
`10
`
`
`
`
`
`
`trolling notch width and notch depth.
`
`
`
`
`
`
`Notch filters are used in analog-signal manipulating
`
`
`
`
`
`
`circuits for rejecting a particular signal frequency, or
`
`
`
`
`
`
`narrow range of frequencies. Conventional notch filters
`
`
`
`
`
`
`have a center or primary rejection frequency w, and a
`
`
`
`
`
`
`
`quality factor Q, which when high corresponds to a
`
`
`
`
`
`
`
`narrow filter bandwidth and when low corresponds to a
`
`
`
`
`
`
`
`relatively wide bandwidth. A high and low Q value also
`
`
`
`
`
`
`corresponds respectively to a narrow notch and a wide
`
`
`
`
`
`
`
`notch, as is further explained below. The transfer func-
`20
`
`
`
`
`
`
`tion of the conventional notch filter is expressed as
`
`15
`
`
`
`
`
`
`
`'
`
`25
`
`
`
`
`
`
`
`Vout _
`$2 + w2
`
`
`Vin
`w
`_ 2
`— s
`w2
`
`
`
`S + Q
`+
`Notch filters of this kind are described by Alan B.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Grebene in his book Bipolar And MOS Analog Inte-
`
`
`
`
`
`
`grated Circuit Design, 1984, pages 736—739.
`
`
`
`
`
`
`
`
`Notch width and notch depth are typically estab- .
`30
`
`
`
`
`
`
`
`
`lished by the filter manufacturer and are not controlla-
`ble by the filter user.
`
`
`
`
`
`
`
`
`
`
`
`
`It is an object of this invention to provide a notch
`
`
`
`
`
`
`
`filter circuit that is programmable with respect to notch
`
`
`
`width and depth.
`35
`
`
`
`
`
`
`
`It is a further object of this invention to provide such
`
`
`
`
`
`
`
`
`
`
`a filter wherein notch width and notch depth are inde-
`
`
`
`
`pendently programmable by the user.
`SUMMARY OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`
`A programmable notch filter includes first and sec-
`
`
`
`
`
`
`
`ond tandem connected operational amplifiers, each with
`
`
`
`
`
`
`
`a capacitor connected output to input across it. The
`
`
`
`
`
`tandem connection is effected by one switched-capaci-
`
`
`
`
`
`
`
`
`tor resistor between the output of the first amplifier to
`
`
`
`
`
`
`
`the input of the second. Another switched-capacitor
`resistor is connected between the notch filter input and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the input of the first amplifier. The filter output is the
`
`
`
`
`
`
`
`output of the second amplifier. Yet another switched
`
`
`
`
`
`
`
`capacitor resistor is connected between the notch filter
`
`
`
`
`
`
`
`
`output and the input of the first amplifier. A feed for-
`
`
`
`
`
`
`
`
`ward capacitor is connected between the input of the
`
`
`
`
`
`
`
`
`notch filter and the input of the second amplifier.
`
`
`
`
`
`
`A notch-width programming circuit consists of a
`
`
`
`
`
`
`circuit branch, that includes a first digitally-programm-
`
`
`
`
`
`
`
`
`able capacitor array, which array has a first group of 55
`
`
`
`
`
`
`
`digital programming terminals and which array is con-
`
`
`
`
`
`
`
`nected in parallel with the yet another switched-capaci-
`
`
`
`
`
`
`
`
`tor resistor for determining the capacitance of the first
`
`
`
`
`
`
`
`
`array, and thus the notch width, in response to a digital
`
`
`
`
`
`
`
`programming signal that may be applied to the first
`
`
`
`
`group of digital programming terminals.
`
`
`
`
`
`
`A notch-depth programming circuit consists of a
`
`
`
`
`
`
`circuit branch,
`includes a second digitally—pro-
`that
`
`
`
`
`
`
`
`grammable capacitor array, which array has a second
`
`
`
`
`
`
`
`group of digital programming terminals and which
`
`
`
`
`
`
`
`
`array is connected in parallel with the another
`
`
`
`
`
`switched-capacitor resistor. This second digitally-pro-
`
`
`
`
`
`
`grammable capacitor array is for determining notch
`
`
`
`2
`
`
`
`
`
`
`depth, in response to a digital programming signal that
`
`
`
`
`
`
`
`may be applied to the second group of digital program-
`
`
`ming terminals.
`
`
`
`
`
`
`
`
`
`In another aspect of this invention, the first and sec-
`
`
`
`
`
`
`
`ond groups of digital terminals of the capacitor arrays
`
`
`
`
`
`
`
`are connected to each other; and a digitally programma-
`
`
`
`
`
`
`
`
`ble voltage divider circuit, has a third group of digital
`
`
`
`
`
`
`programming terminals,
`is connected in the notch-
`
`
`
`
`
`
`
`depth circuit branch, has an input connected to the
`
`
`
`
`
`
`
`
`notch filter input, and has an output connected to the
`
`
`
`
`
`
`
`
`second capacitor array for determining the divider ratio
`
`
`
`
`
`
`
`
`
`of the programmable voltage divider and thus the notch
`
`
`
`
`
`
`
`depth without affecting the notch width, in response to
`
`
`
`
`
`
`
`
`a digital programming signal that may be applied to the
`
`
`
`
`
`third group of digital programming terminals.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`
`
`
`
`
`
`
`
`FIG. 1 shows a circuit diagram of a digitally pro-
`
`
`
`
`
`
`
`grammable capacitor array suitable for use in a notch
`filter circuit of this invention.
`
`
`
`
`
`
`
`
`
`FIG. 2 shows a block-diagram representation of the
`
`
`
`capacitor array of FIG. 1.
`
`
`
`
`
`
`FIG. 3 shows a circuit diagram of a switched capaci-
`tor resistor.
`
`
`
`
`
`
`
`
`FIG. 4 shows a first preferred embodiment of a notch
`filter circuit of this invention.
`
`
`
`
`
`
`
`
`
`
`FIG. 5 shows a current flow diagram corresponding
`to the circuit of FIG. 4.
`.
`
`
`
`
`
`
`
`
`
`FIG. 6 shows a second preferred embodiment of a
`notch filter circuit of this invention.
`
`
`
`
`
`
`
`
`
`
`FIG. 7 shows a block diagram of a reverse-connected
`
`
`
`
`
`
`DAC for use as a digitally controlled voltage divider.
`
`
`
`
`
`
`FIG. 8 shows, for different values of the programma-
`
`
`
`
`
`
`
`
`ble capacitance ratio Co/CQ, plots of the transfer func-
`
`
`
`
`
`
`tion Vout/Vin, or “gain”, as a function of the frequency
`
`
`
`
`
`
`
`
`fk of the input signal, for the circuit of FIG. 5.
`
`
`
`
`
`
`
`FIG. 9 shows, for different values of the programma-
`
`
`
`
`
`
`
`
`ble voltage divider ratio, A, a plot of the transfer func-
`
`
`
`
`
`tion Vout/Vin, or “gain”, as a function of the frequency
`
`
`
`
`
`
`
`
`fk of the input signal, for the circuit of FIG. 5.
`DESCRIPTION OF THE PREFERRED
`
`
`EMBODIMENTS
`
`
`
`
`
`
`
`A digitally programmable capacitor array 10 in FIG.
`
`
`
`
`
`
`
`
`
`1 is binary weighted, i.e. all of the capacitors 12 have
`
`
`
`
`
`
`
`
`the same capacitance value, C, and they are connected
`
`
`
`
`
`
`in binary groups of 1, 2, 4, etc. Electrically programma-
`
`
`
`
`
`
`
`
`ble switches 14, 15, 16 and 17 determine which groups
`
`
`
`
`
`
`of capacitors 12 contribute to the capacitance CA of the
`
`
`
`
`
`array 10 as measured between terminals 18 and 19.
`
`
`
`
`
`
`The digital-signal-activated switches 14, 15, 16 and 17
`
`
`
`
`
`
`are preferably implemented as MOS transistors (not
`
`
`
`
`
`
`shown). A switch to which a binary zero is applied
`
`
`
`
`
`
`
`opens, and a switch to which a binary 1 is applied closes
`
`
`
`
`
`
`to connect the switch-associated group of capacitors 12
`between terminals 18 and terminal 19. Thus for exam-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ple, when the digital programming signal is 1/0/0/1,
`
`
`
`
`
`
`
`only switches 14 and 17 contribute to the array capaci-
`
`
`
`
`
`
`
`tance CA which is illustrated in the block diagram of
`
`
`
`
`
`
`2. The
`corresponding decimal number
`is
`FIG.
`N=D0+2D1+4D2+8D3=L1+2.0+4.0+8.1=9.
`
`
`
`
`
`
`
`
`
`Thus CA=(D0+2D1+4D2+8D3)C, or CA=MC,
`
`
`
`
`
`
`wherein M is the decimal number corresponding to the
`
`
`
`
`
`
`
`
`digital programming signal that sets the switches 14
`
`
`through 17.
`
`
`
`
`
`
`
`For greater simplicity and clarity of presentation, the
`
`
`
`
`
`
`number of programming bits shown in the drawing, m,
`
`45
`
`
`
`50
`
`
`
`65
`
`
`
`
`
`Ex. 1054, Page 5
`
`Ex. 1054, Page 5
`
`

`

`5,331,218
`
`
`
`4
`
`
`
`Vout
`Vin
`
`
`
`
`2
`2
`(Cs)2
`CA
`c,
`
`
`
`
`
`_ S + C0 fc C0 5 + (fr)
`1C0!2
`
`
`
`
`
`(C )2
`_
`C
`
`
`2 _2.
`.95.
`2
`5
`
`
`
`
`
`
`
`S + C0 ft C0 S + (it)
`(Co):
`
`3
`
`
`
`
`
`
`
`
`
`
`is just 4 whereas a greater number of bits will usually be
`
`
`
`
`
`
`preferred. M can be any integer between 0 and 2m—‘.
`
`
`
`
`
`
`Thus for m=4, M can be any integer between 0 and 15.
`
`
`
`
`
`
`The programmable capacitor array of FIG. 1 may be
`
`
`
`
`
`
`more simply represented by symbol 10 of FIG. 2. The 5
`
`
`
`
`
`programmable-array capacitance is CA. The capacitor
`
`
`
`
`
`
`
`
`array 20 has capacitance terminals 18 and 19, and has a
`
`
`
`
`
`
`group of digital programming terminals 22 to which the
`
`
`
`
`programming digital signal is to be applied.
`
`
`
`
`
`
`The switched-capacitor resistor circuit of FIG. 3 10
`
`
`
`
`
`
`simulates a resistor whose equivalent ohmic value is
`Rx: l/fc'C:
`
`
`
`
`
`
`
`
`The form of this transfer function illuminates a major
`
`
`
`
`
`
`
`
`advantage of this notch filter, namely that the center
`
`
`
`
`
`(notch) frequency w is exclusively determined by the
`
`
`
`
`
`
`predictable temperature stable capacitor ratio Cs/Co
`
`
`
`
`
`
`
`
`and the switching frequency fc of the switched capaci-
`tor resistors which can be made as stable as desired by
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the user; and the quality factor Q, which determines the
`width of the filter notch in the transfer function, is ex-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`clusively determined by the capacitor ratio Co/CQ.
`
`
`
`
`
`
`
`Furthermore, it is also preferred to fabricate the fixed
`
`
`
`
`
`
`
`capacitances Co from one or more of the elemental
`
`
`
`
`
`
`
`MOS capacitors that make up the binarily weighted
`
`
`
`
`
`
`
`capacitor arrays so that for any digitally programmed
`
`
`
`
`
`
`values of the array capacitances CA and C9 the ratios
`
`
`
`
`
`
`
`
`
`CA/CQ, that controls notch depth, and the ratio Co/CQ
`
`
`
`
`
`
`
`
`are equally predictable and stable. These key capaci-
`tance ratios are
`
`
`
`
`
`
`w=fi%—’Q= C9
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The above-noted advantages derive partly from the
`
`
`
`
`
`
`use of switched capacitor resistors leading to key capac-
`
`
`
`
`
`
`itance ratio parameters in the transfer function.
`The notch filter transfer function above for the cir-
`
`
`
`
`
`
`
`
`cuit of FIG. 4 can now be rewritten as
`
`
`
`
`
`
`
`
`
`
`
`
`
`20
`
`
`
`
`
`30
`
`
`
`35
`
`
`
`
`
`
`
`
`
`
`
`where C; is the capacitance of switched capacitor 25. 15
`
`
`
`
`
`
`
`
`The two phases 4)] and (#2 of a two phase clock signal of
`
`
`
`
`
`
`frequency fc are applied as indicated in FIG. 3 to the
`clocked switches 26, 27, 28 and 29. With the four
`
`
`
`
`
`
`
`
`
`
`switches clocked as shown in FIG. 3, the resistor is said
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to be a positive switched capacitor resistor. As is well
`
`
`
`
`
`
`known, a negative switched capacitor resistor is formed
`
`
`
`
`
`
`
`
`in the case that switches 28 and 29 are changed to be
`
`
`
`
`
`
`
`clocked respectively by clock phases d>2 and (i); so that
`
`
`
`
`
`
`
`a positive input charge (signal) generates a negative
`25
`
`
`
`output charge (signal).
`
`
`
`
`
`Referring now to FIG. 4, operational amplifiers 30
`
`
`
`
`
`
`
`and 32 have integrating capacitors 34 and 36, respec-
`
`
`
`
`
`
`tively, connected between each amplifiers’s negative
`
`
`
`
`
`
`input and output. A first and positive switched-capaci-
`
`
`
`
`
`
`
`tor resistor circuit 37 is comprised of switches 380, 39a,
`
`
`
`
`
`
`
`
`40a and 41a and capacitor 420. Resistor 37 is connected
`
`
`
`
`
`
`
`
`between the filter input conductor 44 and the negative
`
`
`
`
`
`
`
`
`input of the amplifier 30. A second but negative
`
`
`
`
`switched-capacitor resistor 46 is comprised of switches
`
`
`
`
`
`
`
`
`
`38b, 39b, 40b and 41b and capacitor 42b. Resistor 46 is
`
`
`
`
`
`
`
`connected between the output of the amplifier 30 and
`
`
`
`
`
`
`
`the negative input of the second amplifier 32.
`
`
`
`
`
`A third and positive switched-capacitor resistor 48 is
`
`
`
`
`
`
`
`
`
`comprised of switches 38c, 39c, 40c and 41c and capaci-
`tor 42c. Resistor 48 is connected between the output of 40
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the amplifier '32, that corresponds to the filter output
`
`
`
`
`
`
`
`
`
`conductor 50, and the negative input of the first ampli—
`
`
`
`
`
`
`
`fier 32. A first programmable capacitor array 52, of
`
`
`
`
`
`
`capacitance CA, having a group of digital programming
`
`
`
`
`
`
`
`
`input terminals 54, is connected between the filter out- 45
`
`
`
`
`
`
`
`
`put conductor 50 and the negative input of amplifier 30.
`
`
`
`
`
`
`
`A programmable capacitor array 56, of capacitance CQ,
`
`
`
`
`
`
`having a‘ group of digital programming input terminals
`
`
`
`
`
`
`
`58, is connected in parallel with the switched capacitor
`
`
`
`
`
`37. A feedforward capacitor 60 is connected between 50
`
`
`
`
`
`
`
`
`the filter input conductor 44 and the negative input of
`
`
`
`
`the second amplifier 32.
`
`
`
`
`
`
`
`Although not essential to the invention, the values of
`
`
`
`
`
`
`
`
`switching capacitors 42a, 42b and 42c are preferably of
`
`
`
`
`
`
`
`
`the same integrated circuit structure, e.g. MOS, and 55
`
`
`
`
`
`
`
`
`
`preferably the same size and therefore the having the
`
`
`
`
`
`same value C, for optimum capacitance matching at
`
`
`
`
`
`
`
`manufacture. This also makes simpler the analysis of the
`
`
`
`
`
`
`
`
`circuit. For the same reason, the value of the capacitors
`
`
`
`
`
`
`
`
`34, 36 and 60 are preferably set equal, to value Co.
`
`
`
`
`
`
`
`The current flow diagram of FIG. 5 assigns a recipro-
`
`
`
`
`
`
`
`cal impedance expression to each branch of the notch
`
`
`
`
`
`
`
`
`filter circuit of FIG. 5, which expression when multi-
`
`
`
`
`
`
`
`
`
`plied by the branch voltage drops across the branch
`65
`
`
`
`
`
`
`
`components equals the branch current. This diagram
`
`
`
`
`
`represents a conventional method for analysis of a com-
`
`
`
`
`
`
`
`
`plex circuit, in this instance leading to the notch circuit
`transfer function:
`
`
`
`.w_
` 2
`
`
`
`Vow —S+@23+w2
`
`
`5>‘2+-E—S+w2
`Vm
`
`
`
`
`
`
`
`This equation for the filter of FIG. 4 is comparable to
`the transfer function for a conventional notch filter
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`described above on page 1, except for having the new
`S-term in the numerator. The transfer function of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`notch filter of FIG. 4 is seen to permit changing the
`
`
`
`
`
`
`
`
`center frequency w,
`the Q or notch width, and the
`
`
`
`
`
`
`
`notch depth @by changing capacitance ratios. The
`
`
`
`
`array capacitances CA and C9 are digitally programma-
`
`
`
`
`
`
`
`_ble making this feasible. The center frequency w can be
`
`
`adjusted by adjusting fc.
`
`
`
`
`
`
`However, a change in Q being effected by repro-
`
`
`
`
`
`
`
`
`gramming the value of array capacitance CQ also
`
`
`
`
`
`
`changes notch depth @. But @ can be held constant by
`
`
`
`
`
`
`
`also adjusting CA. In order to achieve complete inde-
`
`
`
`
`
`
`
`pendence of adjustment for each of these three perfor-
`mance characteristics, there is added in the notch filter
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`circuit of FIG. 6 a programmable voltage divider 64,
`
`
`
`
`
`
`having a group 82 of digital programming input termi-
`
`
`
`
`
`
`
`nals, in series with the array capacitor 56.
`
`
`
`
`
`
`Digitally programmable voltage divider (PVD) cir-
`
`
`
`
`
`
`
`cuits may be obtained by using standard digital-to-
`
`
`
`
`
`
`analog circuits (DAC’s) in a voltage mode. A conven-
`
`
`
`
`
`
`tional block symbol representing a standard DAC is
`converted to a PVD 64 by the addition of an arrow at
`
`
`
`
`
`
`
`
`
`
`
`
`the PVD output 84 as shown in FIG. 7, with multiple
`
`
`
`
`
`
`input terminals becoming a group of digital program—
`
`
`
`
`
`
`
`ming PVD terminals 82 for parallel application thereto
`
`
`
`
`
`
`of a digital programming signal. The DAC may be
`
`
`
`
`
`
`operated as PVD 64 by applying at the DAC voltage-
`
`
`
`Ex. 1054, Page 6
`
`
`
`
`
`Ex. 1054, Page 6
`
`

`

`
`
`6
`
`TABLE I-continued
`
`
`curve #
`Q
`M
`
`
`72
`.5
`16
`
`
`
` 1 I
`
`
`
`
`
`
`
`
`
`
`
`
`
`n FIG. 9, the notch filter gain curves 78, 79, 80, 81
`
`
`
`
`
`
`
`
`
`
`and 82 are plotted as a function of input signal fre-
`
`
`
`
`
`
`quency fk, and each corresponding respectively to five
`
`
`
`
`
`
`
`different digital signals of decimal value N applied to
`
`
`
`
`
`
`
`the programmable voltage divider 64. The resulting
`curves and values of attenuation A are given in Table II.
`
`
`
`
`
`
`
`
`
`5,331,218
`
` TABLE II
`
`N
`A
`curve #
`
`
`
`1
`1/ 16
`78
`
`
`2
`1/8
`79
`
`
`
`80
`4
`1/4
`
`
`
`8
`1/2
`81
`
`
`
`116 821
`
`
`
`
`
`
`
`
`
`20
`
`
`
`
`5
`
`
`
`
`
`
`
`reference terminal, now the PVD input terminal 86, an
`
`
`
`
`
`
`
`analog signal to be attenuated and observing the result-
`
`
`
`
`
`
`
`
`ing analog signal at the DAC output terminal, now the
`
`
`
`
`
`
`
`PVD output terminal 84. The amount of attenuation, A,
`
`
`
`
`
`
`obtained is determined by the particular digital signal
`
`
`
`
`
`
`
`
`that is being applied to the group of DAC digital input
`
`
`
`
`
`
`
`terminals, now PVD digital programming terminals 82.
`
`
`
`
`
`Filed concurrently herewith is applicant’s application
`entitled DIGITALLY DUAL-PROGRAMMABLE
`
`
`
`10
`INTEGRATOR CIRCUIT, which describes in more
`
`
`
`
`
`
`
`
`
`
`
`
`detail programmable capacitor arrays and such reverse
`
`
`
`
`
`
`
`connected DACs used as voltage dividers; and that
`
`
`
`
`
`co-filed application is incorporated by reference herein.
`
`
`
`
`
`
`
`The effect of the PVD 64 is to reduce the capacitance
`15
`
`
`
`
`
`
`
`C4 of the array capacitor 56 by the amount of the PVD
`attenuation ratio A.
`
`
`
`
`
`
`
`
`However, it can be seen from an above-given transfer
`
`
`
`
`
`
`
`equation of the circuit of FIG. 4, that in a special case
`
`
`
`
`
`
`
`wherein the same digital programming signal is applied
`
`
`
`
`
`
`to both capacitor-array programming terminals 54 and
`
`
`
`
`
`
`
`
`58 connected in parallel, the ratio of the capacitance
`
`
`
`
`
`
`
`
`
`values of the first and second arrays will remain con-
`
`
`
`
`
`
`
`
`
`stant for all digital programming input signals that may
`
`
`
`
`
`
`
`25
`be applied to the connected together terminals. This
`
`
`
`
`
`
`
`special case exists for the circuit of FIG. 6.
`
`
`
`
`
`
`
`The array capacitors 56 and 52 of FIG. 6 are prefera-
`
`
`
`
`
`
`
`bly identical for optimizing capacitance matching and
`
`
`
`
`
`
`have their programming terminals 58 and 54 connected
`
`
`
`
`
`
`
`in parallel so that both are simultaneously changed by
`
`
`
`
`
`
`
`
`the digital programming signal and always have identi-
`
`
`
`
`
`cal values, i.e. CQ=CA, and
`
`
`
`
`
`
`
`
`In the circuit of FIG. 4, the notch setting parameter
`
`
`
`
`
`
`
`@=CA/CQ, but in the circuit of FIG. 6 the notch-
`
`
`
`
`
`
`35
`depth-setting capacitance is ACA, where A is the PVD
`
`
`
`
`
`attenuation. The new notch-depth-setting parameter is
`
`
`
`3O
`
`
`
`
`
`
`
`
`
`
`
`
`
`The notch width seen in FIG. 9 does not change as
`
`
`
`
`
`
`
`notch depth is programmably varied, and the notch
`
`
`
`
`
`
`
`
`depth in FIG. 8 does not change as notch width is pro-
`
`
`
`
`
`
`grammably varied. Thus complete independence in the
`
`
`
`
`programming of these performance characteristics is
`realized.
`
`
`
`
`
`
`
`The programmable state-variable notch filter circuit
`
`
`
`
`
`
`
`
`of this invention is especially well suited as one of the
`
`
`
`
`
`analog-signal manipulating circuits employed in the
`
`
`
`
`
`
`integrated circuit co-processor described in the patent
`
`
`
`
`
`
`application filed simultaneously herewith entitled HY-
`BRID CONTROL-LAW SERVO CO-PROCESSOR
`
`
`
`
`INTEGRATED CIRCUIT, of the same inventive en-
`
`
`
`
`
`
`
`
`
`
`
`
`
`tity and assigned to the same assignee as is the present
`
`
`
`
`
`
`
`invention. Uses and additional advantages of this notch
`
`
`
`
`
`
`
`filter circuit are described in that co-filed application
`
`
`
`
`
`
`and that co-filed application is hereby incorporated by
`reference herein.
`
`
`We claim:
`
`
`
`
`
`
`
`1. A notch filter circuit comprising:
`
`
`
`
`
`
`
`a) a filter circuit input and a filter circuit output;
`
`
`
`
`
`
`b) first and second operational amplifiers;
`
`
`
`
`
`
`
`c) first and second capacitors connected respectively
`
`
`
`
`
`
`
`
`between the output and the negative input of each
`
`
`
`
`
`
`of said first and second amplifiers;
`
`
`
`
`
`d) a first switched-capacitor resistor connected be-
`
`
`
`
`
`
`
`
`tween said filter circuit
`input and said first-
`
`
`amplifier input;
`
`
`
`
`
`e) a second switched-capacitor resistor connected
`
`
`
`
`
`
`
`
`between said first amplifier output and said second
`
`
`
`
`
`
`amplifier input, said second-amplifier output con-
`
`
`
`
`
`nected to said filter circuit output;
`
`
`
`
`
`f) a third switched-capacitor resistor connected be-
`
`
`
`
`
`
`
`
`
`tween said filter circuit output and said first ampli-
`
`
`fier input;
`,
`
`
`
`
`
`
`g) a first programmable capacitor array connected in
`
`
`
`
`
`
`parallel with said third switched-capacitor resistor;
`
`
`
`
`
`
`
`h) a third capacitor connected between said second-
`
`
`
`
`
`
`
`
`amplifier input and said filter circuit input, and
`
`
`
`
`
`
`i) a second programmable capacitor array connected
`
`
`
`
`
`
`
`in parallel with said first switched-capacitor resis—
`
`
`
`
`
`
`
`tor, so that a change only in the capacitance of said
`
`
`
`
`
`second capacitor array causes a corresponding
`
`
`
`
`
`
`
`
`change in the filter notch depth and a change only
`
`
`
`
`
`
`
`
`in the capacitance of said first capacitor array
`
`
`
`
`
`
`causes a corresponding change in the filter notch
`width.
`
`
`ACA
`ACA
`=——:—-——:,;.
`
`
`
`
`C9
`CA
`
`@1
`
`The transfer function for the notch circuit of FIG. 7
`
`
`
`
`
`
`
`
`is now
`
`
`
`
`
`Vout
`Vin
`
`
`
`
`2
`2
`_L
`CA
`(C5):
`C
`
`
`
`
`
`
`
`
`
`
`
`_ S + A C0
`fr C0 5 + (ff)
`1C0!2
`
`C
`(C )2
`—
`
`2
`2
`S
`Q
`C:
`S + C0 ff C0
`(C102
`
`S + (fr)
`
`'
`
`45
`
`
`
`
`
`
`
`
`
`55
`
`50
`This transfer function indicates that notch width is
`
`
`
`
`
`
`
`
`
`
`
`
`
`programmable by C9, and notch depth is programma-
`
`
`
`
`
`
`
`
`
`ble by A; and notch width and depth are now indepen-
`
`
`dently programmable.
`Performance of this circuit is demonstrated as follows
`
`
`
`
`
`for the notch filter circuit constructed as shown in FIG.
`
`
`
`
`
`
`
`
`6.
`
`
`
`
`
`
`
`
`
`
`
`In FIG. 8, the notch filter gain curves 68, 69, 70, 71
`
`
`
`
`
`
`
`
`
`and 72 are plotted as a function of input signal fre-
`
`
`
`
`
`
`quency fk, each corresponding respectively to five dif-
`
`
`
`
`
`
`
`ferent digital signals of decimal value M applied to the
`
`
`
`
`
`
`
`
`capacitor arrays 52 and 56. The resulting curves and
`
`
`
`
`
`
`values of Q, namely Co/CQ, are given in Table I.
`
`______T§EE‘______
`Q
`curve #
`M
`
`
`
`
`1
`8
`68
`
`
`2
`4
`69
`
`
`70
`4
`2
`
`
`71
`8
`l
`
`
`65
`
`
`
`
`
`
`
`Ex. 1054, Page 7
`
`Ex. 1054, Page 7
`
`

`

`5,331,218
`
`
`7
`2. The notch filter of claim 1 wherein said first, sec-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ond and third capacitors have the same capacitance
`
`
`
`
`
`
`
`values so that the Q of said notch-filter is equal to the
`
`
`
`
`
`
`
`
`ratio of said same capacitance value and the capacitance
`
`
`
`
`
`value of said first capacitor array.
`3. The notch filter of claim 1 wherein said first and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`second arrays are digitally programmable, said first and
`
`
`
`
`
`
`
`second capacitor arrays having a group of digital pro-
`10
`
`
`
`
`
`
`gramming terminals, the groups of programming termi-
`
`
`
`
`
`
`
`
`nals of said first and second capacitor arrays connected
`
`
`
`
`
`
`
`
`
`
`to each other for making the ratio of the capacitance
`
`
`
`
`
`
`
`
`
`values of said first and second arrays constant for all
`
`
`
`
`
`
`
`15
`
`
`
`8
`
`
`
`
`
`
`digital programming input signals that may be applied
`
`
`
`
`
`to said connected together terminals.
`4. The notch filter of claim 3 wherein said first and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`second capacitor arrays are essentially identical, for
`
`
`
`
`
`
`
`
`making the capacitance values of said first and second
`
`
`
`
`
`
`
`
`arrays equal for all digital programming input signals
`
`
`
`
`
`
`
`that may be applied to said connected together termi-
`nals.
`
`
`
`
`
`
`
`
`5. The notch filter of claim 3 additionally comprising
`
`
`
`
`
`
`
`a digitally programmable voltage divider circuit con-
`
`
`
`
`
`
`
`nected in series with said second programmable capaci-
`
`
`
`
`
`
`
`
`
`
`tor array between said filter circuit input and said sec-,
`
`
`
`ond capacitor array.#
`l
`t
`t
`it
`
`
`
`
`
`
`
`
`
`
`
`20
`
`
`
`25
`
`
`
`30
`
`
`
`35
`
`
`
`45
`
`
`
`50
`
`
`
`55
`
`
`
`65
`
`
`
`Ex. 1054, Page 8
`
`Ex. 1054, Page 8
`
`