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`Samsung Electronics Co., Ltd. v. Demaray LLC
`Samsung Electronic's Exhibit 1049
`Exhibit 1049, Page 1
`
`

`

`
`
`US 7,247,227 B2
`
`
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`
`
`
`
`
`
`1/1990 Barrow et al.
`4 894 116 A
`
`
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`
`
`
`
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`
`
`5/1990 Koski et 31.
`4,921,584 A
`
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`
`
`3/1993 Jeung et a1.
`5,194,136 A
`
`
`
`
`
`“/1993 Edlund
`5,259,870 A
`7/1997 Kim et a1.
`5 643 817 A *
`
`
`
`
`
`
`
`
`
`
`5,674,599 A * 10/1997 Yamada
`
`
`
`5,959,763 A
`9/1999 Bozler etual ..................
`
`
`
`
`
`6,172,733 B1
`1/2001 Hong et al.
`
`
`
`
`6,322,712 B1
`11/2001 Hanson et al.
`
`
`
`
`
`6,471,879 B2
`10/2002 Hanson et al.
`
`
`
`
`
`
`
`
`.................. 205/124
`
`
`
`
`428/212
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`
`
`
`
`EP
`
`JP
`JP
`
`JP
`
`JP
`
`JP
`
`JP
`
`
`JP
`
`
`
`
`
`
`0 395 544 Bl
`
`49034906
`52 027354
`
`
`80007697
`
`1083655
`
`4933341
`
`4232250
`
`
`5-127183
`
`
`
`3/1996
`
`
`3/1974
`3/ 1977
`
`2/1980
`
`
`3/1989
`
`
`1 / 1991
`
`
`8/1992
`
`
`
`
`5/1993
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`
`
`Seo, H.S., et a1., “Hillock-Free Al-Gate Materials Using Stress-
`
`
`
`
`
`
`Absorbing Buffer Layer for Large-Area AMLCDs”, SID 96 Digest,
`
`
`
`
`PP~ 341-344, nfi‘moml} ml
`_
`_
`
`
`
`
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`
`
`T. Aral, et a1., Aluminum-based gate structure for act1ve-matr1x
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`
`“(mid crystal displays”a IBM J~ Res V01~N0~ 3/4 May/Jul 1998 ~
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`
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`
`
`
`
`Muni, J.D., et a1., “Electrostatic bonding of Si and glass using A1
`
`
`
`
`
`
`
`interlayer for macropacking of an FED”, Institute of Advanced
`
`
`Engineering, no date.
`
`
`
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`
`
`
`Quenzer, H.J., et a1., SiliconiSilicon anodic-bonding with inter-
`
`
`
`
`
`
`
`
`
`mediate glass layers using spin-on glassesz, IEEE Feb. 11-15, 1996,
`
`
`
`
`
`9.sup.th International Workshop on MEMS. .
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`
`
`
`
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`
`Ching-Fa Yeh, et al., “The Characterization of A1.sub.2 0.sub.3
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`
`
`
`
`
`Prepared by Anodic Oxidation”, Jpn. J. Appl. Phys. vol. 32 (1993)
`
`
`
`
`pp. 2803-2808, no month avail.
`
`
`
`
`
`
`
`
`
`C.C. Wu et a1., “Surface modification and indium tin oxide by
`
`
`
`
`
`
`
`
`plasma treatment: An elfective method to improve the elficiency,
`
`
`
`
`
`
`
`
`brightness, and reliability of organic light emitting devices”, Appl.
`
`
`
`
`
`
`
`
`Phys. Lett. 70 (11) Mar. 17, 1997, pp. 1348-1350..
`JE.A.M. van den Meerakker and W.R. ter Veen. Reductive Corro-
`
`
`
`
`
`
`
`
`sion of ITO in contact with A1 in Alkaline Solutions. J.E1ectrochem.
`
`
`
`
`
`
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`
`
`
`
`
`
`
`
`
`
`Soc. , vol. 139, No. 2, Feb. 1992, pp. 385-390, no month avail.
`
`
`
`* cited by examiner
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`
`Ex. 1049, Page 2
`
`Ex. 1049, Page 2
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`

`

`
`U S Patent
`
`
`
`
`
`mmu,mJ
`
`
`
`e
`
`
`
`0
`
`
`
`SU
`
`
`
`
`2Bn
`
`
`
`
`
`.g.
`
`
`
`
`
`
`m@N.xS.QN\
`
`nNWgfigfifififififififififififigfifififi
`S
`
`
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`
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`
`
`
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`Nx
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`4In,Fa:
`
`n,E:moan;
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`
`
`Ex. 1049, Page 3
`
`Ex. 1049, Page 3
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`
`

`

`
`U.S. Patent
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`
`
`HJ
`
`SU
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`
`
`m7
`
`
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`
`
`
`
`7x\.»Nm,9%Nm.NW
` mSm0%rgfigggfiumnfluhnnflmnfiuuunummanhwfiNW%2..QM“WVH\K%'5»K$a$‘.
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`4r";I...7-.I.l..ll.4ii.z..r’lf€.ll‘.-\r5127:tl__.l..I‘.iy4l.r.ll..l\3’45}4
`
`
`
`m,E:moan:m,NGE
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`
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`Ex. 1049, Page 4
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`Ex. 1049, Page 4
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`

`

`
`U.S. Patent
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`Jul. 24, 2007
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`
`Sheet 3 of 8
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`
`
`US 7,247,227 B2
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`
`
`FIG. 3
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`
`(PRIOR ART)
`
`Ex. 1049, Page 5
`
`Ex. 1049, Page 5
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`

`

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`U.S. Patent
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`Jul. 24, 2007
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`Sheet 4 of 8
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`US 7,247,227 B2
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`Ex. 1049, Page 6
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`

`

`
`U.S. Patent
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`Jul. 24, 2007
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`Sheet 5 of 8
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`US 7,247,227 B2
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`Ex. 1049, Page 7
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`Ex. 1049, Page 7
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`U.S. Patent
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`Jul. 24, 2007
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`Sheet 6 of 8
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`US 7,247,227 B2
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`
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`kalu
`Iiiik
`//////////////////////////////////////////////////////////A
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`4c?
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`//////////////////’//////////////////////////////////////////4
`
`46‘
`
`IIIIII
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`— ’
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`FIG. 7A
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`FIG. 73
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`Ex. 1049, Page 8
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`Ex. 1049, Page 8
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`Jul. 24, 2007
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`Sheet 7 of 8
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`US 7,247,227 B2
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`FIG.8
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`FIG.12
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`FIG.10
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`Ex. 1049, Page 9
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`Ex. 1049, Page 9
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`Jul. 24, 2007
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`Sheet 8 of 8
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`US 7,247,227 B2
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`FIG.13
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`FIG.15
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`FIG.14
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`Ex. 1049, Page 10
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`Ex. 1049, Page 10
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`US 7,247,227 B2
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`
`1
`BUFFER LAYER IN FLAT PANEL DISPLAY
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`CROSS-REFERENCE TO RELATED
`
`APPLICATION
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`This application is a divisional of US. patent application
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`Ser. No. 09/387,910, filed Sep. 1, 1999, now US. Pat. No.
`
`6,322,712.
`REFERENCE TO GOVERNMENT CONTRACT
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`
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`This invention was made with United States Government
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`support under Contract No. DABT63-97-C-0001, awarded
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`by the Advanced Research Projects Agency (ARPA). The
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`United States Government has certain rights in this inven-
`tion.
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`10
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`15
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`
`
`BACKGROUND OF THE INVENTION
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`2
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`which dissolves in the solution, and In metal, which forms
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`grains at the surface. This causes a gray opaque appearance
`and a disconnection between the ITO and aluminum. Cor-
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`rosion of the ITO can prove fatal in devices such as flat panel
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`displays by reducing or eliminating the electrical conduc-
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`tivity and optical transparency of the ITO material. This
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`corrosion can also cause delamination of the aluminum layer
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`from the ITO. Redeposition of corrosion byproducts onto the
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`substrate leads to additional defects, e.g., particle defects.
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`Furthermore, during anodic bonding of spacers to bond
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`pads, excess oxide can change local optical properties of the
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`adjacent ITO between the bond pads. Optical properties may
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`also be changed due to etching.
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`Accordingly, what is needed is an improved method and
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`apparatus for protecting the electrical and optical properties
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`of an ITO layer and the like when such a layer is exposed to
`aluminum.
`
`
`SUMMARY OF THE INVENTION
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`1. Field of the Invention
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`This invention relates to preserving the electrical and
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`optical properties of optically transparent and conductive
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`films such as indium tin oxide (ITO), and more particularly,
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`to providing a buffer or protective layer between aluminum
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`and ITO for use in the fabrication of flat panel displays and
`the like.
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`2. Description of the Related Art
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`Optically transparent and electrically conductive materi-
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`als such as indium tin oxide (ITO) find utility in flat panel
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`display (FPD) industries such as field emission displays
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`(FEDs), liquid crystal displays (LCDs), and organic light
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`emitting devices (OLEDs), as well as in solar cells. Surface
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`and bulk characteristics are imperative to the quality of
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`electrical and optical properties of these and other optically
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`transparent and electrically conductive films. It is therefore
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`very important to ensure that such films exhibit the desired
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`surface and bulk properties such that the desired degree of
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`transmission of visible light and electrical properties are
`obtained.
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`Devices incorporating ITO often use an aluminum layer
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`deposited over the ITO. For instance,
`in an FED device
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`where the faceplate is connected to the baseplate using
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`spacers, aluminum is often deposited over the ITO layer in
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`the faceplate to establish sites for the bonding of misaligned
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`spacers. More particularly, an aluminum layer is formed
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`over the ITO layer, the aluminum layer having wells extend-
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`ing therein to the surface of the ITO layer. Bond pads are
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`provided within these wells against the ITO layer at the
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`desired spacer locations. Then, when an array of spacers is
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`brought against the faceplate for anodic bonding, desired
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`spacers contained in the array will bond to the bond pads,
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`while other, misaligned spacers will bond to the aluminum
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`layer. After bonding is complete, the aluminum layer with
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`the misaligned spacers bonded thereto can be removed to
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`leave the desired spacer configuration in the FED.
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`A problem with using aluminum with ITO in the above
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`and other applications is that ITO is susceptible to corrosion
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`in the presence of aluminum. Atomic and/or ionic diffusion
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`occurs through the aluminum to the ITO during processes
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`such as anodic bonding, thermal cycling, thermal diffusion
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`processes, low energy ion implantation processes, and pro-
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`cesses which include electric and/or magnetic fields. ITO is
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`especially susceptible to corrosion in the presence of alu-
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`minum when exposed to alkaline or basic solutions or
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`solvents. See, J. E. A. M. van den Meerakker and W. R. ter
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`Veen, J. Electrochem. Soc, vol. 139, no. 2, 385 (1992).
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`Corrosion of ITO in alkaline solutions produces SnO32',
`
`20
`
`25
`
`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`Briefly stated, the needs addressed above are solved by
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`providing an aluminum oxide layer between an aluminum
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`layer and an ITO layer to protect the ITO from optical and
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`electrical defects sustained, for instance, during anodic
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`bonding and other fabrication steps. This aluminum oxide
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`barrier layer is preferably formed either by: (1) partially or
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`completely anodizing an aluminum layer formed over the
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`ITO layer, or (2) an in situ process forming aluminum oxide
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`either over the ITO layer or over an aluminum layer formed
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`on the ITO layer. After either of these processes, an alumi-
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`num layer is then formed over the aluminum oxide layer.
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`In accordance with one aspect of the present invention, a
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`method of manufacturing a tin oxide/aluminum structure is
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`provided. The method comprises forming a tin oxide layer,
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`forming an aluminum oxide layer over the tin oxide layer,
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`and forming a top aluminum layer over the aluminum oxide
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`layer. In one embodiment,
`the aluminum oxide layer is
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`formed by anodizing aluminum. In another embodiment, the
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`aluminum oxide layer is formed by reactive sputtering.
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`In accordance with another aspect of the present inven-
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`tion, a tin oxide/aluminum structure is provided comprising
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`a tin oxide layer over a substrate, an aluminum oxide layer
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`over the tin oxide layer, and an aluminum layer over the
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`aluminum oxide layer. In one embodiment, the tin oxide
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`layer comprises indium tin oxide. A second aluminum layer
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`may be provided between the tin oxide layer and the
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`In accordance with another aspect of the present inven-
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`tion, a method of protecting an indium tin oxide layer in the
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`presence of aluminum is provided. An aluminum oxide layer
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`is formed between the indium tin oxide layer and the
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`aluminum. The aluminum oxide layer is preferably formed
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`either by anodizing the aluminum or by reactive sputtering.
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`In accordance with another aspect of the present inven-
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`tion, a method of fabricating a display device structure is
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`provided. The method comprises forming an indium tin
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`oxide layer, forming an aluminum oxide layer over the tin
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`oxide layer, and forming an aluminum layer over the alu-
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`minum oxide layer. The structure is then exposed to an
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`indium tin oxide-corrosive medium, such as would be used
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`during the fabrication of the display device. The aluminum
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`oxide prevents diffusion of the corrosive medium through
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`the aluminum layer to the indium tin oxide layer. Once the
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`structure is no longer exposed to the indium tin oxide-
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`corrosive medium, the aluminum oxide and aluminum lay-
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`ers are removed.
`In one embodiment,
`these layers are
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`removed after spacers have been fabricated. More prefer-
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`Ex. 1049, Page 11
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`Ex. 1049, Page 11
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`

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`US 7,247,227 B2
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`4
`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENTS
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`3
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`ably, by using an aluminum oxide barrier layer between the
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`indium tin oxide layer and the aluminum layer, the alumi-
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`num oxide and aluminum layers can be removed using an
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`etchant comprising phosphoric acid at a temperature up to
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`about 60° C., without damaging the indium tin oxide.
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`In accordance with another aspect of the present inven-
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`tion, a display device structure comprises a substrate, an
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`electrically conductive and optically transparent layer over
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`the substrate, an aluminum oxide layer over the electrically
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`conductive and optically transparent layer, and an aluminum
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`layer over the aluminum oxide layer. In one embodiment,
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`the aluminum oxide layer has a thickness of between about
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`500 and 1,500 A, and the aluminum layer has a thickness of
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`between about 4,500 and 6,000 A. The aluminum oxide
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`layer preferably comprises AlO,C where x is between about
`0.25 and 1.5.
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`The preferred embodiments describe flat panel display
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`devices, and more particularly, fabrication of the faceplate of
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`an FED device using indium tin oxide and the like. It will be
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`appreciated that although the preferred embodiments are
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`described with respect to FED devices, the methods and
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`apparatus taught herein are applicable to other flat panel
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`display devices such as liquid crystal displays (LCDs),
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`organic light emitting devices (OLEDs), plasma displays,
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`vacuum fluorescent displays (VFDs), electroluminescent
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`displays (ELDs), as well as solar cells. Other devices
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`incorporating ITO and similar materials, such as other tin
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`oxides, are also contemplated as being within the scope of
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`this invention, as well as any device which employs an
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`aluminum layer formed over an ITO or similar layer.
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`FIG. 1 illustrates a portion of a flat panel display, includ-
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`ing a plurality of field emission devices. Flat panel display
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`10 comprises a baseplate 12 and a faceplate 14. Baseplate 12
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`includes substrate 16, which is preferably formed from an
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`insulative glass material. Column interconnects 18 are
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`formed and patterned over substrate 16. The purpose and
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`function of column interconnects 18 is disclosed in greater
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`detail below. Furthermore, a resistor layer 20 may be dis-
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`posed over column interconnects 18. Electron emission tips
`22 are formed over substrate 16 at the sites from which
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`electrons are to be emitted, and may be constructed in an
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`etching process from a layer of amorphous silicon that has
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`been deposited over substrate 16. Electron emission tips 22
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`are protrusions that may have one or many shapes, such as
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`pyramids, cones, or other geometries that terminate at a fine
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`point for the emission of electrons.
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`An extraction grid 24, or gate, which is a conductive
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`structure that supports a positive charge relative to the
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`electron emission tips 22 during use,
`is separated from
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`substrate 16 with a dielectric layer 26. Extraction grid 24
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`includes openings 28 through which electron emission tips
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`22 are exposed. Dielectric layer 26 electrically insulates
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`extraction grid 24 from electron emission tips 22 and the
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`associated column interconnects which electrically connect
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`the emission tips with a voltage source 30.
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`Faceplate 14 includes a plurality of pixels 32, which
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`comprise cathodoluminescent material that generates visible
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`light upon being excited by electrons emitted from electron
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`emission tips 22. For example, pixels 32 may be red/green/
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`blue full-color triad pixels. Faceplate 14 further includes a
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`substantially transparent anode 34 and a glass or another
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`transparent panel 36. Spatial support structures or spacers 38
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`are disposed between baseplate 12 and faceplate 14 and
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`prevent the faceplate from collapsing onto the baseplate due
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`to air pressure differentials between the opposite sides of the
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`faceplate. In particular, the gap between faceplate 14 and
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`baseplate 12 is typically evacuated, while the opposite side
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`of the faceplate generally experiences ambient atmospheric
`pressure.
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`The flat panel display is operated by generating a voltage
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`differential between electron emission tips 22 and grid
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`structure 24 using voltage source 30. In particular, a negative
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`charge is applied to electron emission tips 22, while a
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`positive charge is applied to grid structure 24. The voltage
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`differential activates electron emission tips 22, whereby a
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`flux of electrons 40 is emitted therefrom. In addition, a
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`relatively large positive charge is applied to anode 34 using
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`voltage source 30, with the result that a flux of electrons 40
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`strikes the faceplate. The cathodoluminescent material of
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`pixels 32 is excited by the impinging electrons, thereby
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`Ex. 1049, Page 12
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a schematic cross-sectional view of a flat panel
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`display including a plurality of field emission devices.
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`FIG. 2 is an isometric view of a baseplate of a flat panel
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`display, showing an emitter set comprising a plurality of
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`electron emission tips.
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`FIG. 3 is a top view of the baseplate of flat panel display
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`of FIG. 2, showing the addressable rows and columns.
`FIG. 4 is a schematic cross-sectional view of an FED
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`faceplate bonded to a plurality of spacers.
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`FIG. 5 is a schematic top view of the faceplate of FIG. 4,
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`showing an aluminum layer deposited thereon.
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`FIG. 6 is a schematic top view of an array of spacers to
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`be bonded to the faceplate of FIG. 5.
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`FIG. 7A is a schematic cross-sectional view of a flat panel
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`display faceplate having an aluminum layer and an alumi-
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`num oxide layer formed thereover.
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`FIG. 7B is a schematic cross-sectional view of a flat panel
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`display faceplate having an aluminum oxide layer formed
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`thereover and sandwiched between two aluminum layers.
`FIG. 8 is a schematic cross-sectional view of a structure
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`having an ITO layer for a flat panel display faceplate and the
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`like according to a first preferred embodiment, with an
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`aluminum layer formed thereover.
`FIG. 9 is a schematic cross-sectional view of the structure
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`of FIG. 8, showing partial anodization of the aluminum
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`layer.
`FIG. 10 is a schematic cross-sectional view of the struc-
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`ture of FIG. 9, showing the deposition of an additional layer
`of aluminum.
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`FIG. 11 is a schematic cross-sectional view of the struc-
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`ture of FIG. 8, showing complete anodization of the alumi-
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`num layer.
`FIG. 12 is a schematic cross-sectional view of the struc-
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`ture of FIG. 11, showing the deposition of an additional layer
`of aluminum.
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`FIG. 13 is a schematic cross-sectional view of a structure
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`having an ITO layer formed according to a second preferred
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`embodiment of the present invention, showing the formation
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`of the ITO layer on a substrate.
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`FIG. 14 is a schematic cross-sectional view of the display
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`structure of FIG. 13, showing the deposition of an interme-
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`diate aluminum layer, an aluminum oxide layer and a top
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`aluminum layer thereover.
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`FIG. 15 is a schematic cross-sectional view of the display
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`structure of FIG. 13, showing the deposition of an aluminum
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`oxide layer and an aluminum layer thereover.
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`Ex. 1049, Page 12
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`

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`5
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`generating Visible light. The coordinated activation of mul-
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`tiple electron emission tips over the flat panel display 10
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`may be used to produce a Visual image on faceplate 14.
`FIGS. 2 and 3 further illustrate conventional field emis-
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`sion devices. In particular, electron emission tips 22 are
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`grouped into discrete emitter sets 42, in which the bases of
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`the electron emission tips in each set are commonly con-
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`nected. As shown in FIG. 3, for example, emitter sets 42 are
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`configured into columns (e.g., C1-C2) in which the indi-
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`vidual emitter sets 42 in each column are commonly con-
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`nected. Additionally, the extraction grid 24 is divided into
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`grid structures, with each emitter set 42 being associated
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`with an adjacent grid structure. In particular, a grid structure
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`is a portion of extraction grid 24 that lies over a correspond-
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`ing emitter set 42 and has openings 28 formed therethrough.
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`The grid structures are arranged in rows (e.g., Rl-R3) in
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`which the individual grid structures are commonly con-
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`nected in each row. Such an arrangement allows an X-Y
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`addressable array of grid-controlled emitter sets. The two
`20
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`terminals, comprising the electron emission tips 22 and the
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`grid structures, of the three terminal cold cathode emitter
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`structure (where the third terminal is anode 34 in faceplate
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`14 of FIG. 1) are commonly connected along such columns
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`and rows, respectively, by means of high-speed intercon-
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`nects. In particular, column interconnects 18 are formed over
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`substrate 16, and row interconnects 44 are formed over the
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`grid structures.
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`In operation, a specific emitter set is selectively activated
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`by producing a voltage differential between the specific
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`emission set and the associated grid structure. The voltage
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`differential may be selectively established through corre-
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`sponding drive circuitry that generates row and column
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`signals that intersect at the location of the specific emitter
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`set. Referring to FIG. 3, for example, a row signal along row
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`R2 of the extraction grid 24 and a column signal along
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`column C1 of emitter sets 42 activates the emitter set at the
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`intersection of row R2 and column C1. The voltage differ-
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`ential between the grid structure and the associated emitter
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`set produces a localized electric field that causes emission of
`electrons from the selected emitter set.
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`Further details regarding FED devices are disclosed in
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`assignee’s copending application entitled FIELD EMIS-
`SION DEVICE WITH BUFFER LAYER AND METHOD
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`OF MAKING, application Ser. No. 09/096,085, filed Jun.
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`11, 1998, now US. Pat. No. 6,211,608, and US. Pat. No.
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`5,372,973, both of which are hereby incorporated by refer-
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`ence in their entirety.
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`FIG. 4 illustrates more particularly a portion of a faceplate
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`of an FED device fabricated according to a preferred
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`embodiment of the present
`invention. The faceplate 14,
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`shown upside-down relative to the faceplate of FIG. 1,
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`includes a substrate 36 comprising a glass substrate 48, a
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`first SiN,C layer 46 formed on one side of the glass substrate
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`48, and a second SiN,C layer 50 formed on the other side of
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`the glass substrate 48. The first SiN,C layer 46 represents the
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`viewing side of the faceplate 14, and is preferably about 500
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`to 2000 A thick. The glass layer 48 is preferably soda lime
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`glass or borosilicate glass, and preferably has a thickness
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`between about 0.5 and 5 mm. The second SiN,C layer 50 is
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`an antireflective layer preferably about 500 to 2000 A thick.
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`In one embodiment, both the first and second SiN,C layers are
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`more preferably Si3N4.
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`Ablack matrix grill 52 is preferably formed over the SiN,C
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`layer 50. This grill 52 is preferably made of sputtered
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`amorphous Si, and defines open regions for phosphor layer
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`54. The grill 52 preferably has a thickness of between 3000
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`and 20,000 A, with the openings in the grill preferably
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`6
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`created by using an etchant such as an HNO3, HF, acetic acid
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`mixture to etch the amorphous silicon, or KOH/IPA mix-
`tures.
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`The transparent anode 34 of FIG. 1 is preferably a layer
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`of indium tin oxide 56 as shown in FIG. 4. The ITO layer 56
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`is preferably formed over the black matrix Si layer 52 and
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`over the SiN,C layer 50. The ITO layer 56 is preferably
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`deposited using physical vapor deposition, for example DC
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`sputtering, and has a thickness preferably between about
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`2000 and 5000 A. The applied voltage across the ITO layer
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`is preferably about 1000 to 3000 DC volts.
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`Bonding pads 58 are preferably distributed around the
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`faceplate 14, as shown in FIG. 4 and in a top view illustrated
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`in FIG. 5 (with aluminum layer 62 also shown, as described
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`below). These bonding pads 58 are located over the black
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`matrix grill 52 and the ITO layer 56 and provide the location
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`for bonding the spacers 38 to the faceplate 14. The bond
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`pads 58 are preferably made of silicon, and preferably have
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`a surface area when viewed from above of about 35><35 pm.
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`As shown in FIG. 5, the bonding pads 58 are preferably
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`altematingly staggered across the faceplate so that
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`spacers 38 bonded thereon are also spaced in a staggered
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`configuration. It will be appreciated that bond pads 58 may
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`be located in various other configurations on the faceplate
`14.
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`As shown in FIGS. 4 and 5, glass spacers 38 are bonded
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`to the faceplate 14 at bond pads 58 to form the spacers
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`between the faceplate 14 and baseplate 12 (not shown).
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`These spacers 38 are more preferably made of a soda lime
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`silicate glass or borosilicate glass. Glasses containing oxides
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`of SI, Pb, Na, K, Ba, Al, and Ag may also be used. Bonding
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`of the spacers to the faceplate is preferably accomplished
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`using anodic bonding, although other types of bonding such
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`as adhesive bonding may also be used.
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`Although the bond pads are preferably alternatingly stag-
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`gered around the faceplate 14 as shown in FIG. 5,
`it is
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`preferred in one embodiment to attach spacers to the face-
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`plate 14 using a uniform array 60 of spacers, such as shown
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`in FIG. 6, which contains more spacers than there are bond
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`pads 58. Thus, the array 60 not only contains the spacers 38
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`which are to be anodically bonded to the bond pads 58, but
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`it also contains misaligned spacers 66 which will not be
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`bonded to the bond pads 58. The misaligned spacers are
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`instead anodically bonded to a sacrificial aluminum layer 62
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`formed over the faceplate 14, as illustrated in FIGS. 7A and
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`7B and described in further detail below. A matrix glass
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`material is used to keep the spacers in the proper pattern
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`until after they are selectively removed after anodic bonding.
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`In one embodiment, after bonding the matrix glass is
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`removed by etching preferably using an HNO3/HZO or
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`HCl/HNO3/HZO or HCl/HZO mixture. Then, the bulk of the
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`aluminum is removed preferably using HNO3/H3PO4/acetic
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`acid mixture. KOH or NaOH is then preferably used to
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`remove the misaligned spacers 66. The advantages of the
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`uniform array 60 include its simplicity of design as well as
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`lower cost. Furthermore, because anodic bonding occurs at
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`temperatures, for example, of about 450° C., a uniform array
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`of spacers is desired to create a more uniform stress distri-
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`bution when the structure is subsequently cooled.
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`As shown in FIGS. 5, 7A and 7B, the aluminum layer 62
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`has wells 64 to permit access for the aligned spacers 38 to
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`the bonding pads 58. Then, when the array 60 of spacers 38
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`is brought to the faceplate 14 for anodic bonding, spa