(12) United States Patent
`Abe et al.
`
`USOO6507383B1
`US 6,507,383 B1
`(10) Patent No.:
`Jan. 14, 2003
`(45) Date of Patent:
`
`(54) IN-PLANE SWITCHING LIQUID CRYSTAL
`DISPLAY APPARATUS WITH REDUCED
`CAPACITANCE BETWEEN PXEL
`ETERS AND COMMON
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`6,281,953 B1
`8/2001 Lee et al. ..................... 349/43
`
`(75) Inventors: Makoto Abe, Hitachi (JP); Etsuko
`Nishimura, Hitachiohta (JP); Kikuo
`Ono, Mobara (JP); Yoshiaki
`Nakayoshi, Mobara (JP); Masatoshi
`Wakagi, Hitachi (JP)
`
`sk -
`
`cited by examiner
`Primary Examiner–Toan Ton
`ASSistant Examiner Timothy L Rude
`Eary Agent, or Firm- Antonelli, Terry, Stout, &
`
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`(21) Appl. No.:
`09/582,655
`(22) PCT Filed:
`Mar. 21, 2000
`(86) PCT No.:
`PCT/JP00/01712
`S371 (c)(1),
`(2), (4) Date: Jun. 29, 2001
`(87) PCT Pub. No.: WO01/71417
`PCT Pub. Date: Sep. 27, 2001
`e 1 is
`(51) Int. Cl." .............................................. G02F 1/1343
`(52)
`... 349/141; 349/138
`(58) Field of Search .......................................... 349/141
`
`
`
`ABSTRACT
`(57)
`Aliquid crystal display unit in which a voltage is applied to
`a pixel electrode and a common signal electrode constituted
`by two upper and lower transparent conductive layerS hav
`ing insulation layers disposed therebetween So that a liquid
`crystal is driven to control display can improve any one or
`both of reduction of a writing time of the liquid crystal
`(reduction of a capacitance between the pixel electrode and
`the common signal electrode) and reduction of a driving
`voltage of the liquid crystal. An inter-layer insulation layer
`between the transparent electrodes formed of different layers
`is constituted by at least one or a laminated Structure of a part
`of a gate insulation layer, a part of a Surface protection layer
`of a thin film transistor and an applied-type insulation layer
`and insulation layers in an area which is positioned above
`the lower transparent electrode.
`
`26 Claims, 36 Drawing Sheets
`
`POL2
`
`SUB2
`
`LC
`
`POL
`
`x:
`x x.
`x X x
`
`XX
`X
`&
`
`Page 1 of 61
`
`Tianma Exhibit 1007
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 1 of 36
`
`US 6,507,383 B1
`
`FIG. 1
`
`
`
`POL2
`
`SUB2
`
`BM
`
`LC
`
`PAS
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`A
`22ZZ
`
`DL
`
`SUB1
`
`POL1
`
`Page 2 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 2 of 36
`
`US 6,507,383 B1
`
`FIG 2
`
`
`
`|(
`
`Haekae?
`#####~##
`
`Page 3 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 3 of 36
`
`US 6,507,383 B1
`
`FIG. 3
`
`
`
`SUB1
`
`Page 4 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 4 of 36
`
`US 6,507,383 B1
`
`FIG. 4
`
`
`
`POWER SUPPLY CIRCUIT AND
`CRT-TO-TFT CONVERSION CIRCUIT
`
`IMAGE SIGNAL DRIVING CIRCUTH
`
`|
`
`
`
`-- - - - -!!!!!!!
`
`
`
`O|##= -i
`
`----
`
`appa as a
`
`to
`
`is as as a -
`
`
`
`s:
`
`B:
`
`F: A
`
`---
`FT LC
`T
`
`
`
`O|--|-----|-----|-= -1 = *|-----
`
`G:
`---
`
`
`
`CD-}=== *
`
`Page 5 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet S of 36
`
`US 6,507,383 B1
`
`FIG. 5
`
`
`
`BM
`
`OR2
`
`LC
`
`OR1
`G
`GL
`
`SUB
`
`BM
`
`OR2
`
`OR1
`G
`
`SUB1
`
`Page 6 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 6 of 36
`
`US 6,507,383 B1
`
`
`
`
`
`GTM
`
`TC1
`
`PAS
`G
`GL
`
`SUB1
`
`Page 7 of 61
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 14, 2003
`Jan. 14, 2003
`
`Sheet 7 of 36
`Sheet 7 0f 36
`
`US 6,507,383 B1
`US 6,507,383 B1
`
`
`
`DTM
`DTM
`
`
`
`
`
`Page 8 0f61
`
`Page 8 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 8 of 36
`
`US 6,507,383 B1
`
`(A)
`
`(B)
`
`(C)
`
`Cr (CL, GL, GE) BY
`SPATTERING
`
`(D)
`
`Cr (DL, SD) BYSPATTERING
`
`1ST PHOTOLITHOGRAPHY
`(FOR Cr)
`
`4TH PHOTOLITHOGRAPHY
`(FOR Cr)
`
`Cr (CL, GL, GE) ETCHED
`r (CL, GL, GE)
`
`Cr ETCHED
`n-SETCHED
`
`ITO (CE, TCL) BY
`SPATTERING
`
`(E)
`
`SIN (PAS) CVD
`
`2ND PHOTOLITHOGRAPHY
`(FOR ITO)
`
`5THH PHOTOLITHOGRAPHY
`(FOR SIN)
`
`TO (CE, TCL) ETCHED
`(
`)
`
`SN (PAS) ETCHED
`SIN (GDETCHED
`
`APPLIED-TYPE NSULATION
`LAYER (OL 1) APPLIED
`6TH PHOTOLITHOGRAPHY
`(FOR OLI1)
`
`SiN (GI) CVD
`a-Si(S1) CVD
`n+Si(NSI) CVD
`
`3RD PHOTOLITHOGRAPHY
`(FOR a-Si)
`
`a-SETCHED
`n+SETCHED
`
`(F)
`
`(G)
`
`ITO (PX, TC2) BYSPATTERING
`
`7TH PHOTOLITHOGRAPHY
`(FOR ITO)
`
`ITO (PX, TC2) ETCHED
`
`Page 9 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 9 of 36
`
`US 6,507,383 B1
`
`FIG. 9
`
`(A)
`
`DL
`
`(D)
`
`CL 1–E
`
`
`
`E PAS 4
`
`(B)
`
`CE
`
`(C)
`
`G
`
`
`
`Page 10 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 10 Of 36
`
`US 6,507,383 B1
`
`-Adle-Eas
`
`SD GlSNSIsb
`- F - O
`
`
`
`
`
`OL1
`
`
`
`SDS GlcNSlsb
`-- - -
`TFT
`
`Page 11 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 11 of 36
`
`US 6,507,383 B1
`
`FIG 11
`
`
`
`POL2
`
`SUB2
`
`LC
`
`PAS
`DL
`G
`
`POL1
`
`OC
`
`OR2
`
`OR1
`PAS
`G
`CL
`CE
`
`Page 12 of 61
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 14, 2003
`Jan. 14, 2003
`
`Sheet 12 of 36
`Sheet 12 0f 36
`
`US 6,507,383 B1
`US 6,507,383 B1
`
`FIG. 12
`FIG. 12
`
`
`
`
`
`Page 13 of61
`
`Page 13 of 61
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 14, 2003
`Jan. 14, 2003
`
`Sheet 13 of 36
`Sheet 13 0f 36
`
`US 6,507,383 B1
`US 6,507,383 B1
`
`FIG. 13
`FIG. 13
`
`
`
`
`
`Page 14 of61
`
`Page 14 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 14 Of 36
`
`US 6,507,383 B1
`
`FIG. 14
`
`BM
`
`OR2
`
`LC
`
`OR1
`Gl
`GL
`
`SUB1
`
`BM
`
`OR2
`
`OR
`G
`
`SUB
`
`TCL
`
`POL1
`
`
`
`POL2
`SUB2
`
`OC
`
`LC
`
`PAS
`
`POL
`
`Page 15 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 15 of 36
`
`US 6,507,383 B1
`
`FIG. 15
`
`TC1
`
`GL
`
`TH
`
`
`
`Page 16 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 16 of 36
`
`US 6,507,383 B1
`
`(A)
`
`(D)
`
`ITO(CE, TC1) BY SPATTERNG
`
`Cr (DLSD) BYSPATTERING
`
`1STPHOTOLITHOGRAPHY (FOR ITO)
`
`4TH PHOTOLTHOGRAPHY
`(FOR Cr)
`
`TO (CE, TC1) ECHED)
`
`Cr ETCHED
`n-Si ETCHED
`
`(B)
`
`(E)
`
`Cr (CL, C., GE) BYSPATTERING
`
`SiN (PAS) CVD
`
`2ND PHOTOLITHOGRAPHY (FOR Cr)
`
`5THH PHOTOLTHOGRAPHY
`(FOR SIN)
`
`Cr (CL, GL, GE) ETCHED
`
`SiN (PAS) ETCHED
`SiN (GDETCHED
`
`(C)
`
`(F)
`
`SiN (G) CVD
`a-Si(S1) CVD
`n+Si(NSI) CVD
`
`3RD PHOTOLITHOGRAPHY (FOR a-Si)
`
`a-SETCHED
`n+SiTCHED
`
`ITO (PX, TC2) BY
`SPATTERNG
`6TH PHOTOLITHOGRAPHY
`(FORTIO)
`
`ITO (PX, TC2) ETCHED
`
`7TH PHOTOLITHOGRAPHY
`(FOR SIN)
`
`SiN (PAS) ETCHED
`SIN (GDETCHED
`
`Page 17 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 17 of 36
`
`US 6,507,383 B1
`
`(A)
`
`FIG. 17
`
`(D)
`
`DL a
`
`(B)
`
`CL
`
`MCN-PAS 2 -1-E
`
`(C)
`
`G
`
`PX
`
`
`
`Page 18 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 18 of 36
`
`US 6,507,383 B1
`
`FIG. 18
`
`
`
`T-47Aff
`SD SIGlcNSlsb
`V- - -
`
`SUB2
`
`
`
`(B)
`
`GE
`
`(C)
`
`S GNS
`
`
`
`
`
`Ala-N:
`12
`assile
`SDS
`SISD
`GlcN
`TH
`- - -
`
`PAS
`
`SUB
`
`Page 19 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 19 of 36
`
`US 6,507,383 B1
`
`FIG. 19
`
`POL2
`
`SUB2
`
`LC
`
`
`
`POL1
`
`::::::::::::::
`
`OR1
`
`PAS
`G
`PX
`
`Page 20 of 61
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 14, 2003
`Jan. 14, 2003
`
`Sheet 20 of 36
`Sheet 20 0f 36
`
`US 6,507,383 B1
`US 6,507,383 B1
`
`FIG. 20
`FIG. 20
`
`
`
`
`
`Page 21 of61
`
`Page 21 of 61
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 14, 2003
`Jan. 14, 2003
`
`Sheet 21 of 36
`Sheet 21 0f 36
`
`US 6,507,383 B1
`US 6,507,383 B1
`
`
`
`
`
`SUB
`
`Page 22 of 61
`
`Page 22 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 22 of 36
`
`US 6,507,383 B1
`
`FIG. 22
`
`
`
`PAS
`
`s
`
`.
`
`TH
`
`SUB1
`
`Page 23 of 61
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 14, 2003
`Jan. 14, 2003
`
`Sheet 23 of 36
`Sheet 23 0f 36
`
`US 6,507,383 B1
`US 6,507,383 B1
`
`FIG. 23
`F I G. 23
`
`(a)
`
`
`
`POL2
`
`SUBZ
`
`BM
`
`ORI2
`
`LC
` TCL
`
`PAS
`
`POL1
`
`POL2
`
`LC
`
`POL1
`
`Page 24 of 61
`
`Page 24 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 24 of 36
`
`US 6,507,383 B1
`
`FG. 24
`
`
`
`TC
`
`PAS
`G
`GL
`
`SUB
`
`Page 25 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 25 of 36
`
`US 6,507,383 B1
`
`FIG. 25
`
`(b)
`
`
`
`DTM
`
`TC2
`
`Page 26 of 61
`
`

`

`U.S. Patent
`
`Sheet 26 of 36
`
`Jan. 14, 2003
`FIG. 26
`
`US 6,507,383 B1
`
`(A)
`
`Cr (CL, GL, GE) BY sparena
`
`(E)
`
`SN (PAS) CVD,
`APPLIED-TYPE INSULATION
`LAYER (OIL2) ETCHED
`
`
`
`
`
`5THH PHOTOLITHOGRAPHY (FOR SIN)
`
`APPLEED-TYPE INSULATION
`LAYER (OIL2) ETCHED
`SiN (PAS) ETCHED
`SN (GDETCHED
`
`APPLIED-TYPE INSULATION
`LAYER (OL1) APPLIED
`
`6TH PHOTOLITHOGRAPHY (FOR OL11)
`
`TO (CE, TC2, TC3) BYSPATTERING
`
`7TH PHOTOLITHOGRAPHY (FOR ITO)
`
`ITO (CE, TC2, TC3) ETCHED
`
`
`
`
`
`
`
`
`
`OIL2 ETCHED
`SN (PAS) ETCHED
`SIN (GI) ETCHED
`
`1ST PHOTOLITHOGRAPHY (FOR Cr)
`
`Cr (CL, GL, GE) ETCHED
`
`(B)
`
`ITO (PX, TCL) BY spattend
`
`2ND PHOTOLITHOGRAPHY (FOR ITO)
`
`ITO (PX, TCL) ETCHED
`
`SiN (Gl) CVD
`a-Si(S1) CVD
`n+Si(NSI) CVD
`
`3RD PHOTOLITHOGRAPHY (FOR a-S)
`
`a-Si ETCHED
`SETCHED
`
`(D)
`
`Cr (DLSD) BY spatien
`
`4TH PHOTOLITHOGRAPHY (FOR Cr)
`
`Cr ETCHED
`n-SETCHED
`
`Page 27 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 27 Of 36
`
`US 6,507,383 B1
`
`
`
`
`
`DL
`
`PAS
`D
`G
`SUB1
`
`OL1
`
`OL1
`As
`CE
`
`Page 28 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 28 of 36
`
`US 6,507,383 B1
`
`FIG. 28
`
`(A)
`
`GE
`
`(E)
`
`SUB1
`
`it
`
`PAS
`
`(B)
`
`PX
`
`(F)
`
`
`
`TH TH
`a. N.
`1. N
`
`%3A A X-OIL
`ÉSSI f
`
`(C)
`
`S
`
`Gl NS
`
`
`
`2%2 RA 2ASA
`
`
`
`is Scrip-2
`
`- E -
`TFT
`
`
`
`2.É. A.
`ÉSSUE if
`2s, sigA
`AA
`
`
`
`Page 29 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 29 Of 36
`
`US 6,507,383 B1
`
`FIG. 29
`
`
`
`2. s % 5
`
`2EEEEEEEEEEEEEEEE
`
`WSWWSW
`WES5
`a W 1.
`1. E. E. 4.
`SSWSWS
`s WS
`LC2 AO 9.
`W 3. S. 2.
`I
`EY
`w E23
`LE
`
`A11247.2.1.21122
`
`s:
`
`y
`
`Page 30 of 61
`
`

`

`U.S. Patent
`US. Patent
`
`Jan. 14, 2003
`Jan. 14, 2003
`
`Sheet 30 Of 36
`Sheet 30 0f 36
`
`US 6,507,383 B1
`US 6,507,383 B1
`
`FIG. 3O
`FIG. 30
`
`
`
`POL2
`
`SUBZ
`
`LC
`
`OR
`OR|1
`
`CL
`
`IL
`
`PAS
`
`" "
`
`0.
`
`:
`
`w
`9'91
`.vfi
`}*.*'
`0»
`wu-
`
`I’Vfi‘é
`
`POL1
`
`Page 31 of61
`
`mam-mm-m CL
`
`Q'Q‘Q'Q .:
`gaw-
`rfi-fifiq
`an
`an
`wow
`
`9.*¢*’-D;¢Ii
`
`.A
`an
`.-
`
`Page 31 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 31 of 36
`
`US 6,507,383 B1
`
`(1)
`
`(3)
`
`5
`(5)
`
`
`
`(9)
`
`(11)
`
`
`
`
`
`
`
`
`
`
`
`
`
`ESPARENT
`ECTRODE
`P PE40WER
`TRANSPARENT
`ELECTRODE
`
`(2)
`
`UPPER
`TRANSPARENT
`ELECTRODE
`as Ess-PAS
`LOWER
`TRANSPARENT
`ELECTRODE
`
`UPPER
`TRANSPARENT
`ELECTRODE
`(4)
`5: B-1-OIL1
`2 2 LOWER
`%. 2 TRANSPARENT
`ELECTRODE
`UPPER
`
`UPPER
`TRANSPARENT
`ESTRODE
`E. E.
`1LOWER Gl
`P-3-TRANSPARENT
`ELECTRODE
`UPPER
`
`% BS
`
`(8)
`
`
`
`
`
`
`
`
`
`ESERENT
`ANSESSENT
`6
`PASG
`(6)
`:::::::::
`E. PAS-G
`LOWER
`-ELE1Lowe
`REN
`TRANSPARENT
`TR
`ELECTRODE
`IRENSEASE T
`UPPER
`UPPER
`TRANSPARENT
`TRANSPARENT
`ELECTRODE
`ELECTRODE
`Ot
`% PAS
`LOWER
`LOWER
`TRANSPARENT
`TRANSPARENT
`ELECTRODE
`ELECTRODE
`UPPER
`EiSPARENT
`TRANSPARENT
`ELECTRODE (10) a
`MELECTRODE
`E. E. Gl OL2
`% 2 OL1 PAS
`LOWER
`LOWER
`TRANSPARENT
`TRANSPARENT
`ELECTRODE
`ELECTRODE
`UPPER
`UPPER
`TRANSPARENT
`TRANSPARENT
`ANSESSENT (12)
`ELETEODE
`LOWER
`LOWER
`TRANSPARENT
`TRANSPARENT
`ELECTRODE
`ELECTRODE
`
`OIL2
`
`E:
`
`E
`
`
`
`UPPER
`TRANSPARENT
`ELECTRODE'' (14)
`OL1
`OL2
`LOWER
`TRANSPARENT
`ELECTRODE
`
`
`
`UPPER
`TRANSPARENT
`ELECTRODE
`OL1
`PAS
`G
`LOWER
`TRANSPARENT
`ELECTRODE
`
`Page 32 of 61
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`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 32 of 36
`
`US 6,507,383 B1
`
`FIG. 32
`
`UPPER
`TRANSPARENT
`ELECTRODE
`OL1
`PAS
`G
`LOWER
`TRANSPARENT
`ELECTRODE
`UPPER
`TRANSPARENT
`ELECTRODE
`OL1
`PAS Gl
`OWER
`TRANSPARENT
`ELECTRODE
`
`
`
`(20)
`
`(22
`
`LOWER
`TRANSPARENT
`ELECTRODE
`
`G
`
`UPPER
`TRANSPARENT
`ELECTRODE
`OL1
`OL2
`LOWER
`TRANSPARENT
`ELECTRODE
`
`Gl
`
`16
`(16) B,
`
`UPPER
`TRANSPARENT
`ELECTRODE
`
`LOWER
`TRANSPARENT
`ELECTRODE
`
`UPPER
`TRANSPARENT
`ELECTRODE
`
`LOWER
`TRANSPARENT
`ELECTRODE
`UPPER
`TRANSPARENT
`ELECTRODE
`2 2
`62. 2G
`LOWER
`TRANSPARENT
`ELECTRODE
`
`M
`
`UPPER
`TRANSPARENT
`ELECTRODE
`E.
`
`PAS
`LOWER
`TRANSPARENT
`ELECTRODE
`
`(15)
`
`(17)
`
`
`
`
`
`
`
`
`
`
`
`(21)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(23)
`
`(25)
`
`UPPER
`TRANSPARENT
`ELECTRODE
`B E8-OIL2
`--SNPAS
`NOIL
`LOWER
`TRANSPARENT
`ELECTRODE
`
`
`
`
`
`UPPER
`TRANSPARENT
`ELECTRODE
`OL1
`OL2
`PAS
`LOWER
`TRANSPARENT
`ELECTRODE
`
`(24)
`
`(26)
`
`UPPER
`TRANSPARENT
`ELECTRODE
`Ol2PAs
`Gl
`LOWER
`TRANSPARENT
`ELECTRODE
`
`2 2
`
`UPPER
`TRANSPARENT
`ELECTRODE
`BOL1
`OL2PAs
`LOWER
`TRANSPARENT
`ELECTRODE
`
`Page 33 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 33 of 36
`
`US 6,507,383 B1
`
`FIG. 33
`
`(27)
`
`(29)
`
`33
`(33)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(28)
`
`(30)
`
`UPPER
`RANSERENT
`CPAS
`OL2
`PAS
`LOWER
`TRANSPARENT
`ELECTRODE
`
`UPPER
`TRANSPARENT
`ELECTRODE
`OL
`
`9Éas AS
`LOWER
`TRANSPARENT
`ESSESSE
`
`UPPER
`TRANSPARENT
`
`OL1
`
`-
`
`G
`LOWER
`TRANSPARENT
`ELECTRODE
`
`(34)
`
`UPPER
`TRANSPARENT
`ELECTRODE
`OL
`OL2
`PAS
`LOWER
`TRANSPARENT
`
`ESPARENT
`ELECTRODE
`
`PAS
`LOWER
`TRANSPARENT
`ELECTRODE
`
`UPPER
`TRANSPARENT
`ELECTRODE
`
`TRANSPARENT
`ELECTRODE
`UPPER
`TRANSPARENT
`
`TRANSPARENT
`ELECTRODE
`
`UPPER
`TRANSPARENT
`ELECTRODE
`
`(35)
`
`
`
`UPPER
`TRANSPARENT (36)
`ELECTRODE
`
`LOWER
`TRANSPARENT
`ELECTRODE
`
`C
`
`Gl
`LOWER
`TRANSPARENT
`
`
`
`
`
`
`
`
`
`ESPARENT
`ELECTRODE
`OL1
`OL2
`PAS
`G
`LOWER
`TRANSPARENT
`ELECTRODE
`
`Page 34 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 34 of 36
`
`US 6,507,383 B1
`
`(a)
`UPPER TRANSPARENT
`
`asos tact 22/22/2
`INSULATION LAYER 2 x (m)
`SILICONNITRIDELAYER NE
`700nm
`LOWER TRANSPARENT.
`ELECTRODE
`
`(b)
`
`STANDARD STRUCTURE: SILICON NITRIDELAYER (e=6.7)700nm
`
`(A) SILICON NITRIDE LAYER (e=6.7) 700nm
`SILICONNITRIDE LAYER (8 =6.7)x (nm)
`(B) SILICONNITRIDE LAYER (e=6.7)700nm +
`APPLIED TYPE INSULATION LAYER (e=40)x (nm)
`
`
`
`1 O
`
`0. 8
`
`
`
`0. 6
`
`0. 4
`
`0. 2
`
`2000
`1500
`1000
`500
`O
`THICKNESS OF REDUCEDCAPACITANCE INSULATIONLAYER x (nm)
`
`Page 35 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 35 0f 36
`
`US 6,507,383 B1
`
`(a)
`POLARIZING PLATE
`
`TRANSPARENT INSULATION SUBSTRATE
`
`LOUD CRYSTALLAYER
`UPPER TRANSPARENTELECTRODE
`SILICON NITRDE LAYER
`LOWER TRANSPARENTELECTRODE
`TRANSPARENT INSULATION SUBSTRATE
`POLARIZING PLATE-
`
`FIG. 35
`
`X (nm)
`A
`
`&
`
`(b)
`
`
`
`STRUCTUREA
`SILICONNITRIDELAYER 350 nm
`STRUCTUREB
`SLICON NITRDELAYER 700 nm
`
`(C )
`
`
`
`
`
`2
`
`1 O
`
`0. 8
`
`APPLIED WOLTAGE (V)
`
`STANDARD STRUCTURE (SILICONNITRIDE 700 nm)
`
`O
`
`1500
`1000
`500
`THICKNESS OF SILICONNITRIDE x (nm)
`
`2000
`
`Page 36 of 61
`
`

`

`U.S. Patent
`
`Jan. 14, 2003
`
`Sheet 36 of 36
`
`US 6,507,383 B1
`
`(a)
`
`(b)
`
`PNHOLE IN LOWER
`TRANSPARENT
`ELECTRODE
`
`E::::::
`
`PNHOLE IN
`SENNITRIDE
`UPPER
`TRANSPARENT
`ELECTRODE
`
`SILICON
`NITRIDE
`ow. LAYER
`TRANSPARENT
`ELECTRODE
`
`SLICON
`NITRIDE
`LAYER
`
`LOWER
`TRANSPARENT
`ELECTRODE
`
`100
`
`
`
`68 OO
`
`4 O
`
`20
`
`O
`
`10
`8
`6
`4
`2
`O
`DIAMETER OF PINHOLES PRODUCED BY MELTING OF
`LOWERTRANSPARENTELECTRODE 1 (m)
`
`Page 37 of 61
`
`

`

`US 6,507,383 B1
`
`1
`IN-PLANE SWITCHING LIQUID CRYSTAL
`DISPLAY APPARATUS WITH REDUCED
`CAPACITANCE BETWEEN PIXEL
`ELECTRODES AND COMMON
`ELECTRODES
`
`TECHNICAL FIELD
`The present invention relates to a liquid crystal display
`unit and more particularly to a structure of a liquid crystal
`display unit using transparent electrodes as a pixel electrode
`and/or a common electrode.
`
`2
`distance therebetween are made minute to thereby control
`driving of the liquid crystal, a deviation in alignment of the
`two upper and lower ITO electrodes in a photolithographic
`process upon processing of the two upper and lower ITO
`electrodes and a deviation in processing dimensions produce
`uneven display characteristic as they are and more particu
`larly Scattered brightness. In order to avoid this problem, a
`method that the lower ITO electrode is formed on a Sub
`Stantially whole Surface within a unit pixel area is adopted.
`Since the lower ITO electrode is formed on the substantially
`whole Surface within the unit pixel area, it is not necessary
`to consider a deviation in alignment of the upper and lower
`ITO electrodes. Consequently, Scattering of the display
`characteristic can be reduced.
`In the related art, a parasitic capacitance connected in
`parallel to a liquid crystal layer is newly formed in a portion
`where the two upper and lower ITO electrodes constituting
`the pixel electrode and the common Signal electrode overlap
`each other through an inter-layer insulation layer. This
`parasitic capacitance can be effectively utilized as a capaci
`tance for improving the Voltage holding characteristic of the
`liquid crystal, whereas there causes a problem that a time
`required until a desired Voltage is applied to the liquid
`crystal layer, that is a writing time of a Voltage to the liquid
`crystal is increased, So that the Voltage cannot be applied to
`the liquid crystal Sufficiently, when a Voltage is applied
`between the two upper and lower ITO electrodes.
`A method of changing a structure of the insulation layer
`disposed between the two upper and lower layer ITO elec
`trodes is also one of measures for reducing the parasitic
`capacitance, although there is a problem that a driving
`Voltage of the liquid crystal is increased as described later.
`(2) Problem of Increasing Driving Voltage of Liquid Crystal
`When a Voltage is applied to the liquid crystal, a potential
`difference applied to the two upper and lower ITO electrodes
`is utilized, while an insulation layer also exists in the area
`where the insulation layer does not exist in a conventional
`Structure, that is, the area which is positioned above the
`lower ITO electrode and where the upper ITO electrode does
`not exist and the insulation layer forms a capacitance
`connected in Series to the liquid crystal between the two
`upper and lower ITO electrodes. Accordingly, part of the
`potential difference applied to the two upper and lower ITO
`electrodes is absorbed by the capacitance connected in Series
`to the liquid crystal layer. Consequently, it is necessary to
`apply between the two upper and lower ITO electrodes the
`potential difference larger than a desired Voltage to be
`applied to the liquid crystal in consideration of a Voltage
`drop.
`More particularly, there is a problem that the driving
`Voltage is increased due to the insulation layer. When the
`driving Voltage is increased, the power consumption is
`increased and the increased power consumption is not
`Suitable to a portable type liquid crystal display unit par
`ticularly. Further, when the driving Voltage is increased, a
`cheap low-voltage driver cannot be used and accordingly
`there is a problem that the liquid crystal display unit cannot
`be provided cheaply.
`In the conventional Structure, as methods of reducing the
`parasitic capacitance connected in parallel to the liquid
`crystal layer, (1) a method of increasing a thickness of an
`insulation layer between the two upper and lower ITO
`electrodes and (2) a method of changing material of the
`insulation layer and introducing material having a Small
`dielectric constant or adding a new layer are considered. In
`other words, when the number of insulation layerS is n, the
`dielectric constant of the k-th insulation layer 6 and the
`
`15
`
`25
`
`40
`
`BACKGROUND ART
`Many liquid crystal display units adopt an active matrix
`System having a structure including thin film transistors
`(TFT) as Switching elements in a display area in which
`pixels are provided. The liquid crystal display unit of this
`kind adopts a structure having a liquid crystal layer disposed
`between a pair of substrates. TFT elements, a pixel
`electrode, wiring and electrodes for Scanning Signals and
`image Signals, terminals for connecting wiring and external
`driving circuits and the like are formed on one Substrate
`(TFT substrate) and a color filter and an opposite electrode
`are formed on the other substrate (CF substrate). There is
`adopted a twisted nematic display System in which a Voltage
`is applied between the pixel electrode on one Substrate and
`the opposite electrode on the other Substrate to drive the
`liquid crystal and control display.
`In contrast to the above System, as a System capable of
`improving a Visual field angle or viewing angle and contrast
`which are problems to be solved in a liquid crystal display
`unit, JP-A-6-160878 discloses a liquid crystal display unit
`including a common Signal electrode disposed on the TFT
`35
`Substrate instead of the opposite electrode disposed on the
`Substrate on which the color filter is formed and in which a
`Voltage is applied between the pixel electrode in the form of
`teeth of a comb and the common signal electrode to drive the
`liquid crystal and control display. The pixel electrode and
`the common Signal electrode may be made of metal for
`electrodes or wiring or Indium Tin Oxide (ITO) used in a
`transparent pixel electrode.
`As an example in which the ITO electrode is used, S. H.
`Lee et al. describe in SID 98 DIGEST, p.371 (1998) and
`SID 99 DIGEST, p.202 (1999) a technique that the pixel
`electrode and the common Signal electrode are constituted
`by two ITO electrodes constituting upper and lower layers
`between which an insulation layer is disposed and a width of
`the pixel electrode in the form of teeth of a comb and the
`common signal electrode and a distance between the elec
`trodes are made minute to be optimized So that a voltage is
`applied between the two upper and lower ITO electrodes to
`drive the liquid crystal.
`
`45
`
`50
`
`55
`
`DISCLOSURE OF THE INVENTION
`In the above related art, when driving of the liquid crystal
`and a manufacturing proceSS are considered, it is understood
`that there are two problems in regard to the driving of the
`liquid crystal and two problems in regard to the process due
`to a cross-sectional Structure.
`The problems will be described.
`(1) Problem of Increasing Writing Time of Voltage to Liquid
`Crystal
`In the related art, since the width of the two upper and
`lower ITO electrodes formed into teeth of a comb and the
`
`60
`
`65
`
`Page 38 of 61
`
`

`

`3
`thickness thereof d in the portion where the two upper and
`lower ITO electrodes overlap each other, SA defined by
`
`US 6,507,383 B1
`
`1
`
`d
`
`4
`peripheral portion of the Silicon nitride layer constituting the
`inter-layer insulation layer tend to be produced.
`When the crack, pinhole and coating defect in the periph
`eral portion are produced in a portion where the two upper
`and lower ITO electrodes overlap each other, there occurs a
`problem that an insulation defect is caused between the
`upper and lower ITO electrodes and the two upper and lower
`ITO electrodes are short-circuited.
`(4) Problem of Melting of Lower Transparent Electrode,
`Metal Wiring and Metal Electrode Upon Processing of
`Upper Transparent Electrode
`Generally, the wet etching method is used for processing
`of the upper ITO electrode layer. Solution of strong acid
`Such as hydracid bromide, hydrochloric acid, aqua regia
`(Solution of hydrochloric acid and nitric acid), hydrochloric
`acid Solution of ferric chloride is used as an etching liquid.
`When the upper ITO electrode is processed, the insulation
`layer formed on the lower ITO electrode serves to protect the
`lower transparent electrode, although when there is a defec
`tive portion Such as crack, pinhole and coating defect in the
`peripheral portion, wet etching Solution of the ITO layer
`permeates the insulation layer through the defective portion.
`When the surface of the lower ITO electrode is directly
`exposed to the permeated etching Solution, the lower ITO
`electrode is melted and wiring is broken. Further, there is a
`possibility that an electrode and wiring of metal disposed in
`a layer lower than the upper ITO electrode are also corroded
`due to the same phenomenon.
`It is an object of the present invention to provide a panel
`of a liquid crystal display unit including a pixel electrode PX
`and a common Signal electrode constituted by two upper and
`lower transparent conductive layerS having insulation layers
`disposed therebetween, which can reduce any one or both of
`a writing time to a liquid crystal and a driving Voltage of the
`liquid crystal and has excellent numerical aperture and
`transmission factor.
`Further, it is another object of the present invention to
`provide a structure which can attain reduction of defect Such
`as corrosion and disconnection of an electrode constituted
`by the transparent conductive layer disposed in the lower
`layer and an electrode and wiring made of material, caused
`through a defective portion of the insulation layer when the
`transparent conductive layer disposed in the upper layer is
`processed through the insulation layer by etching and reduc
`tion of short-circuit defect due to defective insulation of the
`two upper and lower transparent electrodes and can be
`fabricated with good yield.
`A liquid crystal display unit according to an embodiment
`1 of the present invention includes a pair of Substrate, a
`liquid crystal layer disposed between the pair of Substrates,
`a plurality of Scanning Signal lines, a plurality of image
`Signal lines interSecting the plurality of image Signal lines in
`matrix manner and a plurality of thin film transistors each
`formed in the vicinity of each intersection between the
`Scanning Signal lines and the image Signal lines disposed on
`one (first Substrate) of the Substrates, a plurality of pixels at
`least one of which is formed in each area enclosed by the
`plurality of Scanning Signal lines and image Signal lines and
`each of which includes a common Signal electrode con
`nected acroSS a plurality of pixels and a pixel electrode
`connected to the thin film transistor corresponding thereto,
`the common Signal electrode and the pixel electrode par
`tially overlapping each other through an inter-layer insula
`tion layer, at least part of each of the pixel electrode and the
`common Signal electrode being constituted by a transparent
`conductive layer, one of the pixel electrode and the common
`Signal electrode disposed on the Side of the liquid crystal
`
`15
`
`25
`
`is made Small to thereby reduce the parasitic capacitance. In
`the conventional Structure, however, when the parasitic
`capacitance is reduced, SA of the insulation layer existing in
`an area which is positioned above the lower ITO electrode
`and where the upper ITO electrode does not exist, that is, the
`insulation layer forming the capacitance connected in Series
`to the liquid crystal layer is also made Small to thereby
`reduce the capacitance connected in Series to the liquid
`crystal layer. Consequently, a Voltage drop due to the capaci
`tance connected in Series to the liquid crystal is increased to
`thereby increase the driving Voltage of the liquid crystal.
`Conversely, in order to reduce the driving Voltage of the
`liquid crystal, when SA of the insulation layer disposed in an
`area which is positioned above the lower ITO electrode and
`where the upper ITO electrode does not exist, that is, the
`insulation layer forming the capacitance connected in Series
`to the liquid crystal layer is increased, SA of the inter-layer
`insulation layer, that is, the insulation layer forming the
`parasitic capacitance connected in parallel to the liquid
`crystal layer is also increased, So that the parasitic capaci
`tance is increased in this case. AS described above, in the
`conventional Structure, the reduction of the writing Voltage
`to the liquid crystal and the driving Voltage of the liquid
`crystal have the trade-off relation and it is impossible to
`reduce the capacitance connected in parallel to the liquid
`crystal and increase the capacitance connected in Series to
`the liquid crystal.
`The problem of processing due to the cross-sectional
`Structure is now described.
`(3) Problem of Short-Circuit Between Two Upper and
`Lower Transparent Electrodes
`Generally, a silicon nitride layer formed by the CVD
`40
`method, for example, is used for the insulation layer of TFT
`elements. For example, MonoSilane, ammonia or the like is
`used as reaction gas and accordingly the atmosphere for
`forming layerS is the atmosphere of reduction plasma con
`taining active hydrogen. Therefore, when the Silicon nitride
`layer is formed on the ITO layers constituting the two upper
`and lower transparent electrodes, the surface of the ITO
`layers constituting the transparent conductive layers of oxide
`is exposed to the atmosphere of reduction plasma. It is
`known that the ITO surface is reduced depending on the
`forming condition and the Silicon nitride layer is grown on
`the ITO extraordinarily (Jpn. J. appl. Phys., 32, p.5072
`(1993)). Unevenness of the surface of obtained laminated
`layers becomes remarkable due to the extraordinary growth,
`and minuteneSS and insulation characteristics of the Silicon
`nitride layer itself are reduced. The more the flow rate of the
`reaction gas which is a Supply Source of active hydrogen and
`the higher a temperature of a Substrate, the more the reaction
`of the extraordinary growth of the Silicon nitride layer is
`accelerated. However, in order to obtain a good quality
`Silicon nitride layer for a gate insulation layer of a thin film
`transistor, it is necessary to maintain the temperature of the
`Substrate to be as high a temperature as about 300 degrees
`and the layer is formed on the condition that the extraordi
`nary growth tends to be generated. Accordingly, the proceSS
`that the silicon nitride layer is formed on the ITO layer is in
`a situation that crack, pinhole and coating defect in a
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Page 39 of 61
`
`

`

`S
`layer through an insulation layer being formed into slits or
`teeth of a comb, and further comprises the following means.
`(1) The inter-layer insulation layer includes at least one
`insulation layer or more except a first insulation layer
`having function of a gate insulation layer of the thin film
`transistor and a Second insulation layer having function of
`a Surface protection layer of the thin film transistor and at
`least one insulation layer or more except the Surface
`protection layer of the thin film transistor and the gate
`insulation layer included in the inter-layer insulation layer
`is Selectively formed in conformity with a Second elec
`trode in an area where the Second electrode is disposed
`rather than an area which is positioned above a first
`electrode of the pixel electrode and the common Signal
`electrode, nearer to the first electrode through the insula
`tion layer and where the Second electrode does not exist.
`(2) In a structure in which a liquid crystal having A6 of a
`negative value is used as the liquid crystal layer, when
`
`is SA where the number of insulation layers included in
`the inter-layer insulation layer is n and a dielectric con
`Stant of a k-th insulation layer is 6, a thickness thereof
`being d, and
`
`(where me 1) is S, where the number of insulation layers
`disposed between a first orientation layer disposed above
`a first Substrate and a first electrode of the pixel electrode
`and the common electrode, nearer to the first Substrate
`through insulation layers in an area which is positioned
`above the first electrode and where a Second electrode
`does not exist is m and a dielectric constant of an
`insulation layer constituting a first layer is 6, a thickneSS
`thereof being d, a dielectric constant of a liquid crystal in
`a vertical direction to a director of the liquid crystal being
`€, SA-S is Satisfied.
`(3) In a structure in which a liquid crystal having A6 of a
`positive value is used as the liquid crystal layer, when
`
`1
`
`d
`
`US 6,507,383 B1
`
`6
`a first Substrate and a first electrode of the pixel electrode
`and the common electrode, nearer to the first Substrate
`through insulation layers in an area which is positioned
`above the first electrode and where a Second electrode
`does not exist is m and a dielectric constant of an
`insulation layer constituting a first layer is 6, a thickness
`thereof being d, a dielectric constant of a liquid crystal in
`the parallel direction to a director of the liquid crystal
`being ec, SA-S is Satisfied.
`(4) In the structure in which a liquid crystal having A6 of a
`negative value is used as the liquid crystal layer, when
`
`15
`
`3O
`
`35
`
`40
`
`45
`
`50
`
`1
`
`d
`
`is SA where any insulation layer does not exist between
`the first orientation layer disposed above the first substrate
`and the first electrode in the area which is positioned
`above the first electrode of the pixel electrode and the
`common electrode nearer to the first Substrate through the
`insulation layers and where the Second electrode does not
`exist and the number of insulation layers included the
`inter-layer insulation layer is n, a dielectric constant of the
`k-th insulation layer being 6, a thickness thereof being d.
`and
`
`is S, where a dielectric constant of the liquid crystal in the
`vertical direction to the director of the liquid crystal is
`e., SA-S is Satisfied.
`(5) In the structure in which a liquid crystal having A6 of a
`positive value is used as the liquid crystal layer, when
`
`1
`
`d
`
`is SA where any insulation layer does not exist between
`the first orientation layer disposed above the first substrate
`and the first electrode in the area which is positioned
`above the first electrode of the pixel electrode and the
`co