(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2001/0009447 A1
`(43) Pub. Date:
`Jul. 26, 2001
`Ohta et al.
`
`US 2001 OOO9447A1
`
`(54) LIQUID CRYSTAL DISPLAY DEVICE
`(76) Inventors: Masuyuki Ohta, Mobara-shi (JP);
`Masahiro Ishi, Mobara-shi (JP); Kikuo
`Ono, Mobara-shi (JP); Nobuyuki
`Suzuki, Mobara-shi (JP)
`
`Correspondence Address:
`ANTONELL TERRY STOUT AND KRAUS
`SUTE 1800
`1300 NORTH SEVENTEENTH STREET
`ARLINGTON, VA 22209
`
`(21)
`(22)
`
`Appl. No.:
`
`09/793,921
`
`Filed:
`
`Feb. 28, 2001
`
`Related U.S. Application Data
`(63) Continuation of application No. 09/402,645, filed on
`Oct. 8, 1999, now Pat. No. 6,208,399, which is a 371
`of international application No. PCT/JP98/01500,
`filed on Apr. 1, 1998.
`
`(30)
`
`Foreign Application Priority Data
`
`Apr. 11, 1997 (JP)............................................... 9-93440
`
`Publication Classification
`
`(51) Int. Cl." ........................ G02F 1/136; G02F 1/1333;
`GO2F 1/1343
`(52) U.S. Cl. ............................. 349/43; 349/139; 34.9/138
`
`(57)
`
`ABSTRACT
`
`An active matrix type liquid crystal display device including
`first and Second Substrates, a liquid crystal composition layer
`provided between the first and Second Substrates, a plurality
`of drain lines and gate lines formed on the first Substrate and
`crossing each other in a matrix form, a plurality of counter
`lines formed on the first Substrate, and a plurality of pixels
`formed by adjoining the drain lines and the gate lines. At
`least one counter electrode is formed on one of the drain
`lines with an insulating layer therebetween. Alayer on which
`one of the counter lines is formed and a layer on which the
`at least one counter electrode formed are different, and the
`one of the counter lines and the at least one counter electrode
`for one of the pixels are connected via a through hole.
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`Page 1 of 40
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`Tianma Exhibit 1006
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 1 of 25 US 2001/0009447 A1
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`Page 2 of 40
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`

`

`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 2 of 25 US 2001/0009447 A1
`
`FIG. 2
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`

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`Patent Application Publication
`
`Jul. 26, 2001 Sheet 3 of 25 US 2001/0009447 A1
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`

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`Patent Application Publication
`Jul. 26, 2001 Sheet 4 of 25 US 2001/0009447 A1
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`Patent Application Publication
`
`Jul. 26, 2001
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`Sheet 5 of 25 US 2001/0009447 A1
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`Page 6 of 40
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`

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`Patent Application Publication
`
`Jul. 26, 2001
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`Patent Application Publication
`
`Jul. 26, 2001
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`Sheet 8 of 25 US 2001/0009447 A1
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`Patent Application Publication
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`Jul. 26, 2001 Sheet 9 of 25 US 2001/0009447 A1
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`Page 10 of 40
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`Patent Application Publication
`Jul. 26, 2001 Sheet 10 of 25 US 2001/0009447 A1
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`Patent Application Publication
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`Jul. 26, 2001
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`Sheet 11 of 25 US 2001/0009447 A1
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`

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`Patent Application Publication
`
`Jul. 26, 2001
`Sheet 12 of 25 US 2001/0009447 A1
`FIG. 12
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`Page 13 of 40
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`

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`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 13 of 25 US 2001/0009447 A1
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`

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`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 14 of 25 US 2001/0009447 A1
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`

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`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 15 of 25 US 2001/0009447 A1
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`

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`Patent Application Publication
`
`Jul. 26, 2001 Sheet 16 of 25 US 2001/0009447 A1
`
`FIG. 16
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`Page 17 of 40
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001 Sheet 17 of 25 US 2001/0009447 A1
`
`FIG. 17
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`Page 18 of 40
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001
`Sheet 18 of 25 US 2001/0009447 A1
`FIG. 18
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`Page 19 of 40
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001
`FIG. 19
`
`Sheet 19 of 25 US 2001/0009447 A1
`
`SHD-Shild Case
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`Page 20 of 40
`
`

`

`Patent Application Publication
`
`Drain Line
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`Sheet 20 of 25 US 2001/0009447 A1
`Jul. 26, 2001
`FIG. 20
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`Page 21 of 40
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 21 of 25 US 2001/0009447 A1
`
`FIG. 21
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`Page 22 of 40
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 22 of 25 US 2001/0009447 A1
`
`FIG. 22
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`Page 23 of 40
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 23 of 25 US 2001/0009447 A1
`
`FIG. 23
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`
`

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`Patent Application Publication
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`Jul. 26, 2001
`
`Sheet 24 of 25 US 2001/0009447 A1
`
`FIG. 24
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`Page 25 of 40
`
`

`

`Patent Application Publication
`
`Jul. 26, 2001
`
`Sheet 25 of 25 US 2001/0009447 A1
`
`FIG. 25
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`Page 26 of 40
`
`

`

`US 2001/0009447 A1
`
`Jul. 26, 2001
`
`LIQUID CRYSTAL DISPLAY DEVICE
`
`CROSS REFERENCE TO RELATED
`APPLICATION
`0001. This is a continuation of U.S. application Ser. No.
`09/402,645, filed Oct. 8, 1999, the subject matter of which
`is incorporated by reference herein.
`
`FIELD OF THE INVENTION
`0002 This invention relates to a liquid crystal display
`device; and, more particularly, the invention relates to a high
`picture quality image active matrix System liquid crystal
`display device having thin film transistor elements.
`
`BACKGROUND OF THE INVENTION
`0003) A so-called transverse electric field system color
`liquid crystal display device is constructed Such that trans
`parent Substrates are disposed in an opposed manner with a
`liquid crystal layer interposed therebetween, electrodes for
`display and reference electrodes are provided on liquid
`crystal-Side Surfaces of regions of one or both of the trans
`parent Substrates which correspond to respective unit pixels,
`and electric fields are generated between these display
`electrodes and the reference electrodes parallel to the Sur
`faces of the transparent Substrates So as to modulate light
`which is transmitted through the liquid crystal layer. Such a
`color liquid crystal display device has been known to have
`a So-called excellent broad Visual field angle which allows a
`person to recognize a clear image even from a position
`which is at a large angle relative to the display Screen.
`0004 Liquid crystal display devices having such a con
`Struction are described in detail in, for example, Japanese
`publication of the translation of international patent appli
`cation Hei 5-505247, Japanese patent publication Sho
`63-21907 and Japanese laid-open patent publication Hei
`6-160878.
`0005. However, a liquid crystal display element having
`the above-mentioned construction Still has a problem in that
`an unnecessary electric field generated by the drain lines
`causes fluctuation of an electric field between the display
`electrodes and the reference electrodes, and So a bad image
`quality in which Stripes are produced in a direction along the
`drain lines, or a So-called longitudinal Smear (crosstalk),
`occurs. Means for solving this problem has been described
`in Japanese laid-open patent publication Hei 6-202127. The
`liquid crystal display element having the disclosed construc
`tion, however, is provided with Shield electrodes and an
`electric potential is Supplied from the outside; and, hence, it
`Still has problems in that the charging or discharging of an
`electric current to a capacitance between the Shield elec
`trodes and the Signal electrodes is large, the load on the drive
`circuit is large thus making the power consumption large and
`the drive circuit large, and a connecting means for applying
`the electric potential to the Shield electrodes becomes nec
`essary, thus increasing the StepS and giving rise to connec
`tion failures.
`0006 The present invention has been made in view of the
`foregoing problems, and it is an object of the present
`invention to provide a liquid crystal display device which
`can Suppress the occurrence of longitudinal Smear and
`enhance the productivity, while also enabling a low power
`consumption.
`
`SUMMARY OF THE INVENTION
`0007 To achieve the above object, the present invention
`is constituted by an active matrix System liquid crystal
`display device which includes a plurality of pixels which are
`composed of a plurality of drain lines and a plurality of
`Scanning electrodes, and includes pixel electrodes and
`counter electrodes which are capable of applying an electric
`field parallel to Substrate Surfaces in the pixels, and image
`Signals are capable of being Supplied to the pixel electrodes
`from thin film transistors connected to the drain lines and
`gate lines, wherein the counter electrodes and the pixel
`electrodes are formed linearly So as not to overlap each other
`in a planar condition, and an insulating film having a specific
`dielectric constant not greater than 4 is formed on the drain
`line, and the counter electrodes are formed on the insulating
`film such that they cover the drain lines.
`0008. The invention is further constituted by an active
`matrix System liquid crystal display device, as described
`above, in which the pixel electrodes are formed on the
`insulating film.
`0009. The is further constituted by an active matrix
`System liquid crystal display device, as described above, in
`which the insulating film and at least either one of a gate
`insulating film and a passivation layer of the thin film
`transistor element are formed in the same pattern.
`0010. The invention is further constituted by an active
`matrix System liquid crystal display device, as described
`above, having light Shielding films extending horizontally in
`Stripes.
`0011. The invention is constituted by an active matrix
`System liquid crystal display device, as described above,
`which has an insulating film having a film thickness of not
`Smaller than 1 um and not greater than 3 um.
`0012. The invention is constituted by an active matrix
`System liquid crystal display device, as described above,
`which an the insulating film made of a resist material.
`0013 The invention is constituted by an active matrix
`System liquid crystal display device, as described above, in
`which an inorganic insulating film which protects the thin
`film transistor element has a film thickness of not Smaller
`than 0.05 um and not greater than 0.3 um.
`0014. The liquid crystal display element having the
`above-mentioned construction is produced from the follow
`ing three operations.
`
`Operation 1
`0015 Reference electrodes are formed on an organic
`insulating film in Such a manner that the reference electrodes
`are completely overlapped on drain lines formed on one
`transparent Substrate Side in a plan view, and, hence, almost
`all of the unnecessary lines of electric force which are
`generated by the drain lines are terminated at the reference
`electrodes. Ac6ordingly, the crosstalk due to the leakage
`electric field which is peculiar to a display System, Such as
`the display System of the present invention which adopts a
`transverse electric field, can be resolved. In this manner, the
`leakage electric field is more completely shielded than it
`would be by the shield electrodes which have been conven
`tionally disposed at both sides of the drain line or on the
`counter Substrate; and, hence, the horizontal direction of the
`
`Page 27 of 40
`
`

`

`US 2001/0009447 A1
`
`Jul. 26, 2001
`
`pixels can be occupied by the display electrodes, reference
`electrodes and opening portions. Furthermore, it is also
`unnecessary to hide the gap between the drain line and the
`reference electrode, and, hence, a light insulating film (black
`matrix) in a vertical direction can be eliminated. Therefore,
`a low aperture efficiency, which is the largest defect in the
`display System adopting a transverse electric field, can be
`drastically improved and an aperture efficiency exceeding
`50% can be realized. Namely, according to the present
`invention, a high aperture efficiency and a low Smear con
`dition are compatible.
`
`Operation 2
`0016. The specific dielectric constant of the organic insu
`lating film is approximately half (the specific dielectric
`constant er being approximately 3) that of the inorganic
`insulating film. Furthermore, Since the thickness of the
`organic passivation layer can be easily increased compared
`to the inorganic passivation layer, the distance between the
`drain line and the reference electrode is expanded. Even
`when these drain lines are entirely covered with the refer
`ence electrodes, the capacity formed between the drain lines
`and the reference electrodes can be made considerably
`Small. Accordingly, the load as Seen from the drain lines is
`reduced, So that the wiring propagation delay of the image
`Signal becomes Small, and the Signal Voltage is Sufficiently
`charged into the display electrodes and the drive circuit for
`driving the drain lines can be minimized.
`Operation 3
`0.017. The organic passivation layer has an excellent
`flatneSS So that when the organic passivation layer is coated
`on the uppermost layer of the Substrate which constitutes an
`active element, the flatness of the Substrate which constitutes
`the active element is enhanced. Accordingly, the irregulari
`ties of the brightness (transmission factor)-voltage char
`acteristics caused by the irregularities of the gap between the
`Substrates can be eliminated thus enhancing the uniformity
`of the brightness.
`
`BRIEF EXPLANATION OF THE DRAWINGS
`0.018
`FIG. 1 is a plan view of an essential part showing
`one pixel and a peripheral portion of a liquid crystal display
`portion of an active matrix System color liquid crystal
`display device representing an embodiment of the present
`invention.
`0.019
`FIG. 2 is a cross sectional view of the pixel taken
`along a line 6-6 of FIG. 1.
`0020 FIG. 3 is a cross sectional view of a thin film
`transistor element TFT taken along a line 7-7 of FIG. 1.
`0021
`FIG. 4 is a cross sectional view of an accumulated
`capacitance Cstg taken along a line 8-8 of FIG. 1.
`0022 FIG. 5 is a plan view showing the construction of
`a matrix peripheral portion of a display panel.
`0023 FIG. 6 is a cross sectional view of a panel marginal
`portion without Scanning Signal terminals at the left Side and
`external connecting terminals at the right Side.
`0024 FIGS. 7A and 7B are plan and cross sectional
`Views, respectively, showing the vicinity of a connecting
`portion between a gate terminal GTM and a gate line GL.
`
`0025 FIGS. 8A and 8B are plan and cross sectional
`Views, respectively, showing the vicinity of a connecting
`portion between a drain terminal DTM and a drain line DL.
`0026 FIGS. 9A and 9B are plan and cross sectional
`Views, respectively, showing the vicinity of a connecting
`portion between a common electrode terminal CTM1, a
`common bus line CB1 and a common Voltage Signal line CL.
`0027 FIGS. 10A and 10B are plan and cross sectional
`Views, respectively, showing the vicinity of a connecting
`portion between a common electrode terminal CTM2, a
`common bus line CB2 and a common Voltage Signal line CL.
`0028 FIG. 11 is a circuit block diagram of the matrix
`portion and its periphery of the active matrix System color
`liquid crystal display device of the present invention.
`0029 FIG. 12 is a waveform diagram showing a drive
`waveform of the active matrix System color liquid crystal
`display device of FIG. 1.
`0030 FIG. 13 is a flow chart of a pixel portion and a gate
`terminal portion in croSS Section showing manufacturing
`steps A-C in the manufacture of the substrate SUB1 side.
`0031
`FIG. 14 is a flow chart of a pixel portion and a gate
`terminal portion in croSS Section showing manufacturing
`steps D-E in the manufacture of the substrate SUB1 side.
`0032 FIG. 15 is a flow chart of a pixel portion and a gate
`terminal portion in croSS Section showing manufacturing
`steps F-G in the manufacture of the Substrate SUB1 side.
`0033 FIG. 16 is a top plan view showing a condition in
`which peripheral drive circuits are mounted on a liquid
`crystal display panel.
`0034 FIG. 17 is a sectional view showing the cross
`Sectional Structure of a tape carrier package TCP in which
`integral circuit chipS CH1 which constitute a drive circuit
`are mounted on a flexible wiring Substrate.
`0035 FIG. 18 is a cross sectional view of essential parts
`of in a condition in which the tape carrier package TCP is
`connected to a Scanning Signal circuit terminal GTM of a
`liquid crystal display panel PNL.
`0036 FIG. 19 is an exploded perspective view of a liquid
`crystal display module.
`0037 FIG. 20 is a plan view of essential parts showing
`one pixel and its periphery of a liquid crystal display portion
`of an active matrix System color liquid crystal display device
`representing another embodiment of the present invention.
`0038 FIG. 21 is a cross sectional view of a comb
`electrode portion of the active matrix System color liquid
`crystal display device of FIG. 20.
`0039 FIG. 22 is a cross sectional view of a comb
`electrode portion of the active matrix System color liquid
`crystal display device representing a further embodiment of
`the present invention.
`0040 FIG. 23 is a plan view of an essential part showing
`one pixel and its periphery of a liquid crystal display part of
`an active matrix System color liquid crystal display device of
`still another embodiment of the present invention.
`0041
`FIG. 24 is a plan view of an essential part showing
`one pixel and its periphery of a liquid crystal display part of
`
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`US 2001/0009447 A1
`
`Jul. 26, 2001
`
`an active matrix System color liquid crystal display device of
`a still further embodiment of the present invention.
`0.042
`FIG. 25 is a cross sectional view of a comb
`electrode portion of the active matrix System color liquid
`crystal display device of FIG. 24.
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`0043. The present invention, other objects of the present
`invention and other features of the present invention will be
`clearly understood from the following explanation and the
`accompanying drawings.
`
`Embodiment 1
`0044 Active Matrix Liquid Crystal Display Devices
`0.045. Hereinafter, an embodiment where the present
`invention is applied to an active matrix System color liquid
`crystal display device will be explained. In the drawings,
`elements which have the same function are indicated by the
`Same Symbols and a repeated explanation thereof is omitted.
`0046 Planar Construction of the Matrix Portion (Pixel
`Portion)
`0047 FIG. 1 is a plan view showing one pixel and its
`periphery of the active matrix System color liquid crystal
`display device of the present invention.
`0.048. As shown in FIG. 1, each pixel is disposed in an
`interSect region (region enclosed by four signal lines)
`defined by a gate line (Scanning Signal line or a horizontal
`Signal line) GL, a counter line (counter Voltage signal line)
`CL, and two neighboring drain lines (image Signal lines or
`vertical signal lines) DL. Each pixel includes a thin film
`transistor TFT, a storage capacitance Cstg, a pixel electrode
`PX (called a pixel electrode in this embodiment and acts as
`a display electrode) and a counter electrode CT (called a
`counter electrode in this embodiment and means a reference
`electrode). The gate lines GL and the counter lines CL
`extend in a left to right direction in the drawing and are
`distributed in plural numbers in an upward to downward
`direction. The drain lines DL extend in an upward to
`downward direction in the drawing and are disposed in
`plural numbers in a left to right direction. The pixel elec
`trodes PX are electrically connected to the thin film tran
`sistor TFT by way of source electrodes SD1, and the counter
`electrodes CT are also electrically connected to the counter
`lines CL.
`0049. The pixel electrode PX and the counter electrode
`CT oppose each other and an optical condition of a liquid
`crystal composition LC is controlled by an electric field
`approximately parallel to the Surface of the Substrate which
`is generated between each pixel electrode PX and the
`counter electrode CT, and, hence, the display is controlled.
`The pixel electrodes PX and the counter electrodes CT are
`constructed like a comb and are respectively formed of thin
`electrodes elongated in an upward to downward direction in
`the drawing.
`0050. The electrode widths of the pixel electrodes PX and
`the counter electrodes CT are 6 um respectively. This means
`that to apply a Sufficient electric field to the entire liquid
`crystal layer in the direction of thickness of the liquid crystal
`layer, they are Set to values Sufficiently greater than 3.9 um,
`
`which is the thickness of the liquid crystal composition
`layer, as will be explained later. They may preferably be set
`to 1.5 times greater than the thickness of the liquid crystal
`composition layer. Furthermore, to increase the aperture
`efficiency, they are made as thin as possible. Furthermore,
`the drain lines DL are also Set to 6 um. To prevent a
`disconnection, the electrode width of the drain line DL may
`be slightly widened compared to the pixel electrodes PX and
`the counter electrodes CT.
`0051. The width of the gate lines GL is set such that they
`meet a resistance value Sufficient to propagate the Scanning
`Voltage to the gate electrode GT of the pixel at the tail end
`(side opposite to gate electrode terminals GTM which will
`be explained later). Furthermore, the width of the counter
`line CL is Set Such that it will have a resistance value
`Sufficient to apply a counter Voltage to the counter electrode
`CT of the pixel at the tail end (the pixel remotest from the
`common bus lines CB1, CB2 which will be explained later,
`namely, the pixel interposed between CB1 and CB2).
`0052 On the other hand, the electrode interval between
`the pixel electrode PX and the counter electrode CT varies
`depending on the liquid crystal material being used. This
`means that, Since the intensity of the electric field which
`achieves the maximum transmissivity depends on the liquid
`crystal material, the electrode interval is Set depending on
`the liquid crystal material, and the electrode interval is Set
`Such that the maximum transmissivity is obtained in a range
`of the maximum amplitude of the signal voltage set corre
`sponding to the pressure resistance of the drain drive circuit
`(signal side driver) being used. In case a liquid material
`which will be explained later is used, the interval between
`electrodes is approximately 15 lum.
`0053 Cross Sectional Construction of the Matrix Portion
`(Pixel Portion)
`0054 FIG. 2 is a view showing the cross section taken
`along a line 6-6 of FIG. 1, FIG. 3 is a cross sectional view
`of the thin film transistor TFT taken along a line 7-7 of FIG.
`1, and FIG. 4 is a view showing the cross section of the
`Storage capacitance Cstg taken along a line 8-8 of FIG.1. AS
`shown in FIG. 5 to FIG. 7B, with a liquid crystal compo
`sition layer LC as a reference, the thin film transistor TFT,
`the Storage capacitance Cstg and a group of electrodes are
`formed at a lower portion transparent glass Substrate SUB1
`side, while a color filter FIL and a light blocking film (black
`matrix) BM are formed at an upper portion transparent glass
`Substrate SUB2 side.
`0055) Furthermore, orientation films ORI1, ORI2 are
`mounted on respective Surfaces of the inner Sides (liquid
`crystal LC sides) of the transparent glass substrates SUB1,
`SUB2, which orientation films ORI1, ORI2 control the
`initial orientation of the liquid crystals, and on respective
`Surfaces of the outer sides (liquid crystal LC sides) of the
`transparent glass Substrates SUB1, SUB2, polarizing plates
`are mounted.
`005.6) TFT Substrate
`0057 First of all, the construction of the lower-side
`transparent glass substrate SUB1 (TFT substrate) will be
`explained in detail.
`
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`US 2001/0009447 A1
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`Jul. 26, 2001
`
`0058. Thin Film Transistor TFT
`0059) The thin film transistor TFT is operated such that
`when a positive bias is applied to the gate electrode GT, the
`channel resistance between the Source and drain is reduced,
`and when the bias becomes Zero, the channel resistance is
`increased.
`0060. As shown in FIG. 3, the thin film transistor TFT
`includes the gate electrode GT, an insulating film GI, an
`i-type semiconductor layer AS made of an i-type (intrinsic or
`not doped with conductive type determination impurities)
`amorphous Silicon (Si), a pair of Source electrodes SD1, and
`the drain electrodes SD2. The Source and drain are originally
`determined based on the bias polarity between them, and the
`polarity is inverted during the operation of the circuit in this
`liquid crystal display device; and, hence, it should be
`understood that the Source and drain are Switched during
`operation. In the following explanation, however, for the
`Sake of convenience, one is consistently referred to as the
`Source, while the other is referred to as the drain.
`0061 Gate Electrode GT
`0062) The gate electrode GT is constructed such that it is
`contiguous with the gate line GL and a partial region of the
`gate line GL constitutes the gate electrode GT. The gate
`electrode GT is a portion which extends over an active
`region of the thin film transistor TFT. In this embodiment,
`the gate electrode GT is made of a conductive film g3 having
`a single layer construction. Although a chrome-molybdenum
`alloy (Cr-Mo) film formed by spattering may be used as
`the conductive film g3, for example, the film is not limited
`to Such material.
`0063 Gate Line GL
`0064. The gate line GL is composed of the conductive
`film g3. The conductive film g3 of this gate line GL is
`formed in the same manufacturing Step as the conductive
`film g3 of the gate electrode GT and is formed integrally
`with the conductive film g3 of the gate electrode GT. By
`means of this gate line GL, a gate voltage (a Scanning
`voltage) Vg is Supplied to the gate electrode GT from an
`external circuit. In this embodiment, a chrome-molybdenum
`alloy (Cr-Mo) film formed by spattering may be used as
`the conductive film g3, for example. Furthermore, the gate
`line GL and the gate electrode GT are not limited to the
`chrome-molybdenum alloy and may have a two layer Struc
`ture in which aluminum or aluminum alloy is wrapped by
`chromemolybdenum for lowering the resistance. Still fur
`thermore, a portion where the drain line DL and the gate line
`GL intersect is made narrow to minimize the probability of
`a short circuit with drain line DL. Alternately, the portion
`may be bifurcated So as to be cut out by laser trimming even
`when short-circuiting occurs.
`0065 Counter Line CL
`0.066 The counter line CL is composed of the conductive
`film g3. The conductive film g3 of this counter line CL is
`formed in the same Step as the conductive films g3 of the
`gate electrode CT, the gate line GL and the counter electrode
`GT and is constructed to be electrically connected to the
`counter electrode CT. By means of this counter line CL, a
`counter Voltage Vcom is Supplied to the counter electrode
`CT from the outside. Furthermore, the counter line CL is not
`limited to the chrome-molybdenum alloy and may have a
`
`two layer Structure in which aluminum or aluminum alloy is
`wrapped by chromemolybdenum for lowering the resis
`tance. Still furthermore, a portion where the drain line DL
`and the counter line CL interSect is made narrow to mini
`mize the probability of a short circuit with drain line DL.
`Alternately, the portion may be bifurcated So as to be cut out
`by laser trimming even when a short-circuit occurs.
`Insulating Film GI
`0067
`0068. In the thin film transistor TFT, the insulating film
`GI is used as a gate insulating film for applying an electric
`field to the Semiconductor layer AS together with the gate
`electrode GT. The insulating film GI is formed on the gate
`electrode GT and the upper layer of the gate line GL. AS the
`insulating film GI, a Silicon nitride film formed by a plasma
`CVD method, for example, can be chosen and the formed
`film has a thickness of 2000 4500 A (approximately 3500
`A). Furthermore, the insulating film GI also works as an
`interlayer insulating film among the gate line GL, the
`counter line CL and the drain line DL, thus contributing to
`their electrical insulation.
`I-Type Semiconductor Layer AS
`0069
`0070 The i-type semiconductor layer AS is made of an
`amorphous silicon and is formed to a thickness of 150-2500
`A (approximately 1200 A in this embodiment). A layer d0 is
`a N(+) type amorphous Silicon Semiconductor layer doped
`with phosphor (P) for an ohmic contact and is retained only
`at positions where the i-type Semiconductor layer AS is
`present at a lower Side thereof and the conductive layer d3
`is present at an upper side thereof.
`0071. The i-type semiconductor layers AS and the layer
`d0 are also provided between intersecting portions