United States Patent
`
`[19]
`
`_
`
`[11] Patent Number:
`
`5,452,239
`
`Dai et al.
`
`[45] Date of Patent:
`
`Sep. 19, 1995
`
`USOOS452239A
`
`[54] METHOD OF REMOVING GATED CLOCKS
`FROM THE CLOCK NETS OF A NETLIST
`FOR TIMING SENSITIVE
`MPLEMENTATION OF THE NETLIST IN A
`HARDWARE EMULATION SYSTEM
`
`[58] Field of Search ................................ 364/578-580,
`364/232.3, 927.81; 371/162, 22.1, 22.2, 23, 27;
`340/825.22, 825.06, 825.88, 825.89, 825.83,
`825.84; 307/465, 468, 219, 303; 357/45;
`395/500; 365/201; 370/13, 14, 17
`
`[75]
`
`Inventors: Wei-Jin Dai, Cupertino; Louis
`Galbiafi, III, Mountain View; Joseph
`Varghese, Sunnyvale; Dam V. Bui,
`Milpitas; Stephen P. Sample,
`Mountain View, all of Calif.
`
`[73] Assignee:
`
`Quickturn Design Systems, Inc.,
`Mountain View, Calif.
`
`[21] Appl. No.-: 844
`
`[22] Filed:
`
`Feb. 26, 1993
`
`Related US. Application Data
`
`[63]
`
`Continuation-impart of Ser. No. 13,025, Jan. 29, 1993,
`abandoned.
`
`Int. Cl.6 ........................ G06G 7/48; G06F 17/00
`[51]
`[52] US. Cl. .................................... 364/578; 364/580;
`371/222
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,306,286 12/1981 Cooke et al.
`........................ 364/200
`
`4,578,761
`3/1986 Gray ................................... 364/481
`4,656,580 4/1987 Hitchcock, Sr. et al.
`.......... 364/200
`5,109,353 4/1992 Sample et al.
`...................... 364/578
`
`Primary Examiner—Ellis B. Ramirez
`Assistant Examiner—Craig Steven Miller
`Attorney, Agent, or Firm—Lyon & Lyon
`
`ABSTRACI
`.
`[57]
`An emulation system and method that reduces or elimi-
`nates the number of timing errors such as hold time
`violations when implementing a netlist description of an
`integrated circuit. The emulation system comprises a
`plurality of reprogrammable logic circuits and a plural-
`ity of reprogrammable interconnect circuits. The netlist
`description is optimized to reduce the number of timing
`violations by removing the occurences of gated clocks
`from the netlist, partitioning the netlist description by
`taking into account the occurence of timing violations
`and ensuring that retain state nets are implemented
`properly.
`
`2 Claims, 78 Drawing Sheets
`
`\
`:4:~~~~~~\
`I
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`
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`
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`247V
`
`CONTROL AND DATA FLOW DIAGRAM
`
`CONFIGIT 1042
`
`CONFIGIT 1042
`
`1
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 1 of 78
`
`5,452,239
`
`
`
`PROENG LOCK
`
`
`
`
` LOGIC ANALYZER PAUERN GENERATOR“
`
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`
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`
`2
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 2 of 78
`
`5,452,239
`
`CONNECTIONS TO EXTERNAL SIGNALS
`
`INTERCONNECT
`CHIP
`
`20A
`
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`
`18A
`
`3
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 3 of 78
`
`5,452,239
`
`
`
`4
`
`

`

`US. Patent
`
`Sep. 19, 1995
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`US. Patent
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`Sep. 19, 1995
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`Sheet 5 of 78
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`5,452,239
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`US. Patent
`
`Sep. 19, 1995
`
`Sheet 6 of 78
`
`5,452,239
`
`I/0 PINS
`
`EXTERNAL
`
`[[2]. 7 MIDPLANE CONNECIING
`
`ONE MUX BOARD CUTS ACROSS 88 EM BOARD SIGNAL PINS
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`US. Patent
`
`Sep. 19, 1995
`
`Sheet 8 of 78
`
`5,452,239
`
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`US. Patent
`
`Sep. 19, 1995
`
`Sheet 9 of 78
`
`5,452,239
`
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`US. Patent
`
`Sep. 19, 1995
`
`Sheet 10 of 78
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`5,452,239
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`US. Patent
`
`Sep. 19, 1995
`
`Sheet 11 of 78
`
`5,452,239
`
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`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 12 of 78
`
`5,452,239
`
`STEP 1:
`pREVEN‘nVE
`MEASURE
`
`‘
`TIMING OPTIMIZATION
`
`104
`
`STEP 2
`INFLUENCING
`
`TIMI
`OP
`
`D NETI
`LST
`
`ZE
`
`CLOCK TREE ANALYSIS
`
`MEASURE
`TIMING DRIVEN
`
`CONFIGURATION
`ENGINE
`
`
`CONFIGURATION
`CONSTRAINTS
`
`INCREMENTAL CONFIGURATION
`
`PHYSICAL
`IMPLEMENTATION
`
`-
`
`STEP 5:
`FIXING
`MEASURE
`
`TIMING ANALYSIS
`
`‘20
`
`COENFSTTTUCTIVE
`MEASURE
`
`STEP 4:
`VERIFICATION
`MEASURE
`
`
`- H4
`
`
`
`AUTO DELAY INSERTION
`
`
`ANY HOLD
`VIOLATIONS
`
`
`
`HOLD VIOLATION
`
`LOCATIONS
`
`NO
`
`EMULATION
`
`SPEED
`
`DONE
`
`TIMING IN CONFIGURATION PROCESS
`
`[12.13
`
`13
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 13 of 78
`
`5,452,239
`
`INITIAL OPEN
`
`I NCREMENTAL
`
`PARSE
`
`100
`
`PARSE
`
`100
`
`LINK 8c EXPAND
`
`102
`
`NETLIST COMPARE
`
`118
`
`CHANGE RECORDS
`
`CHANGE RECORDS
`
`OPTIMIZE
`
`104
`
`LINK & EXPAND
`
`102
`
`CLOCK ANALYSIS
`
`105
`
`OPTIMIZE
`
`104
`
`CHANGE RECORDS
`
`CHANGE RECORDS
`
`PARTITION
`
`108
`
`CLOCK ANALYSIS
`
`106
`
`CHANGE RECORDS
`
`CHANGE RECORDS
`
`SYSTEM ROUTE
`
`1 1 0
`
`PARTITION
`
`108
`
`CHANGE RECORDS
`
`CHIP PLACE & ROUTE
`
`112
`
`SYSTEM ROUTE
`
`110
`
`CHANGE RECORDS
`
`TIMING ANALYSISopt
`
`114
`
`CHIP PLACE & ROUTE
`
`112
`
`DELAY INSERTIONopt
`
`TIMING ANALYSISopt
`
`114
`
`116
`
`CHANGE RECORDS
`
`READY FOR EMULATION
`
`-CONFIGURATION CONTROL FLOW
`
`[122.11
`
`14
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 14 of 7s
`
`5,452,239
`
`USER
`
`CAE DB
`
`NETUST OR
`
`.
`
`100
`
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`
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`
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`
`' 124
`
`102
`
`CREATE - 122
`
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`
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`
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`
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`
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`
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`
`108
`
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`
`125
`
`ANNOTATE
`
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`CREATE -
`114
`TIMING ANALYSISopt’
`
`CHIP
`DB
`
`128
`
`ANNOTATE
`
`CONHGURAWON DAJABASEINTERACUONS
`
`[12.15
`
`15
`
`15
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 15 of 78
`
`5,452,239
`
`F’§Y§IEII"T
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`16
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 16 of 78
`
`5,452,239
`
`
`
`SIMPLE CLOCK TREE
`
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`
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`
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`
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`
`[2.17
`
`17
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 17 of 73
`
`5,452,239
`
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`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 18 of 78
`
`5,452,239
`
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`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 19 of 78
`
`5,452,239
`
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`
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`
`20
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 20 of 78
`
`5,452,239
`
`LOW SKEW CLOCK SPLITTING
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`

`

`US. Patent
`
`Sep.19,1995
`
`Sheet 21 of 78
`
`5,452,239
`
`WIRE AND GENERATION
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`
`(L
`
`
`
`[12.1%
`
`BIDIRECTIONAL UMBILICAL (MULTIPLE DRIVERS)
`
`(LOADS)
`
`(LOADS)
`
`
`
`
`
`22
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 22 of 78
`
`5,452,239
`
`
`
`CLOCK DRIVER CIRCUITRY
`
`
`
`
`
`ENTERPRBE
`
`
`
`
`TA COMPUTE
`QBm
`
`
`
`
`PROCESS -l PROCESS
`U' PROCESS
`SERVER
`REC/FEE
`SERVER
`
`
`
`
`
`
`RPC HL/
`PIPE/FILE
`E
`
`
`
`
`MOTIVE
`TIMING ALNALYZER
`
`
`PROCESS
`
`
`ACROSS NETWORKED HEIEROGENOUS
`WORKSTATIONS
`'
`
`TIMING ANALYSIS SUB—SYSTEM PROCESS ARCHITECTURE
`
`[122. 21
`
`23
`
`23
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 23 of 78
`
`5,452,239
`
`
`
`<DES|GN>.QTD
`
`
`
`TIMING FILE FOR
`THE DESIGN
`
`
`TIMING FILE FOR
`MNG Fl E F R
`PARTITION 1
`F’IARITITIONLN O
`O — DENOTES DIRECTORY
`Cl — DENOTES FILES
`
`THE FILE DIRECTORY STRUCTURE FOR THE TIMING SUBSYSTEM
`
`[12. 22
`
`INTERMEDIATE
`LEVEL
`
`TOP LEVEL
`
`
`
`INTERMEDIATE
`LEVEL
`
`
`
`LEAF LEVEL
`
`PHYSICAL HIERARCHY
`
`[12. 23A
`
`24
`
`24
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 24 of 78
`
`5,452,239
`
`FUNCTION GENERATOR
`
`APR DELAY BACK ANNOTATION
`
`[E 238
`
`INST_1
`
`|NST_2
`
`
`
`[123. 21
`
`ON—CHIP ROUTINE DELAY BACK ANNOTATION
`
`
`
`@ - ROUTING DELAYS IN THE PHYSICAL IMPLEMENTATION. [12125
`
`MISSING RE—CONVERGENCE POINT EXAMPLE
`
`25
`
`25
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 25 of 78
`
`$452,239
`
`QBIC SERVER (TIMING ANALYSIS)
`
`TA COMPUTE SERVER
`
`TIMING ANALYSIS
`PARTITION
`
`INITTATE SPLATTER RUN
`
`BROADCASTLNG TA SERVICE
`NEEDED MESSAGE
`
`
`
`PROCESS TA SERVER’S-
`
`
`REQUESTS .HALT OR
`
`DONE?
`
`YES
`
`PROCESSING TA RESULTS
`
`CONTROL FLOW-TIMING ANALYSIS
`
`
` TA
`
`COMPUTE
`SERVER
`
`
`
`
` TA
`
`COMPUTE
`SERVER
`
`
`
`
`
`TA
`
`COMPUTE
`SERVER
`
`
`
`[12. 2(5
`
`26
`
`26
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 26 of 78
`
`5,452,239
`
`EaazooE
`
`
`
`mm>mmmmSnEooE
`
`Ezmm2mg
`
`
`
` mm>xmm 550mmxmfioz_>_m_om_w_ a_mz<z<@235
`
`kmNW
`
`
`
`
`
`x030magma;
`
`moomdsozx
`
` Jomhzoo MES:ohmSmZmgzmamm mSnE.#2;me mzoEzzmo
`
`
`
`hmmzcmmxmfiEI30.:
`
`
`
`
`
`m¢<mmmz5<_._oz:m<oo<omm
`
`
`
`mafim5<I2x351
`
`
`
`m¢<mmm2mzoocz:m<oo<omm
`
`
`
`mEEmmzoozmzbm
`
`295%;me2Bo
`
`
`
`5:52ZOEEE.zm_o
`
`27
`
`
`
`
`
`EMT—m2:mxmfiwtmzmmaze
`
`27
`
`
`
`
`
`
`
`
`
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 27 of 78
`
`5,452,239
`
`QBIC SERVER
`(TIMING ANALYSIS)
`
`‘
`
`
`
`QBIC SERVER
`PROCESS
`
`
`TA COMPUTE SERVER
`
`SEND TA TASK REQUEST
`
`RECIEVE TA TASK REQUEST
`RECIEVE TA DATA
`
`YES W
`
`<W>
`
`NO
`
`NO
`
`GENERATE MOTIVE INPUT FILES
`
`
`
`
`
`
`
`COMMANDS
`ESTABLISH TO/FROM PIPES- MOTIVE PROCESS
`
`INVOKE MOTIVE PROCESS
`
`INITIALIZE MOTIVE
`
`RETURN CODE
`
`CAL. SETUP/HOLD MARGINS
`
`
`
`
` CRITICAL
`NO
`PATH REQUESTED
`
`
`
`CAL. CRITICAL PATHS
`
`
` CLOCK
`NO
`SPEED REQUESTED
`
`
`
`
`TERMINATING MOTIVE PROC.
`
`CAL. CLOCK SPEED
`
`CONTROL FLOW — TIMING ANALYSIS ON A PARTITION
`
`28
`
`E7 N03
`
`28
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 28 of 78
`
`5,452,239
`
`mm.NNN
`
`
`
` Emmavm;z_om<_2QDEm
`
`Hmm._._<2mE0
`
`
`
`25%:QDEm
`
`
`
`25%.:QDEm
`
`OA
`
`
`
`x0040mmfimoz
`
`Swim
`
`
`
`x0040538m
`
`ommmm
`
`29
`
`MT:20mo<EnSEm
`
`
`
`mE/E.ZEmo
`
`mm<ovie;
`
`
`
`.mzo:.<y_:o._<ooHEmx0040520Hzmozmmmomz_om<§135m
`
`
`
`
`
`29
`
`
`
`
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 29 of 78
`
`5,452,239
`
`zofiésoizooHE;
`
`20:50530:
`
`ozanEozEs
`
`SmmmeEzm
`
`
`
`m><._m_oEmmz.
`
`“292N355
`
`060..
`
`295mm;
`
`Ede
`
`5:
`
`zofimmmz.
`
`Eda
`
`m3:
`
`EHEEKOL
`
`
`8.3So:98:50;
`
`
`mmoz_ago:
`
`m05<Exm
`
`Saw2238
`
`
`
`205mmommsozzoo
`
`95%$8\2,
`
`épzmfita\;
`
`QHEm
`
`m_m>._<z<
`
`02:2:
`
`03
`
`
`
`Sm..Nq
`
`
`
`5:902zQEmmz.Edam5“.030.:MT:
`
`30
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 30 of 78
`
`5,452,239
`
`DE$GN ROOT
` DE$GN
`
`PREPROCESSOR
`
`
`
`MODULE
`MODULE
`
`PREPROCESSOR
`PREPROCESSOR
`
`
`
`
` SOFT
`
`MODULE
`
`
`--F ___________ T__-_
`ICONTROL
`
`
`DEflGN
`
`UNKER
`
` HARD MODULE
`
`DUMP &
`
`
`
`
`HNAL
`LCAs &
`
`
`RESULT
`MUXes
`
`TOP—LEVEL ARCHHECTURE OF MODULE CONHGURAHON
`
`[12.31
`
`31
`
`31
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 31 of 78
`
`5,452,239
`
`Ul WITH CALLTNG BACK
`
`
`I COMMUNICATION
`THE MODUIAR QB SERVER
`: CHANNEL
`
`
`CONFIGURATION CONTROLLER
`
`MODULE PREPROCESSOR MODULE PREPROCESSOR
`
`
`
`
`
`
`MODULE P&R
`
`MODULE P&R
`
`THE PROCESS STRUCTURE OF MODULE CONFIGURATION
`
`[12. 6’2
`
`32
`
`32
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 32 of 78
`
`5,452,239
`
`A
`E1
`
`F
`
`E2
`
`'
`
`52
`
`50
`
`.
`
`A
`E1
`
`F
`E2
`
`USER’S TRl—STATE NET
`
`SYSTEM IMPLEMENTATION
`
`
`
`[12. 3’3
`
`TARGET SYSTEM
`
`A .
`E1
`
`.
`
`;
`
`TARGET SYSTEM
`OR
`
`COMPONENT ADAPTOR E;
`
`A
`E1
`
`F
`
`E2
`
`,
`
`>
`
`OR
`COMPONENT ADAPTOR
`
`
`
`USER'S TRT-STATE
`
`SYSTEM IMPLEMENTATION
`
`
`
`IE. 6’1
`
`33
`
`33
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 33 of 78
`
`5,452,239
`
`IMPLEMENTATION
`SYSTEM
`
`[12.35
`
`TRl—STATE
`USER’S.
`
`34
`
`34
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 34 of 78
`
`5,452,239
`
`mmmEmmEzm
`
`Buzzoommfiz
`
`5802
`
`_mmEmmEzm
`
`
`
` _______.llllll.__|lllll|_mZOEEE_zoEE/E
`
`Gm.NNN
`
`
`
`zoEfizmzufié259mH.553:
`
`EfimiEmkmm:
`
`35
`
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 35 of 78
`
`5,452,239
`
`NmmEnEmfizM
`
`#8228152 _,mmEmmEzm
`
`“.3390:
`
`
`
`NZOEEE._29:52;
`
`aaeVA<
`
`Em
`
`36
`
`
`
`km..Nq
`
`zo:<_.zm2m._m2_355WEED:
`
`
`
`HEMLE.mkwm:
`
`36
`
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 36 of 78
`
`5,452,239
`
`HARDWARE UNDER TIMING ANALYSIS
`
`DATA INPUTS
`
`DATA OUTPUTS
`
`SYSTEM
`
`DATA IOPUTS
`
`TARGET
`
`CONFIGURATION TECHNOLOGY MAPPING
`
`DATA INPUTS
`
`QUICKTURN'S
`EMULATION
`MODULE
`
`DATA IOPUTS
`
`INMODE-LEDBY 0—OUT
`.OMPONENT
`
`ADAPTOR
`
`DATA OUTPUTS
`
`
`
`—
`
`TARGET
`
`SYSTEM
`
`ICOMPONENTk
`'ADAPTOR
`
`LOGIC
`ANALYZER
`
`EXTERNAL CONNECTIONS AND CONSIDERATIONS IN TIMING ANALYSIS
`
`[12. 6’8
`
`37
`
`37
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 37 of 78
`
`5,452,239
`
`
`
`
`
`<QN..E20.25835:5:52
`
`29%.onuse8%;25650
`
`5:52053.
`85:50.2228
`
`
`
`,%\WW/U2220amum:
`
`55200252.
`
`>53
`
`2Em>m
`
`Esozummofim
`
`259m
`
`Ezomummofim
`
`n=Io
`
`BEEEO
`
`
`
`EN>._<2<02.2:
`
`mama/‘2m2<2
`
`5352.2291;
`
`m><._m_oHEB
`
`n=Io
`
`252200252.
`
`avg/Ema
`
`38
`
`
`
`mEonEzown—mban—ZHZEEOQ”Em:
`
`
`
`
`
`38
`
`
`
`
`
`
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 38 of 78
`
`5,452,239
`
`TIMING ANALYSIS DATA FLOW
`
`% SPECIFICATIONS
`
`EXTERNAL - USER
`
`DESIGN DATA
`
`KNOWLEDGE
`
`
`DESIGN
`
`TOPOLOGY
`
`ANALYZER
`
`
` KNOWLEDGE INPUTS:
`DESIGN INFO:
`
`- NET EXCLUSIONS
`— NETLIST
`
`
`— NET GROUPINGS
`— TIMING MODELS
`
`
`-— PATH EXCLUSIONS
`- CLOCK PATH LOGIC
`
`
`- CLOCK DEFENITIONS
`- MOTIVE ENV.
`
`
`SEITINGS
`I/O DATA TIMING
`
`
`
`HIERARCHY
`
`MANAGER
`
`TA PARTITIONS
`
`CLOCK TREE
`
`ANALYSIS
`
`.
`
`
`
`
`
`
`
`
` MOTIVE
`TIMING
`
`
`ANALYZER
`
`
`
`
`
`SETUP MARGINS
`
`HOLD MARGINS
`
`LIMITED PATHS
`
`I
`
`T
`
`CRITICAL PA HS
`
`CLOCK SPEED
`CALCULATOR
`
`DERIAATIC
`INSERTION
`
`PATH DELAY
`
`QUERY RESULTS
`
`DATA SYNC
`T
`PULSE WID H
`
`EMULATION
`SPEED
`
`FIXED HOLD
`VIOLATIONS
`
`[12. 398
`
`39
`
`39
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 39 of 78
`
`5,452,239
`
`
`
`EMULATION
`SYSTEM
`
`
`
`EMULATION
`MODULE
`
`
`
`
`
`
`SYSTEM INTERCONNECT TIMING MODELLING
`
`[12. 10
`
`SYSTEM
`
`SYSTEM
`
`POD TIMING MODELLING
`
`ADAPTER
`
`COMPONENT
`
`COMPONENT ADAPTER TIMING MODELLING
`
`[12. 12
`
`4O
`
`40
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 40 of 78
`
`5,452,239
`
`_|
`
`IIIII|IIIl
`
`[EMBEAfiSN‘EA‘RfiwA§E‘—"1 DATA PATH DELAY
`
`FCDITEDNETITAEARTER__—_
`
`..I
`
`CASE 1
`
`-— STORAGE—TO—STORAGE FROM EMULATION HARDWARE TO COMPONENT ADAPTER
`
`[12.13
`
`r- ——————————————— '1
`EMULATION HARDWARE
`
`r- ——————————————— '1
`
`I IIIIIlI
`
`CLOCK
`
`
` EXTERNAL
`
`
`TIMING
`SPEC
`
`
`
`HIERARCHY 0F EXTERNAL TIMING INFORMATION
`
`[12.45
`
`41
`
`41
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 41 of 78
`
`5,452,239
`
`r-——BUT_PLTT§“'
`r ________ 1
`
`EMULATION
`MODULE
`
`
`
`/\
`
` EMULATED
`DESIGN
`
`CLK_|N
`
`
`WHERE THE DELAYS FOR:
`BUFFER: MIN 3N8, MAX 6N8
`AND GATE: MIN 5N8, MAX 7N8
`FF(CLK->Q): MIN 2N8, MAX 5N8
`
`AN EXAMPLE OF EXTERNAL INPUT SIGNALS
`
`[12. 47
`
`42
`
`42
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 42 of 78
`
`5,452,239
`
`
` OUT
`EMULATED
`
`DESIGN
`
`CLK_IN
`
`
`
`CONSTRAINING
`COMPONENT
`FLIP—FLOP
`SETUP = IONS
`HOLD = 5NS
`TRIGGER = RISING
`
`FRAME OF REFERENCE
`
`PERIOD =. IOONS
`
`
`S/H CONSTRAINTS ________.I;;'Q____________________.__;I;I_______
`IHOLD FOR
`SETUP FOR
`I HOLD FOR
`AT TnHE" HYPOTHEHCAL SETUP FOR
`PIN D
`THE pREwous: THE CURRENT
`THE CURRENT {THE NEXT
`CYCLE(TONS)
`I CYCLE(5NS)
`CYCLE(TONS)
`:CYCLE(5NS)
`I
`I
`
`S/H CONSTRAINTS
`
`TRANHSLATED TO OUTPUT I:I] I
`PIN x"
`SETUP = 3ONS
`HOLD = 5NS
`
`I
`
`I
`
`I::I]_I
`SETUP = 3ONS
`HOLD = 5NS
`
`_
`
`CALCULATING EXTERNAL SETUP AND HOLD TIME
`
`[V 18
`
`lg.
`
`
`
`NEI' EXCLUSION EXAMPLES - PATH ELIMINATION
`
`[12.19
`
`43
`
`43
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 43 of 78
`
`5,452,239
`
`
`
`NET EXCLUSION EXAMPLE - FEEDBACK LOOP BREAKING
`
`[12.50
`
`
`
`>I..-
`
`A NET GROUPING EXAMPLE
`
`[12.51
`
`44
`
`44
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 44 of 78
`
`5,452,239
`
` CLOCK
`
`ICYCLE 0
`51
`
`I CYCLE 1
`E3
`
`CLOCK.
`E4:
`521
`DELAYED,CLOCK ,
`DATA $2:
`
`ICYCLE 2
`
`T=ONS
`
`T=1000NS
`
`ZERO CYCLE SETUP PATH
`
`[12. 52
`
`DELAYED_CLOCK
`
` CLOCK
`DELAYED_CLOCK1 ; E2
`; E4-
`E6
`
`ICYCLE O
`E1
`
`ICYCLE 1
`E3
`
`1
`
`ICYCLE 2
`E5
`
`I
`
`DATA
`
`T=sz
`
`I
`T=1ob0Ns
`
`I
`T=2000
`
`MULTI—CYCLE SETUP PATH
`
`[12.53
`
`45
`
`45
`
`

`

`US. Patent
`
`Sep. 19,1995
`
`Sheet 45 of 78
`
`5,452,239
`
`A CIRCUIT WITH A GATED LOCK
`
`
`
`FLIPFLOP WITH CLOCK ENABLE
`
`
`
`GATED-CLOCK OPTIMIZATION
`
`46
`
`46
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 46 of 78
`
`5,452,239
`
`A. ORIGINAL CIRCUIT
`
`
`
`CLOCK
`
`B. TRANSFORMED CIRCUIT
`
`
`
`CLOCK
`
`ORIGINAL CIRCUIT
`CK
`__.I
`I——————
`112’155'3 o::><:s‘::
`
`TRANSFORMED CIRCUIT
`
`[(27.1.55E 0m
`
`EXAMPLE OF CLOCK-GATING LOGIC
`
`47
`
`47
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 47 of 78
`
`5,452,239
`
`A. ORIGINAL CIRCUIT
`
` CLOCK
`
`B. TRANSFORMED CIRCUIT (NON-EQUIVALENT)
`
`
`
`CLOCK
`
`[(2.5%)
`
`_I—_‘L_____
`§A
`
`ORIGINAL CIRCUIT:
`
`[12,“. 5m 4 LI I———_
`
`CK
`
`TRANSFORMED CIRCUIT;
`
`[12”;ng o:><:::::
`
`EXAMPLE OF CLOCK—GENERATION LOGIC
`
`48
`
`48
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 48 of 78
`
`5,452,239
`
`A. ORIGINAL CIRCUIT
`
`[12.57A
`
`B. NOMALIZED CIRCUIT
`
`[2" 57B
`
`QI...QN
`
`QI ...QN CLOCK
`
`QI...QN
`
`C. TRANSFORMED CIRCUIT
`
`A1...NM
`
`QI ...QN
`
`[2]. 57C Q‘l...QN
`
`QI ...QN
`
`CLOCK
`
`GATED CLOCK TRANSFORMATION
`
`49
`
`49
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 49 of 78
`
`5,452,239
`
`ENZ
`
`ENS
`
`EN4
`
`ENS
`
`CLOCK
`
`DATA
`
`EN1
`
`EN2
`
`
`ENS
`
`[12: $0 EN3
`
`EN4
`
`CLOCK
`
`5O
`
`50
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 50 of 78
`
`5,452,239
`
`DETERMINE SET S
`
`OF CLOCK SOURCES
`
`
`
`
`Ci = FIRST CLOCK
`
`SOURCE IN S
`
`
`
`CI = NEXT CLOCK
`
`SOURCE IN S
`
`
`
`
`FOR ALL FLIPFLOPS Fk IN
`INITIALIZE FLAG Fk
`NEILIST,
`
`
`(E0, 1) = TRUE
`
`
`
`
`
`FOR EACH FLIPFLOP WHICH
`CANNOT BE TRANSFORMED WITH
`
`
`Ci, SET FLAG Fk(EQ, I) = FALSE
`
`
`
`
`
`CLOCKS ?
`
` MORE
`
`[12. (ZIA
`
`51
`
`51
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 51 of 78
`
`5,452,239
`
`STARTING FROM ALL USER—DESIGNATED CLOCK
`NETS IN U, TRACE FORWARD THROUGH
`COMBINATIONAL LOGIC, MARKING ALL
`FLIPFLOP AND LATCH CLOCK INPUTS REACHED.
`
`
`
`
`
` STARTING FROM ALL FLIPFLOP AND LATCH CLOCK
`INPUTS NOT MARKED IN PREVIOUS STEP, TRACE
`
`BACKWARD THROUGH COMBINATIONAL LOGIC,
`MARKING FLIPFLOP AND LATCH OUTPUTS REACHED.
`
`
`
`
`
`
`
`
`THE SET D OF NETS MARKED IN THIS STEP ARE
`
`THE DIVIDED CLOCKS.
`
`
`
`
`
`STARTING FROM ALL NETS IN SETS U OR D, TRACE
`FORWARD THROUGH COMBINATIONAL LOGIC,
`MARKING ALL NETS REACHED.
`DURING THIS
`
`PROCESS ACCUMULATE THE SET C OF COMBINED
`
`CLOCKS; THOSE NETS WHOSE DRIVER BLOCKS
`HAVE TWO DIFFERENT INPUTS REACHABLE FROM
`
`
`
`
`
`
`
`NETS IN U OR D.
`
`
`
`COMPUTE THE SETS OF CLOCK SOURCES AS
`
`THE UNION OF SETS U, D, AND C.
`
`[12. $13
`
`52
`
`52
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 52 of 78
`
`5,452,239
`
`CLOCK STATE = STATE ‘I
`
`INITIALIZE ALL NETS IN THE
`NETLIST TO STATE P
`
`
`
`
`
`
`
`ASSIGN CLOCK STATE TO
`CLOCK SOURCE Ci
`
`PROPAGATE VALUES
`
`
`
`CLOCK STATE = STATE 0
`
`
`
`
`
`
`
`
`
`IN THIS STATE, THE
`DETERMINE,
`FLIPFLOPS WHOSE CLOCK INPUTS CAN
`BE REACHED VIA PATHS EITHER FROM
`PRIMARY INPUTS NOT GOING THROUGH
`Ci, OR VIA PATHS WHICH GO THROUGH
`FLIPFLOPS BETWEEN Ci AND THE GIVEN
`CLOCK PIN.
`ASSIGN STATE C TO SUCH
`
`
`
`
`
`
`
`
`FLIPFLOP CLOCK INPUTS.
`
`
`
`
`
`
`
`
`FOR EACH FLIPFLOP Fk WITH STATE C
`ON ITS CLOCK INPUT, SET
`Fk(EQ, I) = FALSE
`
`
`
`
`
`
`STATE 0
`
`[121(ch
`
`53
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 53 of 78
`
`5,452,239
`
` FOR EACH PRIMARY INPUT NET Im
`
`WHICH IS A DIFFERENT NET FROM
`CI, ASSIGN STATE C TO Im
`
`
`
`
`
`FOR EACH FLIPFLOP Fk WHOSE
`
`CLOCK INPUT STATE IS EITHER STATE
`
`
`
`
`
`C OR THE STATE ENTERED WHEN Fk
`IS TRIGGERED, ASSIGN STATE C TO
`THE 0 OUTPUT OF Fk
`
`
`
`
`PROPAGATE VALUES
`
`STABLE
`
`
`
`CONDITION
`
`REACHED?
`
`
`
`[1221510
`
`54
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 54 of 78
`
`5,452,239
`
` FOR EACH PRIMARY INPUT NET Im
`
`
`WHICH IS A DIFFERENT NET FROM
`
`
`
`Ci, ASSIGN STATE C TO Irn
`
`
`
`
`
`
`
`FOR EACH FLIPFLOP Fk WHOSE
`CLOCK INPUT STATE IS EITHER STATE
`
`
`
`
`
`
`
`C OR THE STATE ENTERED WHEN Fk
`IS TRIGGERED, ASSIGN STATE C TO
`THE Q OUTPUT OF Fk
`
`
`
`
`
`
`
`
`
`FOR EACH LATCH Lk WHOSE GATE
`
`INPUT STATE IS EITHER STATE C OR
`
`THE STATE IN WHICH Lk lS
`
`TRANSPARENT, ASSIGN STATE C TO
`THE Q OUTPUT OF Lk
`
`PROPAGATE VALUES
`
`
`
`
`
`
`CONDITION
`
`STABLE
`
`REACHED?
`
`[12. QIE
`
`55
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 55 of 78
`
`5,452,239
`
`THE ORIGINAL DESIGN:
`
`CLK
`
`SI
`
`SN
`
`
`
`[12. (52A
`
`THE TRANSFORMED DESIGN:
`
`
`
`DIN
`
`QOUT
`
`
`
`51
`
`SN
`
`CLK '
`
`TRANSFERRING CLOCK PATH LOGIC TO CLOCK ENABLE
`
`[12. $28
`
`56
`
`56
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 56 of 78
`
`5,452,239
`
`
`
`D CLOCK GAHNGIMPLEMENTAHON:
`
`ENABLE
`
`
`
`CLOCK
`
`CLOCK ENABLE TRANSFORMAHON:
`
`
`
`ENABLE
`
`
`CLOCK MENABLE
`
`CLOCK
`
`D
`
`UNDER CLOCK GAflNG
`
`D_CLOCK
`
`Q
`
`A
`
`A
`
`UNDER CLOCK ENABLE:
`
`“KC
`
`‘
`
`|
`
`><
`
`B
`
`Q
`
`A
`
`><
`
`B
`
`FUNCTIONALLY EQUIVALENT TRANSFORMATION EXAMPLE
`
`[122. Q?
`
`57
`
`57
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 57 of 78
`
`5,452,239
`
`CLOCK GATING IMPLEMENTATION
`
`ENABLE
`
`CLOCK
`
`CLOCK ENABLE TRANSFORMATION:
`ENABLE
`
`
`
`
`CLOCK
`
`CLOCK
`
`ENABLE
`
`
`
`
`D
`
`A
`
`{IIIEIIIIVCIIIIIIIIII
`
`D
`
`UNDER CLOCK GATING
`
`D_CLOCK
`
`I
`
`I
`
`I
`
`I
`
`Q
`
`A
`
`‘1IEIIID'
`
`C
`
`UNDER CLOCK CAONC
`
`Q
`
`A
`
`:3:
`
`C
`
`FUNCTIONALLY NON—EQUIVALENT TRANSFORMATION EXAMPLE
`
`[12. $1
`
`58
`
`58
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 58 of 78
`
`5,452,239
`
`
`
`CLK 1
`
`CLK 2
`
`ANDED MULTIPLE CLOCKS
`
`[V 5
`lfi—L. Q
`
`CLK1
`
`CLK2
`
`MODE
`
`MUXED MULTIPLE CLOCKS
`
`[12/- fig
`
`CLOCK
`
` D_CLOCK
`SIMPLE CASE OF USING DATA AS CLOCK [’ g7
`
`14.
`
`59
`
`59
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 59 of 78
`
`5,452,239
`
`
`
`
`D_CLOCK
`
`COMBINATIONAL
`LOGIC F
`
`CLOCK
`
`GENERAL CASE OF USING DATA AS CLOCK
`
`
`
`
`D_CLOCK
`
`COMBINATIONAL
`LOGIC F
`
`CLOCK
`
`A GENERAL FORM OF CLOCK PATH
`
`60
`
`[IE—4’. g9
`
`60
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 60'of 7s
`
`' 5,452,239
`
`THE ORIGINAL DESIGN:
`
`
`
`ENI
`
`ENZ
`
`CLOCK
`
`,THE TRANSFORMED DESIGN:
`
`
`
`EN‘I
`
`EN2
`
`1
`
`CLOCK ——-
`
`PERFORMING LOGIC TRANSFORMATION
`
`[12. ’70
`
`61
`
`61
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 61 of 78
`
`5,452,239
`
`
`
`ENABLE
`
`
`
`
`D_CLOCK
`
`EXAMPLE 1 OF SYMBOLIC SIMULATION
`
`[12. 71
`
`
`
`ENABLE
`
`
`
`
`D_CLOCK
`
`EXAMPLE 2 OF SYMBOLIC SIMULATION
`
`[122.72
`
`62
`
`62
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 62 of 78
`
`5,452,239
`
`USER SPECIFICATION
`
`\
`
`{’EXIERNAL‘I_
`\ CLOCKS /I ‘\
`fi~.__—/
`
`II
`
`
`
`.—
`
`I
`\ //——“\
`\( Dthfg Ir
`\
`CL C
`I
`\\ _/
`\\ ‘T
`I
`I
`\\
`
`\\
`
`\
`
`\
`
`\
`
`\
`
`\
`\
`\ \
`\\ \
`\\\\
`\\
`
`,_._—.——\
`
`/
`
`\
`ALL CLOCK r’
`SOURCES
`I
`INCLUDING
`I
`COMBINED
`I
`CLOCKS
`/ \
`___./
`
`,———-’
`
`“_
`
`\\
`,1“\
`x’
`CLOCKED \
`‘\\BLOCKS ,I
`771
`I
`I
`,
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`,
`I
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`:: ~~~~~~~~
`\
`_3‘\
`x’
`\
`{LOCK WEI
`777T
`I___J_,,//
`/
`—“"I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`/
`I
`I
`I
`I
`I//
`/,i
`-’
`I
`__-__'_“
`I
`I,
`I
`,
`/
`__/__-”
`_ I
`/
`/
`
`,’
`___
`/
`//’—
`\I
`FUNCT.
`\‘\\l
`|
`//\
`EQUIV.
`GATED CLK I
`REMOVE
`I
`CADIDATES ,
`/
`_,___
`’
`
`\
`
`/
`
`/
`
`///
`
`/
`///
`,,,J
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`,’
`
`/
`
`/
`
`63
`
`63
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 63 of 78
`
`5,452,239
`
`
`
`[12.71
`
`DIVIDED_CLOCK
`
`
`
`
`CLOCK
`
`A DIVIDED CLOCK EXAMPLE
`
`[12. ’75
`
`CASE 1: GENERATING NEW CLOCKS
`
`
`
`
`CLK_I
`
`CLK__2
`
`COMBINED CLK
`
`
`
`CASE 2: SELECTING CLOCKS
`
`COMBINED CLK
`
`
`
`
`CLK__1
`
`CLK_2
`
`
`
`SELECT
`
`EXAMPLE OF COMBINED CLOCKS
`
`64
`
`64
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 64 of 78
`
`5,452,239
`
`THE ORIGINAL DESIGN:
`
` EN‘I
`
`ENZ
`
`CLOCK
`
`THE TRANSFORMED DESIGN:
`
`
`
`PERFORMING LOGIC TRANSFORMATION
`
`fig. 7g
`
`65
`
`65
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`‘ Sheet 65 of 78
`
`5,452,239
`
`BEFORE GATED CLOCK REMOVE:
`
`AFTER GATED CLOCK REMOVE AND
`CLOCK NET ADJUSTMENTS
`
`CLOCK
`
` 82
`
`
`AN EXAMPLE OF CLOCK NET ADJUSTMENTS
`
`[12. 77
`
`66
`
`66
`
`

`

`
`
`67
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 67 of 78
`
`5,452,239
`
`
`
`
`
`
`OPTIMIZER
`
`OPTIMIZED
`
`NEILIST
`
`CLUSTER STEP 1:
`
`GATES TO CLUSTERS
`
`CLUSTER STEP 2:
`
`CLUSTERS TO CHIPS
`
`
`
`
`
`CLUSTER STEP 3:
`
`CHIPS TO BOARDS
`
`IMPROVEMENT
`
`ITERATIONS
`
`
`
`
`
`
`BOARD IMPROVEMENTS
`
`SYSTEM IMPROVEMENTS
`
`68
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 68 of 78
`
`5,452,239
`
`OPTIMIZER
`
`
`
`PATH TIMING
`ESTIMATO R/CALCULATOR
`
` _
`
`PATH CONSTRAINTS
`GENERATOR
`
`TIMING
`CONSTRAINTS
`
`OPTIMIZED
`
`NETLIST
`GATES TO CLUSTERS
`
`CLUSTER STEP 1:
`CONE PARTITIONING
`AND PATH CLUSTERING
`
`CLUSTER STEP 2:
`CLUSTERS TO CHIPS
`
`CLUSTER STEP 3:
`CHIPS TO BOARDS
`
`IMPROVEMENT
`ITERATIONS
`
`
`
`
`BOARD IMPROVEMENTS
`
`
`
`SYSTEM IMPROVEMENTS
`
`
`
`69
`
`69
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 69 of 78
`
`5,452,239
`
` l
`
`i 1
`
`” CONE OF INFLUENCE FOR A FLIP—FLOP INPUT
`
`[V 81
`14.
`
`C
`
`0 o 0
`BEFORE PATH-BASED CLUSTERING: PATH LENGTH = 3
`
`[12.82 STEPS IN FIRST LEVEL CLUSTERING
`
`7O
`
`70
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 70 of 78
`
`5,452,239
`
`REGISTER READ WRITE CYCLE
`
`PTCKW
`PSYNC—
`I._|
`
`PA[O:15]
`
`PTD'
`
`PTDO
`
`VAL”)
`
`TNPUT DATA ananaana
`
`OUTPUT DATA anannana
`
`pms W:>_C
`
`[12.83
`
`LCA PROGRAMZ READBACK
`
`LI LEW
`pm
`PSYNC- —l__1
`
`PA[O:15]
`VAL'D
`
`—————/
`INPUT DATA
`————/
`OUTPUT DATA
`
`PTD'
`
`PTDO
`
`453------
`
`(53------
`
`[12.81
`
`UUUl—ll—IL—JUUUL—ll
`
`VAL'D
`
`JTAG FORMAT
`
`PTCK
`
`PA[O:15]
`
`PTD'
`
`INPUT DATA
`
`PTDO
`
`OUTPUT DATA
`
`[12,“. 85
`
`71
`
`71
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 71 of 78
`
`5,452,239
`
`
`
`
`
`.LCA AND .SCP FILES, AND
`.BIT AND .PIP FOR INCR.
`PARENT
`
`APRERV
`
`
`QBS PROCESS
`
`
`PROCESS
`
`
`QBC and SPL
`
`
`
`RPM
`PROCESS
`
`
`
` CBLKs, PINS, AND
`CONFIG RECORDS
`
`
`L________~_L______~,____J
`
`
`.BIT AND .PIP FILES, AND
`.LCA AND .SCP FOR DEBUG ONLY
`.RPT FILE, AND
`CHIP LEVEL DELAY FILE.
`
`1. CLB DELAYS ARE
`GENERATED BY
`M20 FROM CBLKS
`
`2. ROUTING DELAYS ARE
`INSTALLED IN THE
`DELAY.DEFAULT FILE BY
`A CALL TO M20.
`
`CLBSMDL : CONTAINS CLB GENERATED DELAYS
`DELAY.DEFAULT : CONTAINS ROUTING DELAYS.
`
`[128$
`
`72
`
`:— ““““cfigREN‘T“““
`IARCHITECHTURE + SPLATTER
`I CONTROL
`
`NOTES:
`1. CMS AND 03A ARE SEPA—
`RATE SUBSYSTEMS.
`2. CMS OUTPUTS ARE CON—
`
`SUMED BY 03A, BUT STORED
`IN GLOP FOR INCREMENTAL
`TIME.
`3. CBLKS ARE CONSUMED BY
`M20 TO RECONCILE DELAYS
`WITH LOGICAL NETLIST.
`4. CHIP PLACE AND ROUTE
`IS INTEGRAL WITH QBS,
`SERVER. AND QBIC.
`
`I I I
`
`III I
`
`IIIIIII I|
`
`72
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 72 of 78
`
`5,452,239
`
`F.PARENT/MONITOR
`COMM.
`
`D.PARENT/
`SCAVANGER
`
` PARENT
`
`PROCESS
`
`
`
`
`
`
`SCAVANGER
`MONITOR
`E.MONITOR/
`
`PROCESS
`PROCESS
`SCAVANGER
`
`
`
`A.SCAVANGER
`CONTROL &
`
`
`
`
`
`RPM
`PROCESS
`
`
`
`
`BS
`ROCESS
`
`FEEDBACK
`
`
`
` ENGINE
`PROCESS
`
`
`B.SCAVANGER
`
`G.MONITOR/ENGINE
`COMM.
`DISK IO
`
`H.LICENSE MANAGER
`
`COMMUNICATION
`
`C.QBS
`DISK IO
`
`
`
`
`III I I
`
`II
`
`1.NEI'LISTS
`
`2.CONSTRA|NTS
`
`
`3.CHIPDB
`4.DELAYS
`I
`5.IOB swaps
`
`
`
`.1
`
`IIIIIIII| I
`
`IIII II|I|
`
`IARCHITECTURE + SPLATTER
`I CONTROL
`INOTES:
`I1. SEPERATE CPrScR PROCESS
`I
`,CALLED SCAVANGER AT 088
`IHOST.
`I2. NOW’CHIP ENGINE" PRO— I
`ICESS CONTAINS VENDOR
`ISPECIFIC CODE.
`{3. NO CHIP CONFIG DATA
`lSTORED IN THE GLOP.
`I4.
`INTERFACES ARE WELL
`I DEFINED
`
`_I
`
`73
`
`73
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 73 of 78
`
`5,452,239
`
`E1.5 PROCESS, COMMUNICATIONS, CONTROL, AND DATA
`A. SCAVANGER CONTROL AND FEEDBACK TO QBS.
`'
`THE DIRECT COMMUNICATION TO/FROM QBS WITH SCAVANGER WILL BE
`NAMED PIPES.
`THESE CAN BE FOUND AND OPENED BY THE
`
`QBS PROCESS ONCE THE SCAVANGER PROCESS IS RUNNING.
`DIRECT COMMUNICATION WILL BE LIMITED TO 088 HANDING OFF CHIP
`
`NAMES AS THEY BECOME AVAILABLE, OR A CONTROL FILE.
`FEEDBACK. MAYBE THERE SHOULD NOT BE ANY DIRECT FEEDBACK FOR
`SIMPLICITY.
`SCAVANGER CAN WRITE STATUS TO A FILE.
`STATUS
`MAY BE ERRORS,
`I’M—ALIVE, AND CHIP COMPLETION/
`DISCONNECTS
`
`B. SCAVANGER DISK IO.
`
`EXPECTED INPUTS:
`OTHER INPUTS:
`
`OUTPUTS:
`
`NETLIST, CONSTRAINTS, AND POSSIBLY CONTROL
`SIDE FILES TO DEFINE PACKAGE, AND
`ARCHITECTURE, SPEED INFORMATION
`PHYSICAL DATABASE, BACK—ANNOTATION FILE(S) FOR
`DELAYS, CHIP PIN SWAPS.STATUS.
`
`C. 088 DISK IO
`WILL POLL INFORMATION IN THE CHIPS DIRECTORY TO GAIN ADDITIONAL
`STATUS, AND TO EVALUATE RESULTS AS THEY BECOME AVAILABLE (IF
`NECESSARY).
`
`D. PARENT/SCAVANGER COMM.
`LEVERAGE EXISTING SPLATTER COMMUNICATION BETWEEN APRSERV/QBS BY
`MIMICING CODE RIGHT DOWN TO THE ASV AND 03A ENTRY POINTS.
`SCAVANGER WILL ASSUME THE ROLE OF QBS WHILE COMMUNICATING WITH
`THE CH|P SERVERS.
`
`E. MONITOR/SCAVANGER COMM.
`SAME AS D ABOVE.
`
`F. PARENT/MONITOR COMMUNICATION.
`SAME AS D ABOVE.
`LEVERAGE THIS CODE COMPLETELY.
`
`C. MONITOR/ENGINE COMM.
`THE ENGINE PROCESS IS A NEw PROCESS THAT IS EXEC ED BY THE MONITOR
`PROCESS
`IT WILL HANDLE A COMPLETE PLACE AND ROUTE TASK AND THEN
`EXIT (EXIT IS STILL TBD)
`
`H. LICENSE MANAGER CONTROL.
`THE SOLUTION HERE IS TBD.
`
`[12.88
`
`74
`
`74
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 74 of 78
`
`5,452,239
`
`ANOTHER VIEW OF THE DATA
`(FILES) BEING COMMUNICATED.
`
` CHIP
`SPECIFIC
`
`DATA
`
`
`
`
`SCAVANGER:
`
`033, 028
`
`
`
`ICUTPUT
`NETLISTS AND
`-
`CONSTRAINTS
`2.FEEDBACK
`CHIP COMPLETION,
`
`
`
`
`
`QBIC
`DATA
`
`STRUCTURES
`
`
`
`II
`
`I
`
`CHIP SPECIFIC DATA
`I
`I I. ALL CHIP SPECIFIC
`I DATA WILL BE COMMUNICATED I
`I To SCAVANGER VIA FILES.
`I
`I NETLISTS AND CONSTRAINTS
`I
`I ARE CREATED BY
`I
`I QBS(02C).
`I
`I 2. SCAVANGER WILL COMMU— I
`I
`I
`NICATE THE NETLISTS AND
`I
`I
`CONSTRAINTS TO A CP&R
`I
`|
`I
`|
`SERVER.
`I
`I
`3. CP&R SERVERS WILL RE—
`I
`I
`TURN A PHYSICAL DATA—
`I
`I
`I
`I
`BASE, ROUTING AND GATE
`I
`|
`DELAYS, AND IOB SWAPS.
`|
`I
`4. 088 WILL BACK—ANNO—
`I
`I
`I
`I
`TATE DATA AS NECESSARY.
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`DATA
`
`ANY BACK—
`ANNOTATION
`
`I
`|
`
`1
`AND HANDLE
`
` CHIP
`SPECIFIC
`
`
`DATA
`
`
`
` CHIP
`SPECIFIC
`
`
`DATA
`
`
`
`
`
` CHIP
`SPECIFIC
`
`
`DATA
`
`
`
` CHIP
`SPECIFIC
`
`
`
`
`
`75
`
`75
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 75 of 78
`
`5,452,239
`
`NETWORK COMMUNICATIONS (SPLATTER)
`CHIP PLACE AND ROUTE FRAMEWORK (ASV)
`
`VENDOR #1
`TRANSLANON
`
`VENDOR #2
`TRANSLATION
`
`VENDOR #3
`TRANSLATION
`
`VENDOR #N
`TRANSLAHON
`
`VENDOR #N
`CONTROL
`
`(NEOCAD)
`
`VENDOR #1
`CONTROL
`(e.g. PPR)
`
`VENDOR #2
`CONTROL
`(e.g. APR)
`
`VENDOR #3
`CONTROL
`
`
`
`QT
`
`INTERPRET
`CONTROL
`
`CONTROL
`FILE
`
`
`
`VENDOR
`
`VENDOR
`ENGINE
`
`
`
`N ETLI ST
`PROCESS
`
`
`
`
`
`QT PRO
`FORMAT
`
`TRANSLATE
`
`PRIETARY
`
`
`
`N ETLIST
`VENDOR
`
`
`NETLIST
`CONSTRAINT
`
`FORMAT
`
`
`
`
`FILTER
`
`
`
`QT DLY
`DELAYS 8:
` VENDOR DB
`
`
`FORMAT
`
`PIN SWAPS
`
`
`76
`
`76
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 76 of 78
`
`5,452,239
`
`THE VENDOR LIBRARIES AND CUSTOM LI-
`BRARIES WILL DESCRIBE THE FUNCTIONAL
`LEAF LEVEL OF THE CUSTOMER’S TARGET
`TECHNOLOGY.
`THE QT LIBRARY MAPS LOG—
`IC INTO PIECES WHICH CAN BE TREATED IN
`AS TECHNOLOGY INDEPENDENT, AND
`BEARS ATTRIBUTES TO ASSIST IN PACKING.
`
`
`
`
`CUSTOMER
`NEILIST(S)
`
`
` VENDOR
`
`
`LIBRARY
`PARSE &
`LINK
`
`WT
`
`FUNCTIONS
`LIBRARY
`
`LEAF LEVEL FUNCTIONS IN THE
`
`QT LIBRARY WILL BE GENERIC.
`THE QT LEAF LEVEL DOES NOT
`DEPEND ON ANY VENDOR’S
`FUNCIONALITY.
` NET LISTING
`
`& CHIP
`
`SCHEDULING
`
`SYNTHESIS
`
`QT MACRO
`LIBRARY
`
`CHIP P & R
`VENDOR
`ENGINE
`
`CHIP LEVEL
`TIMING
`MODEL
`
`LEAF LEVEL FUNCTIONS IN THE
`
`QT LIBRARY ARE LINKED WITH
`
`PRIMITIVES AND MACROS IN
`THE VENDOR’S MODELING
`LANGUAGE.
`
`1
`
`IN THE QT
`MACROS (NON—PRIMITIVES)
`MACRO LIBRARY NEED TO HAVE A TIMING
`MODEL CREATED THAT DESCRIBES THE
`TIMING BEHAVIOR OF THE MACROS TO
`
`
`
`QT TIMING
`MODELS
`
`TIMING
`ANALYSIS
`(MOTIVE)
`
`ALL TIMING MODELS WHICH
`ARE FIXED IN STRUCTURE ARE
`CONTAINED HERE.
`THESE
`MODELS MAY BE PARAME—
`TERIZED
`
`______________________ 1
`I
`I TECHNOLOGY LIBRARIES AND WHERE THEY ARE CON— I
`'SUMED
`'
`
`77
`
`77
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 77 of 78
`
`5,452,239
`
`C