UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`PARKERVISION, INC.
`
`vs.
`
`INTEL CORPORATION
`
`Plaintiff,
`
`Defendant.
`
`C.A. No. 6:20-cv-00108-ADA
`
`JURY TRIAL DEMANDED
`
`DEFENDANT INTEL CORPORATION’S
`PRELIMINARY INVALIDITY CONTENTIONS
`
`ParkerVision Ex. 2015
`IPR2021-00990
`Page 1 of 137
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`

`

`TABLE OF CONTENTS
`
`Page(s)
`
`INTRODUCTION ................................................................................................................. 1
`I.
`II. RESERVATIONS .................................................................................................................. 2
`III. INVALIDITY BASED ON PRIOR ART ............................................................................ 4
`A.
`Identification of Prior Art References ............................................................................. 4
`B. Anticipation Under 35 U.S.C. § 102 and/or “Single Reference” Obviousness Under
`35 U.S.C. § 103........................................................................................................................... 7
`C. Obviousness Under 35 U.S.C. § 103 ................................................................................. 9
`1. Motivations to Combine............................................................................................... 13
`IV. INVALIDITY BASED ON 35 U.S.C. § 112 ...................................................................... 51
`
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`I.
`
`INTRODUCTION
`
`Pursuant to the Court’s Scheduling Order (D.I. 34), Defendant Intel Corporation (“Intel”)
`
`hereby provides the following Preliminary Invalidity Contentions with respect to U.S. Patent Nos.
`
`6,266,518 (“’518 patent”); 6,580,902 (“’902 patent”); 7,110,444 (“’444 patent”); 7,539,474 (“’474
`
`patent”); 8,588,725 (“’725 patent”); 8,660,513 (“’513 patent”); 9,118,528 (“’528 patent”);
`
`9,246,736 (“’736 patent”) and 9,444,673 (“’673 patent”) (collectively, the “Asserted Patents”),
`
`which Plaintiff ParkerVision Inc. (“ParkerVision”) has asserted against Intel.
`
`Intel has petitioned for Inter Partes Review of claims 1, 3, and 5 of the ’444 patent (Case
`
`IPR2020-01265) and claims 1, 3, 4, 7, and 9-12 of the ’474 patent (Case IPR2020-01302), and
`
`hereby incorporates those petitions, including the declarations supporting those petitions, and any
`
`subsequent proceedings before the U.S. Patent Trial and Appeal Board related to those petitions
`
`herein by reference.
`
`In ParkerVision’s Preliminary Infringement Contentions served on June 26, 2020 and
`
`Amended Disclosure of Preliminary Contentions served on August 27, 2020, ParkerVision
`
`provided infringement contentions for the forty-nine claims identified below (the “Asserted
`
`Claims”):
`
`Patent
`6,266,518
`6,580,902
`7,110,444
`7,539,474
`8,588,725
`8,660,513
`9,118,528
`9,246,736
`9,444,673
`
`Asserted Claims
`50, 67
`1, 2, 4, 5
`2, 3, 4
`1, 6, 10, 11
`1, 6, 7, 13, 14, 16, 17, 18, 19
`19, 24, 27, 28
`1, 5, 9, 14, 15, 17
`1, 11, 15, 19, 21, 26, 27
`1, 2, 5, 6, 7, 13, 16, 17, 18, 19
`
`See ParkerVision’s Preliminary Infringement Contentions (June 26, 2020) (“Preliminary
`
`Infringement Contentions”) at 2; ParkerVision’s Amended Disclosure of Preliminary Infringement
`
`1
`
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`Contentions (Aug. 27, 2020) (amending asserted priority dates for the Asserted Claims); see also
`
`July 16, 2020 Letter from Ronald Daignault to Jason Choy (“ParkerVision inadvertently included
`
`claim 5 of the ’444 patent as an asserted claim. Accordingly, ParkerVision withdraws claim 5 of
`
`the ’444 patent as an asserted claim from this case.”). Intel accordingly provides its Preliminary
`
`Invalidity Contentions for these claims.
`
`With respect to each Asserted Claim and based on its investigation to date, Intel’s
`
`Preliminary Invalidity Contentions: (1) identify each statutory section relied upon for any
`
`assertion of invalidity; (2) identify items of prior art that anticipate and/or render obvious each
`
`asserted claim; (3) specify whether each such item of prior art (or a combination of the same)
`
`anticipates each asserted claim and/or renders it obvious; (4) include charts identifying where each
`
`element in each asserted claim is disclosed, described, taught, or otherwise inherent in the prior art
`
`(at least under ParkerVision’s apparent interpretation of the claims as shown in its Preliminary
`
`Infringement Contentions); and (5) identify grounds for invalidating the asserted claims based on
`
`35 U.S.C. § 112. See D.I. 34.
`
`II.
`
`RESERVATIONS
`
`Intel reserves the right to amend these Preliminary Invalidity Contentions as permitted by
`
`the Federal Rules of Civil Procedure, the Order Governing Proceedings (D.I. 17), the Scheduling
`
`Order (D.I. 34), including in light of the parties’ positions and the Court’s ruling on claim
`
`construction, and to the extent ParkerVision seeks to add to or amend its Preliminary Infringement
`
`Contentions in any way.
`
`For example, ParkerVision’s Preliminary Infringement Contentions improperly rely on
`
`“information and belief” to allege infringement of multiple limitations of the Asserted Claims.
`
`Such allegations fail to provide the required notice to Intel of ParkerVision’s interpretation of the
`
`Asserted Claims. Intel reserves the right to revise, amend, and/or supplement the information
`2
`
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`
`provided herein if and when ParkerVision supplements its Preliminary Infringement Contentions
`
`with regard to those limitations for which ParkerVision has improperly relied on “information and
`
`belief” to allege infringement.
`
`Nothing in these Preliminary Invalidity Contentions shall be treated as an admission that
`
`Intel’s accused technology meets any limitations of the claims. Intel denies that it infringes any
`
`claim of the Asserted Patents. Nothing stated herein shall be construed as an admission or a waiver
`
`of any particular construction of any claim term. Intel expressly reserves the right to contest any
`
`claim construction asserted by ParkerVision and expressly reserves all non-infringement
`
`arguments.
`
`Intel has provided Preliminary Invalidity Contentions that apply the Asserted Claims in the
`
`way that ParkerVision has applied the Asserted Claims in its Preliminary Infringement
`
`Contentions. To the extent that any prior art reference identified by Intel contains a claim element
`
`that is the same as or similar to an element in an accused product, inclusion of that reference in
`
`Intel’s Preliminary Invalidity Contentions is intended to show that the Asserted Claims are invalid
`
`at least under ParkerVision’s apparent interpretation of the claims and infringement positions and
`
`shall not be deemed a waiver by Intel of any claim construction or non-infringement position. By
`
`including prior art that invalidates the claims of the Asserted Patents based on ParkerVision’s
`
`apparent infringement theories, Intel is neither adopting nor acceding in any manner to
`
`ParkerVision’s infringement theories or any claim construction that ParkerVision may propose
`
`pursuant to those theories. Nothing stated herein shall be treated as an admission or suggestion
`
`that Intel agrees with ParkerVision regarding either the alleged scope of any of the Asserted Claims
`
`or the claim constructions that ParkerVision may seek to advance later in the case.
`
`
`
`3
`
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`Finally, references to the preamble of a claim in these Preliminary Invalidity Contentions
`
`shall not be treated as an admission that the preamble is a limitation of a claim.
`
`III.
`
`INVALIDITY BASED ON PRIOR ART
`A.
`
`Identification of Prior Art References
`
`Subject to the reservation of rights above, Intel identifies herein prior art references that,
`
`under ParkerVision’s apparent infringement theories and/or under any reasonable interpretation of
`
`the Asserted Claims, anticipate and/or render obvious one or more of the Asserted Claims. The
`
`patents/applications, publications, devices, methods, and systems identified are also relevant for
`
`their showing of the state of the art and reasons and motivations for making improvements,
`
`additions, and combinations.
`
`As explained further below, the following prior art patent references, including those listed
`
`in Exhibits 1 to 35, anticipate and/or render obvious one or more Asserted Claims (at least under
`
`ParkerVision’s apparent interpretation of the claims set forth in its Preliminary Infringement
`
`Contentions), and/or illustrate the state of the art at the time of the alleged invention. For published
`
`patent applications, Intel may identify the application and a patent that subsequently issued from
`
`that application. For any citation to a published application, Intel reserves the right to cite to the
`
`corresponding disclosure in the subsequently issued patent and vice versa.
`
`SHORT
`NAME
`Squires
`Cerny
`
`Gehring
`Schiltz
`
`McEwan
`
`Hulkko
`
`
`
`COUNTRY
`
`U.S.
`U.S.
`
`U.S.
`U.S.
`
`U.S.
`
`EP
`
`PATENT
`NUMBER
`3,383,601
`3,716,730
`
`4,944,025
`5,339,459
`
`5,345,471
`
`0643477
`
`4
`
`ISSUE DATE
`
`PATENTEE
`
`May 14, 1968 Squires
`February 13,
`Cerny
`1973
`July 24, 1990 Gehring, et al.
`August 16,
`Schiltz, et al.
`1994
`September 6,
`1994
`March 15,
`1995
`
`Hulkko, J.
`
`McEwan
`
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`
`
`SHORT
`NAME
`Shen 698
`Yu
`
`Andrys
`Sokoler
`Arpaia
`
`Tayloe
`
`COUNTRY
`
`U.S.
`U.S.
`
`U.S.
`U.S.
`U.S.
`
`U.S.
`
`PATENT
`NUMBER
`5,640,698
`5,831,316
`
`6,057,714
`6,073,001
`6,192,225
`
`6,230,000
`
`ISSUE DATE
`
`PATENTEE
`
`June 17, 1997 Shen, et al.
`November 3,
`Yu, et al.
`1998
`May 2, 2000
`June 6, 2000
`February 20,
`2001
`May 8, 2001
`
`Andrsy, et al.
`Sokoler
`Arpaia
`
`Tayloe
`
`As explained further below, the following prior art publications, including those listed in
`
`Exhibits 1 to 35, anticipate and/or render obvious one or more Asserted Claims (at least under
`
`ParkerVision’s apparent interpretation of the claims set forth in its Preliminary Infringement
`
`Contentions), and/or illustrate the state of the art at the time of the alleged invention.
`
`SHORT
`NAME
`DeMaw
`Estabrook
`
`Horowitz
`Wilson
`
`Carr 1992
`Weisskopf
`
`Nozawa
`
`Abidi1
`
`Abidi2
`
`Crols 1995
`
`Avitabile
`
`TITLE
`
`AUTHOR
`
`DATE
`
`Practical RF Design Manual
`The Direct Conversion Receiver:
`Analysis and Design of the Front-End
`Component
`The Art of Electronics (2d ed.)
`A Single-Chip VHF and UHF
`Receiver for Radio Paging
`NE602 Primer
`Subharmonic Sampling of Microwave
`Signal Processing Requirements
`The Merigo Method: SSB Generator/
`Producing a Demodulator
`Low-Power Radio-Frequency IC’s for
`Portable Communications
`Direct-Conversion Radio
`Transceivers for Digital
`Communications
`A Single-Chip 900 MHz CMOS
`Receiver Front-End with a High
`Performance Low-IF Topology
`S-Band Digital Downconverter for
`Radar Applications Based on a GaAs
`MMIC Fast Sample-and-Hold
`
`DeMaw, D.
`Estabrook, P.
`
`1982
`1989
`
`1989
`Horowitz, P.
`December
`Wilson, J.F. et
`1991
`al
`January 1992
`Carr, J.J.
`Weisskopf, P. May 1992
`
`Nozawa, Y.
`
`1993
`
`Abidi, A.
`
`Abidi, A.
`
`Crols, J.
`
`April 1995
`
`December
`1995
`
`December
`1995
`
`Avitabile, G., et
`al.
`
`December
`1996
`
`
`
`5
`
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`

`TITLE
`
`AUTHOR
`
`DATE
`
`
`
`SHORT
`NAME
`Hull
`
`Shen
`
`Avitabile
`
`Carr 1997
`Chen
`
`Razavi
`
`Philips
`SA602A
`Datasheet
`Crols 1997
`Johns
`
`A Direct-Conversion Receiver for
`900 MHz (ISM Band) Spread
`Spectrum Digital Cordless Telephone
`A 900-MHz RF Front-End with
`Integrated Discrete-Time Filtering
`S-Band Digital Downconverter for
`Radar Applications Based on a GaAs
`MMIC Fast Sample-and-Hold
`Using the NE602
`A 0.25-mW Low-Pass Passive Sigma-
`Delta Modulator with Built-In Mixer
`for a 10-MHz IF Input
`Design Considerations for Direct-
`Conversion Receivers
`SA602A Double-Balanced Mixer and
`Oscillator
`
`CMOS Wireless Transceiver Design
`Analog Integrated Circuit Design
`
`Hull, C., et al.
`
`Shen, D.H., et
`al.
`Avitabile, G, et
`al.
`
`December
`1996
`
`December
`1996
`1996
`
`Carr, J.J.
`Chen, G.
`
`February 1997
`June 1997
`
`Razavi, B.
`
`June 1997
`
`Philips
`
`November
`1997
`
`Crols, J.
`Johns, D.A., et
`al.
`Larson, L.E.
`
`1997
`1997
`
`1997
`
`Lee, T.H.
`
`1998, 1999
`
`Texas
`Instruments
`
`December
`1998
`
`Lee1
`
`Larson
`
`RF and Microwave Circuit Design for
`Wireless Communications
`The Design of CMOS Radio-
`Frequency Integrated Circuits
`TI Datasheet SN74CBT3253D
`Dual 1-of-4 FET Multiplexer/
`Demultiplexer
`
`In addition to the above prior art patents and publications, on information and belief, there
`
`are prior art systems that anticipate and/or render obvious one or more Asserted Claims (at least
`
`under ParkerVision’s apparent interpretation of the claims as set forth in its Preliminary
`
`Infringement Contentions), and/or illustrate the state of the art at the time of the alleged invention.
`
`Because fact discovery is stayed until January 29, 2021, (D.I. 34 at 3), Intel is unable to conduct
`
`
`1 For simplicity and to avoid duplication, when “Lee” is referenced in this Cover Pleading and in
`the accompanying Exhibits A-I, “Lee” refers to each of Lee, T.H, The Design of CMOS Radio-
`Frequency Integrated Circuits, Cambridge University Press, 1999 and Lee, T.H., The Design of
`CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, February 1998, which
`are both independently prior art to the Asserted Patents.
`6
`
`
`
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`
`
`discovery to confirm its information and belief. Intel reserves the right to supplement its invalidity
`
`contentions with additional prior art systems once it is able to conduct discovery.
`
`B.
`
`Anticipation Under 35 U.S.C. § 102 and/or “Single Reference” Obviousness
`Under 35 U.S.C. § 103
`
`Subject to the reservation of rights above and based on Intel’s present understanding of the
`
`Asserted Claims and ParkerVision’s apparent interpretation of the Asserted Claims as applied in
`
`its Preliminary Infringement Contentions, the prior art references identified below anticipate
`
`and/or render obvious the Asserted Claims, at least under ParkerVision’s apparent infringement
`
`and claim construction theories. For each of these references, Intel has provided a claim chart to
`
`identify where each element of the Asserted Claims can be found in the prior art listed below, at
`
`least under ParkerVision’s apparent theories. To the extent that a reference cited below does not
`
`anticipate one or more claims of the asserted patent, it alone and/or combined with the knowledge
`
`of a person of ordinary skill in the art at the time of the alleged invention renders those claims
`
`obvious at least under ParkerVision’s apparent theories.
`
`Subject to the reservation of rights above, at least under Intel’s present understanding of
`
`ParkerVision’s apparent positions as to the scope of the Asserted Claims, each of the Asserted
`
`Claims is invalid as anticipated and/or rendered obvious under 35 U.S.C. § 102 and/or § 103 by
`
`at least the following prior art references.
`
`Prior Art Patents
`
`SHORT
`NAME
`Squires
`Cerny
`Gehring
`Schiltz
`McEwan
`Hulkko
`
`
`
`PATENT NUMBER
`
`ISSUE DATE
`
`PATENTEE
`
`U.S. Patent No. 6,230,000 May 14, 1968
`U.S. Patent No. 3,716,730
`February 13, 1973
`U.S. Patent No. 4,944,025
`July 24, 1990
`U.S. Patent No. 5,339,459
`August 16, 1994
`U.S. Patent No. 5,345,471
`September 6, 1994
`EP Patent No. 0643477
`March 15, 1995
`
`Squires
`Cerny
`Gehring, et al.
`Schiltz, et al.
`McEwan
`Nokia Mobile
`Phones Ltd.
`
`7
`
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`

`

`Shen 698
`Andrys
`Sokoler
`Arpaia
`Tayloe
`
`June 17, 1997
`U.S. Patent No. 5,640,698
`U.S. Patent No. 6,057,714 May 2, 2000
`U.S. Patent No. 6,073,001
`June 6, 2000
`U.S. Patent No. 6,192,225
`February 20, 2001
`U.S. Patent No. 6,230,000 May 8, 2001
`
`Shen, et al.
`Andrys, et al.
`Sokoler
`Arpaia
`Tayloe
`
`
`
`
`
`
`
`SHORT
`NAME
`DeMaw
`Estabrook
`
`Wilson
`
`Carr 1992
`Weisskopf
`
`Nozawa
`
`Abidi1
`
`Abidi2
`
`Crols 1995
`
`Avitabile
`
`Hull
`
`Shen
`
`Prior Art Publications
`
`
`AUTHOR
`
`TITLE
`
`Wilson, J.F. et al
`
`Carr, J.J.
`Weisskopf, P.
`
`Nozawa, Y.
`
`Abidi, A.
`
`Abidi, A.
`
`Crols, J.
`
`Avitabile, G., et al.
`
`Practical RF Design Manual DeMaw, D.
`The Direct Conversion
`Estabrook, P.
`Receiver: Analysis and
`Design of the Front-End
`Component
`A Single-Chip VHF and UHF
`Receiver for Radio Paging
`NE602 Primer
`Subharmonic Sampling of
`Microwave Signal Processing
`Requirements
`The Merigo Method: SSB
`Generator/ Producing a
`Demodulator
`Low-Power Radio-Frequency
`IC’s for Portable
`Communications
`Direct-Conversion Radio
`Transceivers for Digital
`Communications
`A Single-Chip 900 MHz
`CMOS Receiver Front-End
`with a High Performance
`Low-IF Topology
`S-Band Digital
`Downconverter for Radar
`Applications Based on a
`GaAs MMIC Fast Sample-
`and-Hold
`A Direct-Conversion
`Receiver for 900 MHz (ISM
`Band) Spread Spectrum
`Digital Cordless Telephone
`A 900-MHz RF Front-End
`with Integrated Discrete-
`Time Filtering
`
`Hull, C., et al.
`
`Shen, D.H., et al.
`
`8
`
`DATE
`
`1982
`1989
`
`December 1991
`
`January 1992
`May 1992
`
`1993
`
`April 1995
`
`December 1995
`
`December 1995
`
`December 1996
`
`December 1996
`
`December 1996
`
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`

`SHORT
`NAME
`Carr 1997
`Chen
`
`Razavi
`
`Philips
`SA602A
`Larson
`
`Crols 1997
`
`Lee
`
`Using the NE602
`A 0.25-mW Low-Pass
`Passive Sigma-Delta
`Modulator with Built-In
`Mixer for a 10-MHz IF Input
`Design Considerations for
`Direct-Conversion Receivers
`SA602A Double-Balanced
`Mixer and Oscillator
`RF and Microwave Circuit
`Design for Wireless
`Communications
`CMOS Wireless Transceiver
`Design
`The Design of CMOS Radio-
`Frequency Integrated Circuits
`TI Datasheet SN74CBT3253D
`Dual 1-of-4 FET Multiplexer/
`Demultiplexer
`
`TITLE
`
`AUTHOR
`
`DATE
`
`Carr, J.J.
`Chen, G.
`
`February 1997
`June 1997
`
`Razavi, B.
`
`Philips
`
`Larson, L.E.
`
`Crols, J.
`
`Lee, T.H.
`
`June 1997
`
`November 1997
`
`1997
`
`1997
`
`1998, 1999
`
`Texas Instruments
`
`December 1998
`
`
`
`
`
`C.
`
`Obviousness Under 35 U.S.C. § 103
`
`To the extent a finder of fact determines that a limitation of an asserted claim was not
`
`disclosed by one of the references identified above, those claims are nevertheless unpatentable as
`
`obvious because the Asserted Claims contain nothing that goes beyond ordinary innovation.
`
`Under any reasonable interpretation of the Asserted Claims, as well as under ParkerVision’s
`
`apparent positions as to the scope of the Asserted Claims, the Asserted Claims are invalid as
`
`obvious under 35 U.S.C. § 103. To the extent not anticipated, no Asserted Claim goes beyond
`
`combining known elements to achieve predictable results or does more than choose between clear
`
`alternatives known to those of skill in the art. These obviousness contentions are provided in the
`
`alternative to Intel’s anticipation contentions and are not to be construed to suggest that any
`
`reference included in the combinations is not itself anticipatory at least under ParkerVision’s
`
`apparent interpretation of the claims as set forth in its Preliminary Infringement Contentions.
`
`
`
`9
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`
`The Asserted Claims are rendered obvious, at least under ParkerVision’s apparent
`
`infringement theories, when considered in view of: (1) information known to persons of ordinary
`
`skill in the art at the time of the alleged invention; (2) any of the other primary prior art references;
`
`(3) any of the additional prior art identified in these contentions; and/or (4) statements in the
`
`intrinsic record of the Asserted Patents. Intel’s claim charts in Exhibits 1-35 identify the
`
`disclosures in other prior art references with which the primary references may be combined to
`
`render the Asserted Claims obvious, at least under ParkerVision’s apparent interpretation of the
`
`claims set forth in its Preliminary Infringement Contentions.
`
`In attached Exhibits A-I, Intel identifies certain references and combinations of references
`
`that, at least under ParkerVision’s apparent infringement and claim construction theories, render
`
`one or more of the Asserted Claims obvious. ParkerVision’s Preliminary Infringement
`
`Contentions allege infringement based on nothing more than “information and belief” for many
`
`elements of the forty-nine asserted claims, and the parties have not yet exchanged proposed terms
`
`for claim construction or proposed constructions. Intel expects to be able to identify the
`
`combinations of references that render one or more of the Asserted Claims obvious with greater
`
`specificity as ParkerVision provides greater specificity regarding its allegations of infringement,
`
`identifies support for those allegations, and the parties and the Court identify and resolve any
`
`disputes regarding the scope of the claims, including through claim construction.
`
`The combinations identified in Exhibits A-I are given merely to illustrate various
`
`combinations and are not intended to provide an exhaustive list of every possible invalidating
`
`combination. Intel reserves its right to identify additional combinations based on the prior art cited
`
`in these contentions. For example, and not by way of limitation, Intel reserves its right to rely on
`
`
`
`10
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`the illustrative teachings of the references cited for particular claim elements in the claim charts
`
`included in Exhibits 1 to 35.
`
`Each of the references cited in these contentions is analogous art to the claimed invention
`
`of the Asserted Patents: (1) each reference is from the same field of endeavor as the Asserted
`
`Patents’ alleged invention (even if the reference addresses a different problem); and/or (2) each
`
`reference is reasonably pertinent to the problem faced by the named inventors of the Asserted
`
`Patents (even if the reference is not in the same field of endeavor as the claimed invention). It
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`therefore would have been obvious for someone of ordinary skill in the art to identify and combine
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`elements from these references and devices.
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`The Supreme Court identified in KSR International Co. v. Teleflex, Inc., 550 U.S. 398
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`(2007) a number of rationales that would support a finding that the Asserted Claims are obvious:
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`A. the claims combine prior art elements according to known methods to yield
`predictable results;
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`B. the claims involve the simple substitution of one known element for another to
`obtain predictable results;
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`C. the claims involve the use of a known technique to improve similar devices
`(methods, or products) in the same way;
`
`D. the claims apply a known technique to a known device (method, or product)
`ready for improvement to yield predictable results;
`
`E. the claims involve combinations of prior art references that would have been
`“obvious to try”—i.e., a person of ordinary skill in the art could have reached
`the Asserted Claims by choosing from a finite number of identified, predictable
`solutions, with a reasonable expectation of success; and/or
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`F. the claims are simply variations of work from one field of endeavor or a
`different one that would have been prompted based on design incentives or
`other market forces because the variations were predictable to one of ordinary
`skill in the art.
`
`KSR, 550 U.S. at 414-18 (rejecting Federal Circuit’s “rigid” application of motivation-to-combine
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`test, and instead espousing “expansive and flexible” approach); see also Examination Guidelines
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`for Determining Obviousness Under 35 U.S.C. 103 in View of the Supreme Court Decision in
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`KSR International Co. v. Teleflex Inc., 72 Fed. Reg. 57,526 (Oct. 10, 2007). The Supreme Court
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`has also held that a person of ordinary skill in the art is “a person of ordinary creativity, not an
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`automaton,” that a motivation to combine may be simply “common sense,” and that “familiar items
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`may have obvious uses beyond their primary purposes, and in many cases a person of ordinary
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`skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” KSR,
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`550 U.S. at 420-21. The Supreme Court further held that it is sufficient that a combination of
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`elements was “obvious to try,” holding that, “[w]hen there is a design need or market pressure to
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`solve a problem and there are a finite number of identified, predictable solutions, a person of
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`ordinary skill has good reason to pursue the known options within his or her technical grasp.” Id.
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`at 421.
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`The various elements of the Asserted Claims were well known in the prior art at the time
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`of the alleged invention, and the use of these features in combination simply: (a) combines prior
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`art elements according to known methods to yield predictable results; (b) involves the simple
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`substitution of one known element for another to obtain predictable results; (c) involves the use of
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`a known technique to improve similar devices (methods or products) in the same way; (d) applies
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`a known technique to a known device, method, or product ready for improvement to yield
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`predictable results; (e) involves combinations of prior art references that would have been “obvious
`
`to try”—i.e., a person of ordinary skill in the art could have reached the Asserted Claims by
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`choosing from a finite number of identified, predictable solutions, with a reasonable expectation
`
`of success; and/or (f) would have been prompted by known work in the field of radio frequency
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`transceiver architecture based on design incentives or other market forces, because such variations
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`were predictable to one of ordinary skill in the art.
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`1.
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`Motivations to Combine
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`A patent claim may also be invalidated as obvious based on a teaching-suggestion-
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`motivation rationale—i.e., that some teaching, suggestion, or motivation would have led one of
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`ordinary skill to modify the prior art reference teachings or to combine the teachings to arrive at
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`the Asserted Patents’ alleged invention. Teachings, suggestions, motivations, and/or reasons to
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`modify or combine elements or disclosures can come from many sources, including the prior art
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`(specific and as a whole), common knowledge, common sense, predictability, expectations,
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`industry trends, design incentives or need, market demand or pressure, market forces, obviousness
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`to try, the nature of the problem faced, and/or knowledge possessed by a person of ordinary skill.
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`Below, Intel identifies certain motivations to combine various teachings in the prior art.
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`These examples are given to illustrate various motivations to combine and are not intended to
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`provide motivations to combine for every cited reference, or to identify an exhaustive set of every
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`possible motivation to combine the references listed below. Intel reserves its right to identify
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`additional motivations to combine and contends that the motivations described below apply to
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`additional combinations.
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`Motivation to Combine Multiple Down-Conversion Modules to Generate Down-Converted
`Signals that Are Opposite (e.g., 180 Degrees out of Phase) to Each Other
`
`
`A person of ordinary skill in the art would have been motivated to combine (1) the
`
`teachings of any of the prior art references cited in these invalidity contentions that have a single
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`down-conversion module that receives an input signal and generates a single down-converted
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`signal with (2) the teachings of any of the cited prior art references that have multiple down-
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`conversion modules that receive an input signal and generate a first down-converted signal and a
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`second down-converted signal that is the inverse or opposite of the first down-converted signal.
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`More specifically, a person of ordinary skill in the art would have been motivated to implement
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`multiple down-conversion modules (rather than a single module) to generate multiple, opposite
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`down-converted signals, because the multiple down-converted signals can be easily combined
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`(e.g., by subtracting one signal from the other signal) to remove undesired, “common mode”
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`portions of the down-converted signals and generate a resultant down-converted signal that does
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`not include these undesired portions.
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`As an illustrative, non-limiting example, a person of ordinary skill in the art would have
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`been motivated to combine the teachings of Shen 698 and/or Schiltz (which disclose, at least in
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`one embodiment, a single down-conversion module that receives an input signal and produces a
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`single down-converted signal) with either Arpaia, Tayloe, and/or Sokoler (which disclose multiple
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`down-conversion modules that receive an input signal and produce multiple down-converted
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`signals that are opposite to each other) to produce a down-converter having multiple modules that
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`generate multiple, opposite down-converted signals.
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`A person of ordinary skill in the art would have been motivated to combine the teachings
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` of Shen 698 and/or Schiltz with Arpaia, Tayloe, and/or Sokoler because the references are all in
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`the same field (radio or carrier frequency receivers) and address the same problem or objective
`
`(obtaining an information signal or baseband signal from a received modulated signal) in similar
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`ways (down-converting or demodulating the received modulated signal to obtain the information
`
`signal or baseband signal). See, e.g., Shen 698 at 1:5-15 (“The present invention relates to radio
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`receivers and methods for the reception of RF (radio frequency) communications signals. In
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`particular, it relates to radio receivers using high-speed discrete-time electronic circuits and
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`methods for RF signal reception using sub-sampling for frequency down conversion.”); Shen 698
`
`at claim 9 (“9. A radio receiver comprising: a receiving means for receiving an RF signal
`
`containing an RF channel of carrier frequency fc within a channel allocation band having
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`bandwidth B; a filtering means for filtering the RF signal to a bandwidth W to yield a band-limited
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`signal, the band-limited signal containing the channel allocation band; a discrete-time sampling
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`means for sampling the band limited signal at a sampling frequency fs to yield an image signal
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`containing an image channel of frequency fi, where fi<fs<fc; a discrete-time down-converting
`
`means for down converting and down-sampling the image signal using sub-sampling to yield a
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`non-zero-frequency, low frequency signal containing a down-converted channel of frequency f.
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`where 0<fk<fi; a discrete-time channel-select filtering means for removing adjacent-channel
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`interference from the low frequency signal to isolate the down-converted channel; and a
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`demodulation means for demodulating the down converted channel to yield a baseband signal.”);
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`Schiltz at 1:6-10 (“The present invention relates generally to high speed electronic circuits. More
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`specifically, the present invention relates to a high speed sample and hold circuit and to radios
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`which use such a circuit as a mixer.”), 3:4-8 (“FIG. 1 shows a block diagram of a radio 10 which
`
`converts one or more RF signals into an IF signal and then into a baseband signal. Radio 10
`
`includes an antenna 12, which provides a first RF signal and an optional antenna 14 which provides
`
`a second RF signal.”); Arpaia at 1:4-10 (“The present invention generally relates to a direct
`
`conversion receiver (or a homodyne receiver) that separates a received radio signal into its in-
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`phase (I) and quadrature (Q) components while also reducing second-order intermodulation
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`products due to non-linearities in the mixers and reducing feedback from the tuned local
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`oscillator.”), 5:31-50 (“FIG. 5 shows another embodiment of the present invention. In this circuit,
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`the received signal is split into four channels and each channel is fed into a separate mixer 3, 3′,
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`3″, 3′″. A local oscillator 4 feeds a sinusoid into each of the mixers 3, 3′, 3″, 3′″. In the top mixer
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`3, the phase of the local oscillator signal is changed by π/2 (i.e., sin(2πf1t)). In the top-middle
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`mixer 3′, the phase of the local oscillator is changed by −π/2 (i.e., −sin(2πf1t). In the bottom-
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`middle mi